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std: Disable some vector-related tests for hexagon.

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See:

* https://github.com/llvm/llvm-project/issues/118879
* https://github.com/llvm/llvm-project/issues/134659
This commit is contained in:
Alex Rønne Petersen 2025-04-07 18:15:31 +02:00
parent 382aa48f04
commit 01b5e8b296
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2 changed files with 4 additions and 1 deletions
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4
lib/std/mem.zig
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@ -431,7 +431,9 @@ test zeroes {
}
try testing.expectEqual(@as(@TypeOf(b.vector_u32), @splat(0)), b.vector_u32);
try testing.expectEqual(@as(@TypeOf(b.vector_f32), @splat(0.0)), b.vector_f32);
try testing.expectEqual(@as(@TypeOf(b.vector_bool), @splat(false)), b.vector_bool);
if (!(builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon)) {
try testing.expectEqual(@as(@TypeOf(b.vector_bool), @splat(false)), b.vector_bool);
}
try testing.expectEqual(@as(?u8, null), b.optional_int);
for (b.sentinel) |e| {
try testing.expectEqual(@as(u8, 0), e);

1
lib/std/simd.zig
View file

@ -464,6 +464,7 @@ test "vector prefix scan" {
if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
if ((builtin.cpu.arch == .armeb or builtin.cpu.arch == .thumbeb) and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/22060
if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/21893
if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;
if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;