update CPU features to LLVM 16

build.zig

@@ -97,6 +97,11 @@ pub fn build(b: *Builder) !void {
         "llvm-has-arc",
         "Whether LLVM has the experimental target arc enabled",
     ) orelse false;
+    const llvm_has_xtensa = b.option(
+        bool,
+        "llvm-has-xtensa",
+        "Whether LLVM has the experimental target xtensa enabled",
+    ) orelse false;
     const enable_macos_sdk = b.option(bool, "enable-macos-sdk", "Run tests requiring presence of macOS SDK and frameworks") orelse false;
     const enable_symlinks_windows = b.option(bool, "enable-symlinks-windows", "Run tests requiring presence of symlinks on Windows") orelse false;
     const config_h_path_option = b.option([]const u8, "config_h", "Path to the generated config.h");
@@ -186,6 +191,7 @@ pub fn build(b: *Builder) !void {
     exe_options.addOption(bool, "llvm_has_m68k", llvm_has_m68k);
     exe_options.addOption(bool, "llvm_has_csky", llvm_has_csky);
     exe_options.addOption(bool, "llvm_has_arc", llvm_has_arc);
+    exe_options.addOption(bool, "llvm_has_xtensa", llvm_has_xtensa);
     exe_options.addOption(bool, "force_gpa", force_gpa);
     exe_options.addOption(bool, "only_c", only_c);
     exe_options.addOption(bool, "omit_pkg_fetching_code", false);
@@ -340,6 +346,7 @@ pub fn build(b: *Builder) !void {
     test_cases_options.addOption(bool, "llvm_has_m68k", llvm_has_m68k);
     test_cases_options.addOption(bool, "llvm_has_csky", llvm_has_csky);
     test_cases_options.addOption(bool, "llvm_has_arc", llvm_has_arc);
+    test_cases_options.addOption(bool, "llvm_has_xtensa", llvm_has_xtensa);
     test_cases_options.addOption(bool, "force_gpa", force_gpa);
     test_cases_options.addOption(bool, "only_c", only_c);
     test_cases_options.addOption(bool, "enable_qemu", b.enable_qemu);

lib/std/target.zig

@@ -459,6 +459,7 @@ pub const Target = struct {
     pub const bpf = @import("target/bpf.zig");
     pub const csky = @import("target/csky.zig");
     pub const hexagon = @import("target/hexagon.zig");
+    pub const loongarch = @import("target/loongarch.zig");
     pub const m68k = @import("target/m68k.zig");
     pub const mips = @import("target/mips.zig");
     pub const msp430 = @import("target/msp430.zig");
@@ -471,6 +472,7 @@ pub const Target = struct {
     pub const ve = @import("target/ve.zig");
     pub const wasm = @import("target/wasm.zig");
     pub const x86 = @import("target/x86.zig");
+    pub const xtensa = @import("target/xtensa.zig");
 
     pub const Abi = enum {
         none,
@@ -1007,6 +1009,7 @@ pub const Target = struct {
                     .thumbeb => .ARM,
                     .x86 => .@"386",
                     .xcore => .XCORE,
+                    .xtensa => .XTENSA,
                     .nvptx => .NONE,
                     .amdil => .NONE,
                     .hsail => .NONE,
@@ -1032,7 +1035,7 @@ pub const Target = struct {
                     .spir64 => .NONE,
                     .wasm64 => .NONE,
                     .renderscript64 => .NONE,
-                    .amdgcn => .NONE,
+                    .amdgcn => .AMDGPU,
                     .bpfel => .BPF,
                     .bpfeb => .BPF,
                     .csky => .CSKY,
@@ -1122,6 +1125,7 @@ pub const Target = struct {
                     .amdil64,
                     .bpfel,
                     .csky,
+                    .xtensa,
                     .hexagon,
                     .hsail,
                     .hsail64,
@@ -1236,6 +1240,7 @@ pub const Target = struct {
                     .spirv32,
                     .loongarch32,
                     .dxil,
+                    .xtensa,
                     => return 32,
 
                     .aarch64,
@@ -1271,6 +1276,7 @@ pub const Target = struct {
                     .arm, .armeb, .thumb, .thumbeb => "arm",
                     .aarch64, .aarch64_be, .aarch64_32 => "aarch64",
                     .bpfel, .bpfeb => "bpf",
+                    .loongarch32, .loongarch64 => "loongarch",
                     .mips, .mipsel, .mips64, .mips64el => "mips",
                     .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
                     .amdgcn => "amdgpu",
@@ -1290,9 +1296,13 @@ pub const Target = struct {
                 return switch (arch) {
                     .arm, .armeb, .thumb, .thumbeb => &arm.all_features,
                     .aarch64, .aarch64_be, .aarch64_32 => &aarch64.all_features,
+                    .arc => &arc.all_features,
                     .avr => &avr.all_features,
                     .bpfel, .bpfeb => &bpf.all_features,
+                    .csky => &csky.all_features,
                     .hexagon => &hexagon.all_features,
+                    .loongarch32, .loongarch64 => &loongarch.all_features,
+                    .m68k => &m68k.all_features,
                     .mips, .mipsel, .mips64, .mips64el => &mips.all_features,
                     .msp430 => &msp430.all_features,
                     .powerpc, .powerpcle, .powerpc64, .powerpc64le => &powerpc.all_features,
@@ -1302,6 +1312,7 @@ pub const Target = struct {
                     .spirv32, .spirv64 => &spirv.all_features,
                     .s390x => &s390x.all_features,
                     .x86, .x86_64 => &x86.all_features,
+                    .xtensa => &xtensa.all_features,
                     .nvptx, .nvptx64 => &nvptx.all_features,
                     .ve => &ve.all_features,
                     .wasm32, .wasm64 => &wasm.all_features,
@@ -1313,11 +1324,15 @@ pub const Target = struct {
             /// All processors Zig is aware of, sorted lexicographically by name.
             pub fn allCpuModels(arch: Arch) []const *const Cpu.Model {
                 return switch (arch) {
+                    .arc => comptime allCpusFromDecls(arc.cpu),
                     .arm, .armeb, .thumb, .thumbeb => comptime allCpusFromDecls(arm.cpu),
                     .aarch64, .aarch64_be, .aarch64_32 => comptime allCpusFromDecls(aarch64.cpu),
                     .avr => comptime allCpusFromDecls(avr.cpu),
                     .bpfel, .bpfeb => comptime allCpusFromDecls(bpf.cpu),
+                    .csky => comptime allCpusFromDecls(csky.cpu),
                     .hexagon => comptime allCpusFromDecls(hexagon.cpu),
+                    .loongarch32, .loongarch64 => comptime allCpusFromDecls(loongarch.cpu),
+                    .m68k => comptime allCpusFromDecls(m68k.cpu),
                     .mips, .mipsel, .mips64, .mips64el => comptime allCpusFromDecls(mips.cpu),
                     .msp430 => comptime allCpusFromDecls(msp430.cpu),
                     .powerpc, .powerpcle, .powerpc64, .powerpc64le => comptime allCpusFromDecls(powerpc.cpu),
@@ -1326,6 +1341,7 @@ pub const Target = struct {
                     .sparc, .sparc64, .sparcel => comptime allCpusFromDecls(sparc.cpu),
                     .s390x => comptime allCpusFromDecls(s390x.cpu),
                     .x86, .x86_64 => comptime allCpusFromDecls(x86.cpu),
+                    .xtensa => comptime allCpusFromDecls(xtensa.cpu),
                     .nvptx, .nvptx64 => comptime allCpusFromDecls(nvptx.cpu),
                     .ve => comptime allCpusFromDecls(ve.cpu),
                     .wasm32, .wasm64 => comptime allCpusFromDecls(wasm.cpu),
@@ -1373,6 +1389,8 @@ pub const Target = struct {
                     .avr => &avr.cpu.avr2,
                     .bpfel, .bpfeb => &bpf.cpu.generic,
                     .hexagon => &hexagon.cpu.generic,
+                    .loongarch32 => &loongarch.cpu.generic_la32,
+                    .loongarch64 => &loongarch.cpu.generic_la64,
                     .m68k => &m68k.cpu.generic,
                     .mips, .mipsel => &mips.cpu.mips32,
                     .mips64, .mips64el => &mips.cpu.mips64,
@@ -1720,6 +1738,7 @@ pub const Target = struct {
                 .dxil,
                 .loongarch32,
                 .loongarch64,
+                .xtensa,
                 => return result,
             },
 
@@ -1884,6 +1903,7 @@ pub const Target = struct {
             .dxil,
             .loongarch32,
             .loongarch64,
+            .xtensa,
             => 16,
         };
     }

lib/std/target/amdgpu.zig

@@ -14,6 +14,7 @@ pub const Feature = enum {
     atomic_fadd_rtn_insts,
     atomic_pk_fadd_no_rtn_insts,
     auto_waitcnt_before_barrier,
+    back_off_barrier,
     ci_insts,
     cumode,
     dl_insts,
@@ -25,6 +26,7 @@ pub const Feature = enum {
     dot6_insts,
     dot7_insts,
     dot8_insts,
+    dot9_insts,
     dpp,
     dpp8,
     dpp_64bit,
@@ -34,6 +36,7 @@ pub const Feature = enum {
     fast_denormal_f32,
     fast_fmaf,
     flat_address_space,
+    flat_atomic_fadd_f32_inst,
     flat_for_global,
     flat_global_insts,
     flat_inst_offsets,
@@ -41,6 +44,7 @@ pub const Feature = enum {
     flat_scratch_insts,
     flat_segment_offset_bug,
     fma_mix_insts,
+    fmacf64_inst,
     fmaf,
     fp64,
     fp8_insts,
@@ -54,6 +58,7 @@ pub const Feature = enum {
     gfx10_b_encoding,
     gfx10_insts,
     gfx11,
+    gfx11_full_vgprs,
     gfx11_insts,
     gfx7_gfx8_gfx9_insts,
     gfx8_insts,
@@ -75,6 +80,7 @@ pub const Feature = enum {
     load_store_opt,
     localmemorysize32768,
     localmemorysize65536,
+    mad_intra_fwd_bug,
     mad_mac_f32_insts,
     mad_mix_insts,
     mai_insts,
@@ -130,6 +136,7 @@ pub const Feature = enum {
     unpacked_d16_vmem,
     unsafe_ds_offset_folding,
     user_sgpr_init16_bug,
+    valu_trans_use_hazard,
     vcmpx_exec_war_hazard,
     vcmpx_permlane_hazard,
     vgpr_index_mode,
@@ -162,7 +169,7 @@ pub const all_features = blk: {
     };
     result[@enumToInt(Feature.a16)] = .{
         .llvm_name = "a16",
-        .description = "Support gfx10-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands",
+        .description = "Support A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@enumToInt(Feature.add_no_carry_insts)] = .{
@@ -206,6 +213,11 @@ pub const all_features = blk: {
         .description = "Hardware automatically inserts waitcnt before barrier",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.back_off_barrier)] = .{
+        .llvm_name = "back-off-barrier",
+        .description = "Hardware supports backing off s_barrier if an exception occurs",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.ci_insts)] = .{
         .llvm_name = "ci-insts",
         .description = "Additional instructions for CI+",
@@ -258,7 +270,12 @@ pub const all_features = blk: {
     };
     result[@enumToInt(Feature.dot8_insts)] = .{
         .llvm_name = "dot8-insts",
-        .description = "Has v_dot2_f16_f16, v_dot2_bf16_bf16, v_dot2_f32_bf16, v_dot4_i32_iu8, v_dot8_i32_iu4 instructions",
+        .description = "Has v_dot4_i32_iu8, v_dot8_i32_iu4 instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.dot9_insts)] = .{
+        .llvm_name = "dot9-insts",
+        .description = "Has v_dot2_f16_f16, v_dot2_bf16_bf16, v_dot2_f32_bf16 instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@enumToInt(Feature.dpp)] = .{
@@ -306,6 +323,11 @@ pub const all_features = blk: {
         .description = "Support flat address space",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.flat_atomic_fadd_f32_inst)] = .{
+        .llvm_name = "flat-atomic-fadd-f32-inst",
+        .description = "Has flat_atomic_add_f32 instruction",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.flat_for_global)] = .{
         .llvm_name = "flat-for-global",
         .description = "Force to generate flat instruction for global",
@@ -341,6 +363,11 @@ pub const all_features = blk: {
         .description = "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.fmacf64_inst)] = .{
+        .llvm_name = "fmacf64-inst",
+        .description = "Has v_fmac_f64 instruction",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.fmaf)] = .{
         .llvm_name = "fmaf",
         .description = "Enable single precision FMA (not as fast as mul+add, but fused)",
@@ -487,6 +514,11 @@ pub const all_features = blk: {
             .vscnt,
         }),
     };
+    result[@enumToInt(Feature.gfx11_full_vgprs)] = .{
+        .llvm_name = "gfx11-full-vgprs",
+        .description = "GFX11 with 50% more physical VGPRs and 50% larger allocation granule than GFX10",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.gfx11_insts)] = .{
         .llvm_name = "gfx11-insts",
         .description = "Additional instructions for GFX11+",
@@ -507,6 +539,7 @@ pub const all_features = blk: {
         .description = "GFX9 GPU generation",
         .dependencies = featureSet(&[_]Feature{
             .@"16_bit_insts",
+            .a16,
             .add_no_carry_insts,
             .aperture_regs,
             .ci_insts,
@@ -629,6 +662,11 @@ pub const all_features = blk: {
         .description = "The size of local memory in bytes",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.mad_intra_fwd_bug)] = .{
+        .llvm_name = "mad-intra-fwd-bug",
+        .description = "MAD_U64/I64 intra instruction forwarding bug",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.mad_mac_f32_insts)] = .{
         .llvm_name = "mad-mac-f32-insts",
         .description = "Has v_mad_f32/v_mac_f32/v_madak_f32/v_madmk_f32 instructions",
@@ -933,6 +971,11 @@ pub const all_features = blk: {
         .description = "Bug requiring at least 16 user+system SGPRs to be enabled",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.valu_trans_use_hazard)] = .{
+        .llvm_name = "valu-trans-use-hazard",
+        .description = "Hazard when TRANS instructions are closely followed by a use of the result",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.vcmpx_exec_war_hazard)] = .{
         .llvm_name = "vcmpx-exec-war-hazard",
         .description = "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)",
@@ -1089,6 +1132,7 @@ pub const cpu = struct {
         .name = "gfx1010",
         .llvm_name = "gfx1010",
         .features = featureSet(&[_]Feature{
+            .back_off_barrier,
             .dl_insts,
             .ds_src2_insts,
             .flat_segment_offset_bug,
@@ -1120,6 +1164,7 @@ pub const cpu = struct {
         .name = "gfx1011",
         .llvm_name = "gfx1011",
         .features = featureSet(&[_]Feature{
+            .back_off_barrier,
             .dl_insts,
             .dot1_insts,
             .dot2_insts,
@@ -1156,6 +1201,7 @@ pub const cpu = struct {
         .name = "gfx1012",
         .llvm_name = "gfx1012",
         .features = featureSet(&[_]Feature{
+            .back_off_barrier,
             .dl_insts,
             .dot1_insts,
             .dot2_insts,
@@ -1192,6 +1238,7 @@ pub const cpu = struct {
         .name = "gfx1013",
         .llvm_name = "gfx1013",
         .features = featureSet(&[_]Feature{
+            .back_off_barrier,
             .dl_insts,
             .ds_src2_insts,
             .flat_segment_offset_bug,
@@ -1224,6 +1271,7 @@ pub const cpu = struct {
         .name = "gfx1030",
         .llvm_name = "gfx1030",
         .features = featureSet(&[_]Feature{
+            .back_off_barrier,
             .dl_insts,
             .dot1_insts,
             .dot2_insts,
@@ -1245,6 +1293,7 @@ pub const cpu = struct {
         .name = "gfx1031",
         .llvm_name = "gfx1031",
         .features = featureSet(&[_]Feature{
+            .back_off_barrier,
             .dl_insts,
             .dot1_insts,
             .dot2_insts,
@@ -1266,6 +1315,7 @@ pub const cpu = struct {
         .name = "gfx1032",
         .llvm_name = "gfx1032",
         .features = featureSet(&[_]Feature{
+            .back_off_barrier,
             .dl_insts,
             .dot1_insts,
             .dot2_insts,
@@ -1287,6 +1337,7 @@ pub const cpu = struct {
         .name = "gfx1033",
         .llvm_name = "gfx1033",
         .features = featureSet(&[_]Feature{
+            .back_off_barrier,
             .dl_insts,
             .dot1_insts,
             .dot2_insts,
@@ -1308,6 +1359,7 @@ pub const cpu = struct {
         .name = "gfx1034",
         .llvm_name = "gfx1034",
         .features = featureSet(&[_]Feature{
+            .back_off_barrier,
             .dl_insts,
             .dot1_insts,
             .dot2_insts,
@@ -1329,6 +1381,7 @@ pub const cpu = struct {
         .name = "gfx1035",
         .llvm_name = "gfx1035",
         .features = featureSet(&[_]Feature{
+            .back_off_barrier,
             .dl_insts,
             .dot1_insts,
             .dot2_insts,
@@ -1350,6 +1403,7 @@ pub const cpu = struct {
         .name = "gfx1036",
         .llvm_name = "gfx1036",
         .features = featureSet(&[_]Feature{
+            .back_off_barrier,
             .dl_insts,
             .dot1_insts,
             .dot2_insts,
@@ -1378,14 +1432,19 @@ pub const cpu = struct {
             .dot5_insts,
             .dot7_insts,
             .dot8_insts,
+            .dot9_insts,
+            .flat_atomic_fadd_f32_inst,
             .gfx11,
+            .gfx11_full_vgprs,
             .image_insts,
             .ldsbankcount32,
+            .mad_intra_fwd_bug,
             .nsa_encoding,
             .nsa_max_size_5,
             .packed_tid,
             .shader_cycles_register,
             .user_sgpr_init16_bug,
+            .valu_trans_use_hazard,
             .vcmpx_permlane_hazard,
             .wavefrontsize32,
         }),
@@ -1401,13 +1460,18 @@ pub const cpu = struct {
             .dot5_insts,
             .dot7_insts,
             .dot8_insts,
+            .dot9_insts,
+            .flat_atomic_fadd_f32_inst,
             .gfx11,
+            .gfx11_full_vgprs,
             .image_insts,
             .ldsbankcount32,
+            .mad_intra_fwd_bug,
             .nsa_encoding,
             .nsa_max_size_5,
             .packed_tid,
             .shader_cycles_register,
+            .valu_trans_use_hazard,
             .vcmpx_permlane_hazard,
             .wavefrontsize32,
         }),
@@ -1423,14 +1487,18 @@ pub const cpu = struct {
             .dot5_insts,
             .dot7_insts,
             .dot8_insts,
+            .dot9_insts,
+            .flat_atomic_fadd_f32_inst,
             .gfx11,
             .image_insts,
             .ldsbankcount32,
+            .mad_intra_fwd_bug,
             .nsa_encoding,
             .nsa_max_size_5,
             .packed_tid,
             .shader_cycles_register,
             .user_sgpr_init16_bug,
+            .valu_trans_use_hazard,
             .vcmpx_permlane_hazard,
             .wavefrontsize32,
         }),
@@ -1446,14 +1514,17 @@ pub const cpu = struct {
             .dot5_insts,
             .dot7_insts,
             .dot8_insts,
+            .dot9_insts,
+            .flat_atomic_fadd_f32_inst,
             .gfx11,
             .image_insts,
             .ldsbankcount32,
+            .mad_intra_fwd_bug,
             .nsa_encoding,
             .nsa_max_size_5,
             .packed_tid,
             .shader_cycles_register,
-            .user_sgpr_init16_bug,
+            .valu_trans_use_hazard,
             .vcmpx_permlane_hazard,
             .wavefrontsize32,
         }),
@@ -1696,6 +1767,7 @@ pub const cpu = struct {
             .atomic_fadd_no_rtn_insts,
             .atomic_fadd_rtn_insts,
             .atomic_pk_fadd_no_rtn_insts,
+            .back_off_barrier,
             .dl_insts,
             .dot1_insts,
             .dot2_insts,
@@ -1706,6 +1778,7 @@ pub const cpu = struct {
             .dot7_insts,
             .dpp_64bit,
             .fma_mix_insts,
+            .fmacf64_inst,
             .full_rate_64_ops,
             .gfx9,
             .gfx90a_insts,
@@ -1741,6 +1814,7 @@ pub const cpu = struct {
             .atomic_fadd_no_rtn_insts,
             .atomic_fadd_rtn_insts,
             .atomic_pk_fadd_no_rtn_insts,
+            .back_off_barrier,
             .dl_insts,
             .dot1_insts,
             .dot2_insts,
@@ -1750,7 +1824,9 @@ pub const cpu = struct {
             .dot6_insts,
             .dot7_insts,
             .dpp_64bit,
+            .flat_atomic_fadd_f32_inst,
             .fma_mix_insts,
+            .fmacf64_inst,
             .fp8_insts,
             .full_rate_64_ops,
             .gfx9,

lib/std/target/arm.zig

@@ -17,6 +17,7 @@ pub const Feature = enum {
     avoid_movs_shop,
     avoid_partial_cpsr,
     bf16,
+    big_endian_instructions,
     cde,
     cdecp0,
     cdecp1,
@@ -27,6 +28,7 @@ pub const Feature = enum {
     cdecp6,
     cdecp7,
     cheap_predicable_cpsr,
+    clrbhb,
     crc,
     crypto,
     d32,
@@ -77,11 +79,13 @@ pub const Feature = enum {
     has_v8_6a,
     has_v8_7a,
     has_v8_8a,
+    has_v8_9a,
     has_v8m,
     has_v8m_main,
     has_v9_1a,
     has_v9_2a,
     has_v9_3a,
+    has_v9_4a,
     has_v9a,
     hwdiv,
     hwdiv_arm,
@@ -171,6 +175,7 @@ pub const Feature = enum {
     v8_6a,
     v8_7a,
     v8_8a,
+    v8_9a,
     v8a,
     v8m,
     v8m_main,
@@ -178,6 +183,7 @@ pub const Feature = enum {
     v9_1a,
     v9_2a,
     v9_3a,
+    v9_4a,
     v9a,
     vfp2,
     vfp2sp,
@@ -274,6 +280,11 @@ pub const all_features = blk: {
             .neon,
         }),
     };
+    result[@enumToInt(Feature.big_endian_instructions)] = .{
+        .llvm_name = "big-endian-instructions",
+        .description = "Expect instructions to be stored big-endian.",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.cde)] = .{
         .llvm_name = "cde",
         .description = "Support CDE instructions",
@@ -342,6 +353,11 @@ pub const all_features = blk: {
         .description = "Disable +1 predication cost for instructions updating CPSR",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.clrbhb)] = .{
+        .llvm_name = "clrbhb",
+        .description = "Enable Clear BHB instruction",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.crc)] = .{
         .llvm_name = "crc",
         .description = "Enable support for CRC instructions",
@@ -681,6 +697,14 @@ pub const all_features = blk: {
             .has_v8_7a,
         }),
     };
+    result[@enumToInt(Feature.has_v8_9a)] = .{
+        .llvm_name = "v8.9a",
+        .description = "Support ARM v8.9a instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .clrbhb,
+            .has_v8_8a,
+        }),
+    };
     result[@enumToInt(Feature.has_v8m)] = .{
         .llvm_name = "v8m",
         .description = "Support ARM v8M Baseline instructions",
@@ -719,6 +743,14 @@ pub const all_features = blk: {
             .has_v9_2a,
         }),
     };
+    result[@enumToInt(Feature.has_v9_4a)] = .{
+        .llvm_name = "v9.4a",
+        .description = "Support ARM v9.4a instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .has_v8_9a,
+            .has_v9_3a,
+        }),
+    };
     result[@enumToInt(Feature.has_v9a)] = .{
         .llvm_name = "v9a",
         .description = "Support ARM v9a instructions",
@@ -1027,28 +1059,28 @@ pub const all_features = blk: {
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@enumToInt(Feature.v2)] = .{
-        .llvm_name = "armv2",
+        .llvm_name = null,
         .description = "ARMv2 architecture",
         .dependencies = featureSet(&[_]Feature{
             .strict_align,
         }),
     };
     result[@enumToInt(Feature.v2a)] = .{
-        .llvm_name = "armv2a",
+        .llvm_name = null,
         .description = "ARMv2a architecture",
         .dependencies = featureSet(&[_]Feature{
             .strict_align,
         }),
     };
     result[@enumToInt(Feature.v3)] = .{
-        .llvm_name = "armv3",
+        .llvm_name = null,
         .description = "ARMv3 architecture",
         .dependencies = featureSet(&[_]Feature{
             .strict_align,
         }),
     };
     result[@enumToInt(Feature.v3m)] = .{
-        .llvm_name = "armv3m",
+        .llvm_name = null,
         .description = "ARMv3m architecture",
         .dependencies = featureSet(&[_]Feature{
             .strict_align,
@@ -1384,6 +1416,23 @@ pub const all_features = blk: {
             .virtualization,
         }),
     };
+    result[@enumToInt(Feature.v8_9a)] = .{
+        .llvm_name = "armv8.9-a",
+        .description = "ARMv89a architecture",
+        .dependencies = featureSet(&[_]Feature{
+            .aclass,
+            .crc,
+            .crypto,
+            .db,
+            .dsp,
+            .fp_armv8,
+            .has_v8_9a,
+            .mp,
+            .ras,
+            .trustzone,
+            .virtualization,
+        }),
+    };
     result[@enumToInt(Feature.v8a)] = .{
         .llvm_name = "armv8-a",
         .description = "ARMv8a architecture",
@@ -1495,6 +1544,22 @@ pub const all_features = blk: {
             .virtualization,
         }),
     };
+    result[@enumToInt(Feature.v9_4a)] = .{
+        .llvm_name = "armv9.4-a",
+        .description = "ARMv94a architecture",
+        .dependencies = featureSet(&[_]Feature{
+            .aclass,
+            .crc,
+            .db,
+            .dsp,
+            .fp_armv8,
+            .has_v9_4a,
+            .mp,
+            .ras,
+            .trustzone,
+            .virtualization,
+        }),
+    };
     result[@enumToInt(Feature.v9a)] = .{
         .llvm_name = "armv9-a",
         .description = "ARMv9a architecture",

lib/std/target/avr.zig

@@ -30,6 +30,7 @@ pub const Feature = enum {
     memmappedregs,
     movw,
     mul,
+    progmem,
     rmw,
     smallstack,
     special,
@@ -68,6 +69,7 @@ pub const all_features = blk: {
             .avr0,
             .lpm,
             .memmappedregs,
+            .progmem,
         }),
     };
     result[@enumToInt(Feature.avr2)] = .{
@@ -156,6 +158,7 @@ pub const all_features = blk: {
         .description = "The device is a part of the avr6 family",
         .dependencies = featureSet(&[_]Feature{
             .avr51,
+            .eijmpcall,
         }),
     };
     result[@enumToInt(Feature.avrtiny)] = .{
@@ -229,6 +232,11 @@ pub const all_features = blk: {
         .description = "The device supports the multiplication instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.progmem)] = .{
+        .llvm_name = "progmem",
+        .description = "The device has a separate flash namespace",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.rmw)] = .{
         .llvm_name = "rmw",
         .description = "The device supports the read-write-modify instructions: XCH, LAS, LAC, LAT",
@@ -299,6 +307,7 @@ pub const all_features = blk: {
             .lpmx,
             .movw,
             .mul,
+            .progmem,
             .spm,
             .spmx,
             .sram,
@@ -317,6 +326,7 @@ pub const all_features = blk: {
             .lpmx,
             .movw,
             .mul,
+            .progmem,
             .sram,
         }),
     };

lib/std/target/csky.zig

@@ -3075,7 +3075,9 @@ pub const cpu = struct {
     pub const generic = CpuModel{
         .name = "generic",
         .llvm_name = "generic",
-        .features = featureSet(&[_]Feature{}),
+        .features = featureSet(&[_]Feature{
+            .btst16,
+        }),
     };
     pub const @"i805" = CpuModel{
         .name = "i805",

lib/std/target/hexagon.zig

@@ -21,6 +21,8 @@ pub const Feature = enum {
     hvxv67,
     hvxv68,
     hvxv69,
+    hvxv71,
+    hvxv73,
     long_calls,
     mem_noshuf,
     memops,
@@ -42,6 +44,8 @@ pub const Feature = enum {
     v67,
     v68,
     v69,
+    v71,
+    v73,
     zreg,
 };
 
@@ -153,6 +157,20 @@ pub const all_features = blk: {
             .hvxv68,
         }),
     };
+    result[@enumToInt(Feature.hvxv71)] = .{
+        .llvm_name = "hvxv71",
+        .description = "Hexagon HVX instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .hvxv69,
+        }),
+    };
+    result[@enumToInt(Feature.hvxv73)] = .{
+        .llvm_name = "hvxv73",
+        .description = "Hexagon HVX instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .hvxv71,
+        }),
+    };
     result[@enumToInt(Feature.long_calls)] = .{
         .llvm_name = "long-calls",
         .description = "Use constant-extended calls",
@@ -262,6 +280,16 @@ pub const all_features = blk: {
         .description = "Enable Hexagon V69 architecture",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.v71)] = .{
+        .llvm_name = "v71",
+        .description = "Enable Hexagon V71 architecture",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.v73)] = .{
+        .llvm_name = "v73",
+        .description = "Enable Hexagon V73 architecture",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.zreg)] = .{
         .llvm_name = "zreg",
         .description = "Hexagon ZReg extension instructions",
@@ -484,4 +512,75 @@ pub const cpu = struct {
             .v69,
         }),
     };
+    pub const hexagonv71 = CpuModel{
+        .name = "hexagonv71",
+        .llvm_name = "hexagonv71",
+        .features = featureSet(&[_]Feature{
+            .cabac,
+            .compound,
+            .duplex,
+            .mem_noshuf,
+            .memops,
+            .nvj,
+            .nvs,
+            .small_data,
+            .v5,
+            .v55,
+            .v60,
+            .v62,
+            .v65,
+            .v66,
+            .v67,
+            .v68,
+            .v69,
+            .v71,
+        }),
+    };
+    pub const hexagonv71t = CpuModel{
+        .name = "hexagonv71t",
+        .llvm_name = "hexagonv71t",
+        .features = featureSet(&[_]Feature{
+            .audio,
+            .compound,
+            .mem_noshuf,
+            .memops,
+            .nvs,
+            .small_data,
+            .tinycore,
+            .v5,
+            .v55,
+            .v60,
+            .v62,
+            .v65,
+            .v66,
+            .v67,
+            .v68,
+            .v69,
+            .v71,
+        }),
+    };
+    pub const hexagonv73 = CpuModel{
+        .name = "hexagonv73",
+        .llvm_name = "hexagonv73",
+        .features = featureSet(&[_]Feature{
+            .compound,
+            .duplex,
+            .mem_noshuf,
+            .memops,
+            .nvj,
+            .nvs,
+            .small_data,
+            .v5,
+            .v55,
+            .v60,
+            .v62,
+            .v65,
+            .v66,
+            .v67,
+            .v68,
+            .v69,
+            .v71,
+            .v73,
+        }),
+    };
 };

lib/std/target/loongarch.zig

@@ -0,0 +1,129 @@
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
+const std = @import("../std.zig");
+const CpuFeature = std.Target.Cpu.Feature;
+const CpuModel = std.Target.Cpu.Model;
+
+pub const Feature = enum {
+    @"32bit",
+    @"64bit",
+    d,
+    f,
+    la_global_with_abs,
+    la_global_with_pcrel,
+    la_local_with_abs,
+    lasx,
+    lbt,
+    lsx,
+    lvz,
+};
+
+pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;
+pub const featureSetHas = CpuFeature.feature_set_fns(Feature).featureSetHas;
+pub const featureSetHasAny = CpuFeature.feature_set_fns(Feature).featureSetHasAny;
+pub const featureSetHasAll = CpuFeature.feature_set_fns(Feature).featureSetHasAll;
+
+pub const all_features = blk: {
+    const len = @typeInfo(Feature).Enum.fields.len;
+    std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
+    var result: [len]CpuFeature = undefined;
+    result[@enumToInt(Feature.@"32bit")] = .{
+        .llvm_name = "32bit",
+        .description = "LA32 Basic Integer and Privilege Instruction Set",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.@"64bit")] = .{
+        .llvm_name = "64bit",
+        .description = "LA64 Basic Integer and Privilege Instruction Set",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.d)] = .{
+        .llvm_name = "d",
+        .description = "'D' (Double-Precision Floating-Point)",
+        .dependencies = featureSet(&[_]Feature{
+            .f,
+        }),
+    };
+    result[@enumToInt(Feature.f)] = .{
+        .llvm_name = "f",
+        .description = "'F' (Single-Precision Floating-Point)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.la_global_with_abs)] = .{
+        .llvm_name = "la-global-with-abs",
+        .description = "Expand la.global as la.abs",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.la_global_with_pcrel)] = .{
+        .llvm_name = "la-global-with-pcrel",
+        .description = "Expand la.global as la.pcrel",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.la_local_with_abs)] = .{
+        .llvm_name = "la-local-with-abs",
+        .description = "Expand la.local as la.abs",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.lasx)] = .{
+        .llvm_name = "lasx",
+        .description = "'LASX' (Loongson Advanced SIMD Extension)",
+        .dependencies = featureSet(&[_]Feature{
+            .lsx,
+        }),
+    };
+    result[@enumToInt(Feature.lbt)] = .{
+        .llvm_name = "lbt",
+        .description = "'LBT' (Loongson Binary Translation Extension)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.lsx)] = .{
+        .llvm_name = "lsx",
+        .description = "'LSX' (Loongson SIMD Extension)",
+        .dependencies = featureSet(&[_]Feature{
+            .d,
+        }),
+    };
+    result[@enumToInt(Feature.lvz)] = .{
+        .llvm_name = "lvz",
+        .description = "'LVZ' (Loongson Virtualization Extension)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    const ti = @typeInfo(Feature);
+    for (result) |*elem, i| {
+        elem.index = i;
+        elem.name = ti.Enum.fields[i].name;
+    }
+    break :blk result;
+};
+
+pub const cpu = struct {
+    pub const generic = CpuModel{
+        .name = "generic",
+        .llvm_name = "generic",
+        .features = featureSet(&[_]Feature{}),
+    };
+    pub const generic_la32 = CpuModel{
+        .name = "generic_la32",
+        .llvm_name = "generic-la32",
+        .features = featureSet(&[_]Feature{
+            .@"32bit",
+        }),
+    };
+    pub const generic_la64 = CpuModel{
+        .name = "generic_la64",
+        .llvm_name = "generic-la64",
+        .features = featureSet(&[_]Feature{
+            .@"64bit",
+        }),
+    };
+    pub const la464 = CpuModel{
+        .name = "la464",
+        .llvm_name = "la464",
+        .features = featureSet(&[_]Feature{
+            .@"64bit",
+            .lasx,
+            .lbt,
+            .lvz,
+        }),
+    };
+};

lib/std/target/nvptx.zig

@@ -22,6 +22,9 @@ pub const Feature = enum {
     ptx73,
     ptx74,
     ptx75,
+    ptx76,
+    ptx77,
+    ptx78,
     sm_20,
     sm_21,
     sm_30,
@@ -39,6 +42,9 @@ pub const Feature = enum {
     sm_75,
     sm_80,
     sm_86,
+    sm_87,
+    sm_89,
+    sm_90,
 };
 
 pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;
@@ -135,6 +141,21 @@ pub const all_features = blk: {
         .description = "Use PTX version 7.5",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.ptx76)] = .{
+        .llvm_name = "ptx76",
+        .description = "Use PTX version 7.6",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.ptx77)] = .{
+        .llvm_name = "ptx77",
+        .description = "Use PTX version 7.7",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.ptx78)] = .{
+        .llvm_name = "ptx78",
+        .description = "Use PTX version 7.8",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.sm_20)] = .{
         .llvm_name = "sm_20",
         .description = "Target SM 2.0",
@@ -220,6 +241,21 @@ pub const all_features = blk: {
         .description = "Target SM 8.6",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.sm_87)] = .{
+        .llvm_name = "sm_87",
+        .description = "Target SM 8.7",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.sm_89)] = .{
+        .llvm_name = "sm_89",
+        .description = "Target SM 8.9",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.sm_90)] = .{
+        .llvm_name = "sm_90",
+        .description = "Target SM 9.0",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     const ti = @typeInfo(Feature);
     for (result) |*elem, i| {
         elem.index = i;
@@ -233,6 +269,7 @@ pub const cpu = struct {
         .name = "sm_20",
         .llvm_name = "sm_20",
         .features = featureSet(&[_]Feature{
+            .ptx32,
             .sm_20,
         }),
     };
@@ -240,6 +277,7 @@ pub const cpu = struct {
         .name = "sm_21",
         .llvm_name = "sm_21",
         .features = featureSet(&[_]Feature{
+            .ptx32,
             .sm_21,
         }),
     };
@@ -262,6 +300,7 @@ pub const cpu = struct {
         .name = "sm_35",
         .llvm_name = "sm_35",
         .features = featureSet(&[_]Feature{
+            .ptx32,
             .sm_35,
         }),
     };
@@ -361,4 +400,28 @@ pub const cpu = struct {
             .sm_86,
         }),
     };
+    pub const sm_87 = CpuModel{
+        .name = "sm_87",
+        .llvm_name = "sm_87",
+        .features = featureSet(&[_]Feature{
+            .ptx74,
+            .sm_87,
+        }),
+    };
+    pub const sm_89 = CpuModel{
+        .name = "sm_89",
+        .llvm_name = "sm_89",
+        .features = featureSet(&[_]Feature{
+            .ptx78,
+            .sm_89,
+        }),
+    };
+    pub const sm_90 = CpuModel{
+        .name = "sm_90",
+        .llvm_name = "sm_90",
+        .features = featureSet(&[_]Feature{
+            .ptx78,
+            .sm_90,
+        }),
+    };
 };

lib/std/target/powerpc.zig

@@ -19,6 +19,7 @@ pub const Feature = enum {
     e500,
     efpu2,
     extdiv,
+    fast_MFLR,
     fcpsgn,
     float128,
     fpcvt,
@@ -176,6 +177,11 @@ pub const all_features = blk: {
         .description = "Enable extended divide instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.fast_MFLR)] = .{
+        .llvm_name = "fast-MFLR",
+        .description = "MFLR is a fast instruction",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.fcpsgn)] = .{
         .llvm_name = "fcpsgn",
         .description = "Enable the fcpsgn instruction",
@@ -787,6 +793,7 @@ pub const cpu = struct {
             .crypto,
             .direct_move,
             .extdiv,
+            .fast_MFLR,
             .fcpsgn,
             .fpcvt,
             .fprnd,
@@ -941,6 +948,7 @@ pub const cpu = struct {
             .crypto,
             .direct_move,
             .extdiv,
+            .fast_MFLR,
             .fcpsgn,
             .fpcvt,
             .fprnd,

lib/std/target/riscv.zig

@@ -5,22 +5,26 @@ const CpuFeature = std.Target.Cpu.Feature;
 const CpuModel = std.Target.Cpu.Model;
 
 pub const Feature = enum {
+    @"32bit",
     @"64bit",
     a,
     c,
     d,
     e,
-    experimental_zbe,
+    experimental_zawrs,
-    experimental_zbf,
+    experimental_zca,
-    experimental_zbm,
+    experimental_zcd,
-    experimental_zbp,
+    experimental_zcf,
-    experimental_zbr,
+    experimental_zihintntl,
-    experimental_zbt,
+    experimental_ztso,
     experimental_zvfh,
     f,
+    forced_atomics,
+    h,
     lui_addi_fusion,
     m,
     no_default_unroll,
+    no_optimized_zero_stride_load,
     no_rvc_hints,
     relax,
     reserve_x1,
@@ -55,8 +59,15 @@ pub const Feature = enum {
     reserve_x8,
     reserve_x9,
     save_restore,
+    short_forward_branch_opt,
+    svinval,
+    svnapot,
+    svpbmt,
+    tagged_globals,
     unaligned_scalar_mem,
     v,
+    xtheadvdot,
+    xventanacondops,
     zba,
     zbb,
     zbc,
@@ -100,6 +111,7 @@ pub const Feature = enum {
     zvl4096b,
     zvl512b,
     zvl64b,
+    zvl65536b,
     zvl8192b,
 };
 
@@ -112,6 +124,11 @@ pub const all_features = blk: {
     const len = @typeInfo(Feature).Enum.fields.len;
     std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
     var result: [len]CpuFeature = undefined;
+    result[@enumToInt(Feature.@"32bit")] = .{
+        .llvm_name = "32bit",
+        .description = "Implements RV32",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.@"64bit")] = .{
         .llvm_name = "64bit",
         .description = "Implements RV64",
@@ -139,34 +156,34 @@ pub const all_features = blk: {
         .description = "Implements RV32E (provides 16 rather than 32 GPRs)",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@enumToInt(Feature.experimental_zbe)] = .{
+    result[@enumToInt(Feature.experimental_zawrs)] = .{
-        .llvm_name = "experimental-zbe",
+        .llvm_name = "experimental-zawrs",
-        .description = "'Zbe' (Extract-Deposit 'Zb' Instructions)",
+        .description = "'Zawrs' (Wait on Reservation Set)",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@enumToInt(Feature.experimental_zbf)] = .{
+    result[@enumToInt(Feature.experimental_zca)] = .{
-        .llvm_name = "experimental-zbf",
+        .llvm_name = "experimental-zca",
-        .description = "'Zbf' (Bit-Field 'Zb' Instructions)",
+        .description = "'Zca' (part of the C extension, excluding compressed floating point loads/stores)",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@enumToInt(Feature.experimental_zbm)] = .{
+    result[@enumToInt(Feature.experimental_zcd)] = .{
-        .llvm_name = "experimental-zbm",
+        .llvm_name = "experimental-zcd",
-        .description = "'Zbm' (Matrix 'Zb' Instructions)",
+        .description = "'Zcd' (Compressed Double-Precision Floating-Point Instructions)",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@enumToInt(Feature.experimental_zbp)] = .{
+    result[@enumToInt(Feature.experimental_zcf)] = .{
-        .llvm_name = "experimental-zbp",
+        .llvm_name = "experimental-zcf",
-        .description = "'Zbp' (Permutation 'Zb' Instructions)",
+        .description = "'Zcf' (Compressed Single-Precision Floating-Point Instructions)",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@enumToInt(Feature.experimental_zbr)] = .{
+    result[@enumToInt(Feature.experimental_zihintntl)] = .{
-        .llvm_name = "experimental-zbr",
+        .llvm_name = "experimental-zihintntl",
-        .description = "'Zbr' (Polynomial Reduction 'Zb' Instructions)",
+        .description = "'zihintntl' (Non-Temporal Locality Hints)",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@enumToInt(Feature.experimental_zbt)] = .{
+    result[@enumToInt(Feature.experimental_ztso)] = .{
-        .llvm_name = "experimental-zbt",
+        .llvm_name = "experimental-ztso",
-        .description = "'Zbt' (Ternary 'Zb' Instructions)",
+        .description = "'Ztso' (Memory Model - Total Store Order)",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@enumToInt(Feature.experimental_zvfh)] = .{
@@ -181,6 +198,16 @@ pub const all_features = blk: {
         .description = "'F' (Single-Precision Floating-Point)",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.forced_atomics)] = .{
+        .llvm_name = "forced-atomics",
+        .description = "Assume that lock-free native-width atomics are available",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.h)] = .{
+        .llvm_name = "h",
+        .description = "'H' (Hypervisor)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.lui_addi_fusion)] = .{
         .llvm_name = "lui-addi-fusion",
         .description = "Enable LUI+ADDI macrofusion",
@@ -196,6 +223,11 @@ pub const all_features = blk: {
         .description = "Disable default unroll preference.",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.no_optimized_zero_stride_load)] = .{
+        .llvm_name = "no-optimized-zero-stride-load",
+        .description = "Hasn't optimized (perform fewer memory operations)zero-stride vector load",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.no_rvc_hints)] = .{
         .llvm_name = "no-rvc-hints",
         .description = "Disable RVC Hint Instructions.",
@@ -366,6 +398,31 @@ pub const all_features = blk: {
         .description = "Enable save/restore.",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.short_forward_branch_opt)] = .{
+        .llvm_name = "short-forward-branch-opt",
+        .description = "Enable short forward branch optimization",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.svinval)] = .{
+        .llvm_name = "svinval",
+        .description = "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.svnapot)] = .{
+        .llvm_name = "svnapot",
+        .description = "'Svnapot' (NAPOT Translation Contiguity)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.svpbmt)] = .{
+        .llvm_name = "svpbmt",
+        .description = "'Svpbmt' (Page-Based Memory Types)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.tagged_globals)] = .{
+        .llvm_name = "tagged-globals",
+        .description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.unaligned_scalar_mem)] = .{
         .llvm_name = "unaligned-scalar-mem",
         .description = "Has reasonably performant unaligned scalar loads and stores",
@@ -380,6 +437,18 @@ pub const all_features = blk: {
             .zvl128b,
         }),
     };
+    result[@enumToInt(Feature.xtheadvdot)] = .{
+        .llvm_name = "xtheadvdot",
+        .description = "'xtheadvdot' (T-Head Vector Extensions for Dot)",
+        .dependencies = featureSet(&[_]Feature{
+            .v,
+        }),
+    };
+    result[@enumToInt(Feature.xventanacondops)] = .{
+        .llvm_name = "xventanacondops",
+        .description = "'XVentanaCondOps' (Ventana Conditional Ops)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.zba)] = .{
         .llvm_name = "zba",
         .description = "'Zba' (Address Generation Instructions)",
@@ -652,6 +721,13 @@ pub const all_features = blk: {
             .zvl32b,
         }),
     };
+    result[@enumToInt(Feature.zvl65536b)] = .{
+        .llvm_name = "zvl65536b",
+        .description = "'Zvl' (Minimum Vector Length) 65536",
+        .dependencies = featureSet(&[_]Feature{
+            .zvl32768b,
+        }),
+    };
     result[@enumToInt(Feature.zvl8192b)] = .{
         .llvm_name = "zvl8192b",
         .description = "'Zvl' (Minimum Vector Length) 8192",
@@ -697,7 +773,9 @@ pub const cpu = struct {
     pub const generic_rv32 = CpuModel{
         .name = "generic_rv32",
         .llvm_name = "generic-rv32",
-        .features = featureSet(&[_]Feature{}),
+        .features = featureSet(&[_]Feature{
+            .@"32bit",
+        }),
     };
     pub const generic_rv64 = CpuModel{
         .name = "generic_rv64",
@@ -706,10 +784,17 @@ pub const cpu = struct {
             .@"64bit",
         }),
     };
+    pub const rocket = CpuModel{
+        .name = "rocket",
+        .llvm_name = "rocket",
+        .features = featureSet(&[_]Feature{}),
+    };
     pub const rocket_rv32 = CpuModel{
         .name = "rocket_rv32",
         .llvm_name = "rocket-rv32",
-        .features = featureSet(&[_]Feature{}),
+        .features = featureSet(&[_]Feature{
+            .@"32bit",
+        }),
     };
     pub const rocket_rv64 = CpuModel{
         .name = "rocket_rv64",
@@ -718,25 +803,19 @@ pub const cpu = struct {
             .@"64bit",
         }),
     };
-    pub const sifive_7_rv32 = CpuModel{
+    pub const sifive_7_series = CpuModel{
-        .name = "sifive_7_rv32",
+        .name = "sifive_7_series",
-        .llvm_name = "sifive-7-rv32",
+        .llvm_name = "sifive-7-series",
         .features = featureSet(&[_]Feature{
             .no_default_unroll,
-        }),
+            .short_forward_branch_opt,
-    };
-    pub const sifive_7_rv64 = CpuModel{
-        .name = "sifive_7_rv64",
-        .llvm_name = "sifive-7-rv64",
-        .features = featureSet(&[_]Feature{
-            .@"64bit",
-            .no_default_unroll,
         }),
     };
     pub const sifive_e20 = CpuModel{
         .name = "sifive_e20",
         .llvm_name = "sifive-e20",
         .features = featureSet(&[_]Feature{
+            .@"32bit",
             .c,
             .m,
         }),
@@ -745,6 +824,7 @@ pub const cpu = struct {
         .name = "sifive_e21",
         .llvm_name = "sifive-e21",
         .features = featureSet(&[_]Feature{
+            .@"32bit",
             .a,
             .c,
             .m,
@@ -754,6 +834,7 @@ pub const cpu = struct {
         .name = "sifive_e24",
         .llvm_name = "sifive-e24",
         .features = featureSet(&[_]Feature{
+            .@"32bit",
             .a,
             .c,
             .f,
@@ -764,6 +845,7 @@ pub const cpu = struct {
         .name = "sifive_e31",
         .llvm_name = "sifive-e31",
         .features = featureSet(&[_]Feature{
+            .@"32bit",
             .a,
             .c,
             .m,
@@ -773,6 +855,7 @@ pub const cpu = struct {
         .name = "sifive_e34",
         .llvm_name = "sifive-e34",
         .features = featureSet(&[_]Feature{
+            .@"32bit",
             .a,
             .c,
             .f,
@@ -783,11 +866,13 @@ pub const cpu = struct {
         .name = "sifive_e76",
         .llvm_name = "sifive-e76",
         .features = featureSet(&[_]Feature{
+            .@"32bit",
             .a,
             .c,
             .f,
             .m,
             .no_default_unroll,
+            .short_forward_branch_opt,
         }),
     };
     pub const sifive_s21 = CpuModel{
@@ -831,6 +916,7 @@ pub const cpu = struct {
             .d,
             .m,
             .no_default_unroll,
+            .short_forward_branch_opt,
         }),
     };
     pub const sifive_u54 = CpuModel{
@@ -854,6 +940,26 @@ pub const cpu = struct {
             .d,
             .m,
             .no_default_unroll,
+            .short_forward_branch_opt,
+        }),
+    };
+    pub const syntacore_scr1_base = CpuModel{
+        .name = "syntacore_scr1_base",
+        .llvm_name = "syntacore-scr1-base",
+        .features = featureSet(&[_]Feature{
+            .@"32bit",
+            .c,
+            .no_default_unroll,
+        }),
+    };
+    pub const syntacore_scr1_max = CpuModel{
+        .name = "syntacore_scr1_max",
+        .llvm_name = "syntacore-scr1-max",
+        .features = featureSet(&[_]Feature{
+            .@"32bit",
+            .c,
+            .m,
+            .no_default_unroll,
         }),
     };
 };

lib/std/target/wasm.zig

@@ -113,7 +113,10 @@ pub const cpu = struct {
     pub const generic = CpuModel{
         .name = "generic",
         .llvm_name = "generic",
-        .features = featureSet(&[_]Feature{}),
+        .features = featureSet(&[_]Feature{
+            .mutable_globals,
+            .sign_ext,
+        }),
     };
     pub const mvp = CpuModel{
         .name = "mvp",

lib/std/target/x86.zig

@@ -12,7 +12,9 @@ pub const Feature = enum {
     @"64bit",
     adx,
     aes,
+    allow_light_256_bit,
     amx_bf16,
+    amx_fp16,
     amx_int8,
     amx_tile,
     avx,
@@ -33,7 +35,10 @@ pub const Feature = enum {
     avx512vnni,
     avx512vp2intersect,
     avx512vpopcntdq,
+    avxifma,
+    avxneconvert,
     avxvnni,
+    avxvnniint8,
     bmi,
     bmi2,
     branchfusion,
@@ -42,6 +47,7 @@ pub const Feature = enum {
     clwb,
     clzero,
     cmov,
+    cmpccxadd,
     crc32,
     cx16,
     cx8,
@@ -104,9 +110,11 @@ pub const Feature = enum {
     prefer_128_bit,
     prefer_256_bit,
     prefer_mask_registers,
+    prefetchi,
     prefetchwt1,
     prfchw,
     ptwrite,
+    raoint,
     rdpid,
     rdpru,
     rdrnd,
@@ -211,6 +219,11 @@ pub const all_features = blk: {
             .sse2,
         }),
     };
+    result[@enumToInt(Feature.allow_light_256_bit)] = .{
+        .llvm_name = "allow-light-256-bit",
+        .description = "Enable generation of 256-bit load/stores even if we prefer 128-bit",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.amx_bf16)] = .{
         .llvm_name = "amx-bf16",
         .description = "Support AMX-BF16 instructions",
@@ -218,6 +231,13 @@ pub const all_features = blk: {
             .amx_tile,
         }),
     };
+    result[@enumToInt(Feature.amx_fp16)] = .{
+        .llvm_name = "amx-fp16",
+        .description = "Support AMX amx-fp16 instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .amx_tile,
+        }),
+    };
     result[@enumToInt(Feature.amx_int8)] = .{
         .llvm_name = "amx-int8",
         .description = "Support AMX-INT8 instructions",
@@ -360,6 +380,20 @@ pub const all_features = blk: {
             .avx512f,
         }),
     };
+    result[@enumToInt(Feature.avxifma)] = .{
+        .llvm_name = "avxifma",
+        .description = "Enable AVX-IFMA",
+        .dependencies = featureSet(&[_]Feature{
+            .avx2,
+        }),
+    };
+    result[@enumToInt(Feature.avxneconvert)] = .{
+        .llvm_name = "avxneconvert",
+        .description = "Support AVX-NE-CONVERT instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .avx2,
+        }),
+    };
     result[@enumToInt(Feature.avxvnni)] = .{
         .llvm_name = "avxvnni",
         .description = "Support AVX_VNNI encoding",
@@ -367,6 +401,13 @@ pub const all_features = blk: {
             .avx2,
         }),
     };
+    result[@enumToInt(Feature.avxvnniint8)] = .{
+        .llvm_name = "avxvnniint8",
+        .description = "Enable AVX-VNNI-INT8",
+        .dependencies = featureSet(&[_]Feature{
+            .avx2,
+        }),
+    };
     result[@enumToInt(Feature.bmi)] = .{
         .llvm_name = "bmi",
         .description = "Support BMI instructions",
@@ -407,6 +448,11 @@ pub const all_features = blk: {
         .description = "Enable conditional move instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.cmpccxadd)] = .{
+        .llvm_name = "cmpccxadd",
+        .description = "Support CMPCCXADD instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.crc32)] = .{
         .llvm_name = "crc32",
         .description = "Enable SSE 4.2 CRC32 instruction (used when SSE4.2 is supported but function is GPR only)",
@@ -732,6 +778,11 @@ pub const all_features = blk: {
         .description = "Prefer AVX512 mask registers over PTEST/MOVMSK",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.prefetchi)] = .{
+        .llvm_name = "prefetchi",
+        .description = "Prefetch instruction with T0 or T1 Hint",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.prefetchwt1)] = .{
         .llvm_name = "prefetchwt1",
         .description = "Prefetch with Intent to Write and T1 Hint",
@@ -747,6 +798,11 @@ pub const all_features = blk: {
         .description = "Support ptwrite instruction",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@enumToInt(Feature.raoint)] = .{
+        .llvm_name = "raoint",
+        .description = "Support RAO-INT instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@enumToInt(Feature.rdpid)] = .{
         .llvm_name = "rdpid",
         .description = "Support RDPID instructions",
@@ -1059,6 +1115,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .@"64bit",
             .adx,
+            .allow_light_256_bit,
             .avxvnni,
             .bmi,
             .bmi2,
@@ -1488,6 +1545,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .@"64bit",
             .adx,
+            .allow_light_256_bit,
             .avx2,
             .bmi,
             .bmi2,
@@ -1615,6 +1673,7 @@ pub const cpu = struct {
             .@"64bit",
             .adx,
             .aes,
+            .allow_light_256_bit,
             .avx512cd,
             .avx512dq,
             .avx512ifma,
@@ -1667,6 +1726,7 @@ pub const cpu = struct {
             .@"64bit",
             .adx,
             .aes,
+            .allow_light_256_bit,
             .avx512bw,
             .avx512cd,
             .avx512dq,
@@ -1720,6 +1780,7 @@ pub const cpu = struct {
             .@"64bit",
             .adx,
             .aes,
+            .allow_light_256_bit,
             .avx512bf16,
             .avx512cd,
             .avx512dq,
@@ -1789,6 +1850,7 @@ pub const cpu = struct {
         .llvm_name = "core-avx2",
         .features = featureSet(&[_]Feature{
             .@"64bit",
+            .allow_light_256_bit,
             .avx2,
             .bmi,
             .bmi2,
@@ -1901,6 +1963,86 @@ pub const cpu = struct {
             .xsaveopt,
         }),
     };
+    pub const emeraldrapids = CpuModel{
+        .name = "emeraldrapids",
+        .llvm_name = "emeraldrapids",
+        .features = featureSet(&[_]Feature{
+            .@"64bit",
+            .adx,
+            .allow_light_256_bit,
+            .amx_bf16,
+            .amx_int8,
+            .avx512bf16,
+            .avx512bitalg,
+            .avx512cd,
+            .avx512fp16,
+            .avx512ifma,
+            .avx512vbmi,
+            .avx512vbmi2,
+            .avx512vnni,
+            .avx512vpopcntdq,
+            .avxvnni,
+            .bmi,
+            .bmi2,
+            .cldemote,
+            .clflushopt,
+            .clwb,
+            .cmov,
+            .crc32,
+            .cx16,
+            .enqcmd,
+            .ermsb,
+            .false_deps_getmant,
+            .false_deps_mulc,
+            .false_deps_mullq,
+            .false_deps_perm,
+            .false_deps_range,
+            .fast_15bytenop,
+            .fast_gather,
+            .fast_scalar_fsqrt,
+            .fast_shld_rotate,
+            .fast_variable_crosslane_shuffle,
+            .fast_variable_perlane_shuffle,
+            .fast_vector_fsqrt,
+            .fsgsbase,
+            .fsrm,
+            .fxsr,
+            .gfni,
+            .idivq_to_divl,
+            .invpcid,
+            .lzcnt,
+            .macrofusion,
+            .mmx,
+            .movbe,
+            .movdir64b,
+            .movdiri,
+            .nopl,
+            .pconfig,
+            .pku,
+            .popcnt,
+            .prefer_256_bit,
+            .prfchw,
+            .ptwrite,
+            .rdpid,
+            .rdrnd,
+            .rdseed,
+            .sahf,
+            .serialize,
+            .sha,
+            .shstk,
+            .tsxldtrk,
+            .uintr,
+            .vaes,
+            .vpclmulqdq,
+            .vzeroupper,
+            .waitpkg,
+            .wbnoinvd,
+            .x87,
+            .xsavec,
+            .xsaveopt,
+            .xsaves,
+        }),
+    };
     pub const generic = CpuModel{
         .name = "generic",
         .llvm_name = "generic",
@@ -2000,11 +2142,155 @@ pub const cpu = struct {
             .xsaves,
         }),
     };
+    pub const grandridge = CpuModel{
+        .name = "grandridge",
+        .llvm_name = "grandridge",
+        .features = featureSet(&[_]Feature{
+            .@"64bit",
+            .adx,
+            .avxifma,
+            .avxneconvert,
+            .avxvnni,
+            .avxvnniint8,
+            .bmi,
+            .bmi2,
+            .cldemote,
+            .clflushopt,
+            .clwb,
+            .cmov,
+            .cmpccxadd,
+            .crc32,
+            .cx16,
+            .f16c,
+            .fast_movbe,
+            .fma,
+            .fsgsbase,
+            .fxsr,
+            .gfni,
+            .hreset,
+            .invpcid,
+            .lzcnt,
+            .mmx,
+            .movbe,
+            .movdir64b,
+            .movdiri,
+            .nopl,
+            .pconfig,
+            .pku,
+            .popcnt,
+            .prfchw,
+            .ptwrite,
+            .raoint,
+            .rdpid,
+            .rdrnd,
+            .rdseed,
+            .sahf,
+            .serialize,
+            .sha,
+            .shstk,
+            .slow_incdec,
+            .slow_lea,
+            .slow_two_mem_ops,
+            .use_glm_div_sqrt_costs,
+            .vaes,
+            .vpclmulqdq,
+            .vzeroupper,
+            .waitpkg,
+            .widekl,
+            .x87,
+            .xsavec,
+            .xsaveopt,
+            .xsaves,
+        }),
+    };
+    pub const graniterapids = CpuModel{
+        .name = "graniterapids",
+        .llvm_name = "graniterapids",
+        .features = featureSet(&[_]Feature{
+            .@"64bit",
+            .adx,
+            .allow_light_256_bit,
+            .amx_bf16,
+            .amx_fp16,
+            .amx_int8,
+            .avx512bf16,
+            .avx512bitalg,
+            .avx512cd,
+            .avx512fp16,
+            .avx512ifma,
+            .avx512vbmi,
+            .avx512vbmi2,
+            .avx512vnni,
+            .avx512vpopcntdq,
+            .avxvnni,
+            .bmi,
+            .bmi2,
+            .cldemote,
+            .clflushopt,
+            .clwb,
+            .cmov,
+            .crc32,
+            .cx16,
+            .enqcmd,
+            .ermsb,
+            .false_deps_getmant,
+            .false_deps_mulc,
+            .false_deps_mullq,
+            .false_deps_perm,
+            .false_deps_range,
+            .fast_15bytenop,
+            .fast_gather,
+            .fast_scalar_fsqrt,
+            .fast_shld_rotate,
+            .fast_variable_crosslane_shuffle,
+            .fast_variable_perlane_shuffle,
+            .fast_vector_fsqrt,
+            .fsgsbase,
+            .fsrm,
+            .fxsr,
+            .gfni,
+            .idivq_to_divl,
+            .invpcid,
+            .lzcnt,
+            .macrofusion,
+            .mmx,
+            .movbe,
+            .movdir64b,
+            .movdiri,
+            .nopl,
+            .pconfig,
+            .pku,
+            .popcnt,
+            .prefer_256_bit,
+            .prefetchi,
+            .prfchw,
+            .ptwrite,
+            .rdpid,
+            .rdrnd,
+            .rdseed,
+            .sahf,
+            .serialize,
+            .sha,
+            .shstk,
+            .tsxldtrk,
+            .uintr,
+            .vaes,
+            .vpclmulqdq,
+            .vzeroupper,
+            .waitpkg,
+            .wbnoinvd,
+            .x87,
+            .xsavec,
+            .xsaveopt,
+            .xsaves,
+        }),
+    };
     pub const haswell = CpuModel{
         .name = "haswell",
         .llvm_name = "haswell",
         .features = featureSet(&[_]Feature{
             .@"64bit",
+            .allow_light_256_bit,
             .avx2,
             .bmi,
             .bmi2,
@@ -2085,6 +2371,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .@"64bit",
             .adx,
+            .allow_light_256_bit,
             .avx512bitalg,
             .avx512cd,
             .avx512dq,
@@ -2128,7 +2415,6 @@ pub const cpu = struct {
             .rdseed,
             .sahf,
             .sha,
-            .slow_3ops_lea,
             .vaes,
             .vpclmulqdq,
             .vzeroupper,
@@ -2144,6 +2430,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .@"64bit",
             .adx,
+            .allow_light_256_bit,
             .avx512bitalg,
             .avx512cd,
             .avx512dq,
@@ -2189,7 +2476,6 @@ pub const cpu = struct {
             .rdseed,
             .sahf,
             .sha,
-            .slow_3ops_lea,
             .vaes,
             .vpclmulqdq,
             .vzeroupper,
@@ -2392,6 +2678,70 @@ pub const cpu = struct {
             .vzeroupper,
         }),
     };
+    pub const meteorlake = CpuModel{
+        .name = "meteorlake",
+        .llvm_name = "meteorlake",
+        .features = featureSet(&[_]Feature{
+            .@"64bit",
+            .adx,
+            .allow_light_256_bit,
+            .avxvnni,
+            .bmi,
+            .bmi2,
+            .cldemote,
+            .clflushopt,
+            .clwb,
+            .cmov,
+            .crc32,
+            .cx16,
+            .f16c,
+            .false_deps_perm,
+            .false_deps_popcnt,
+            .fast_15bytenop,
+            .fast_gather,
+            .fast_scalar_fsqrt,
+            .fast_shld_rotate,
+            .fast_variable_crosslane_shuffle,
+            .fast_variable_perlane_shuffle,
+            .fast_vector_fsqrt,
+            .fma,
+            .fsgsbase,
+            .fxsr,
+            .gfni,
+            .hreset,
+            .idivq_to_divl,
+            .invpcid,
+            .lzcnt,
+            .macrofusion,
+            .mmx,
+            .movbe,
+            .movdir64b,
+            .movdiri,
+            .nopl,
+            .pconfig,
+            .pku,
+            .popcnt,
+            .prfchw,
+            .ptwrite,
+            .rdpid,
+            .rdrnd,
+            .rdseed,
+            .sahf,
+            .serialize,
+            .sha,
+            .shstk,
+            .slow_3ops_lea,
+            .vaes,
+            .vpclmulqdq,
+            .vzeroupper,
+            .waitpkg,
+            .widekl,
+            .x87,
+            .xsavec,
+            .xsaveopt,
+            .xsaves,
+        }),
+    };
     pub const nehalem = CpuModel{
         .name = "nehalem",
         .llvm_name = "nehalem",
@@ -2620,12 +2970,77 @@ pub const cpu = struct {
             .x87,
         }),
     };
+    pub const raptorlake = CpuModel{
+        .name = "raptorlake",
+        .llvm_name = "raptorlake",
+        .features = featureSet(&[_]Feature{
+            .@"64bit",
+            .adx,
+            .allow_light_256_bit,
+            .avxvnni,
+            .bmi,
+            .bmi2,
+            .cldemote,
+            .clflushopt,
+            .clwb,
+            .cmov,
+            .crc32,
+            .cx16,
+            .f16c,
+            .false_deps_perm,
+            .false_deps_popcnt,
+            .fast_15bytenop,
+            .fast_gather,
+            .fast_scalar_fsqrt,
+            .fast_shld_rotate,
+            .fast_variable_crosslane_shuffle,
+            .fast_variable_perlane_shuffle,
+            .fast_vector_fsqrt,
+            .fma,
+            .fsgsbase,
+            .fxsr,
+            .gfni,
+            .hreset,
+            .idivq_to_divl,
+            .invpcid,
+            .lzcnt,
+            .macrofusion,
+            .mmx,
+            .movbe,
+            .movdir64b,
+            .movdiri,
+            .nopl,
+            .pconfig,
+            .pku,
+            .popcnt,
+            .prfchw,
+            .ptwrite,
+            .rdpid,
+            .rdrnd,
+            .rdseed,
+            .sahf,
+            .serialize,
+            .sha,
+            .shstk,
+            .slow_3ops_lea,
+            .vaes,
+            .vpclmulqdq,
+            .vzeroupper,
+            .waitpkg,
+            .widekl,
+            .x87,
+            .xsavec,
+            .xsaveopt,
+            .xsaves,
+        }),
+    };
     pub const rocketlake = CpuModel{
         .name = "rocketlake",
         .llvm_name = "rocketlake",
         .features = featureSet(&[_]Feature{
             .@"64bit",
             .adx,
+            .allow_light_256_bit,
             .avx512bitalg,
             .avx512cd,
             .avx512dq,
@@ -2669,7 +3084,6 @@ pub const cpu = struct {
             .rdseed,
             .sahf,
             .sha,
-            .slow_3ops_lea,
             .vaes,
             .vpclmulqdq,
             .vzeroupper,
@@ -2713,6 +3127,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .@"64bit",
             .adx,
+            .allow_light_256_bit,
             .amx_bf16,
             .amx_int8,
             .avx512bf16,
@@ -2773,7 +3188,6 @@ pub const cpu = struct {
             .serialize,
             .sha,
             .shstk,
-            .slow_3ops_lea,
             .tsxldtrk,
             .uintr,
             .vaes,
@@ -2787,6 +3201,66 @@ pub const cpu = struct {
             .xsaves,
         }),
     };
+    pub const sierraforest = CpuModel{
+        .name = "sierraforest",
+        .llvm_name = "sierraforest",
+        .features = featureSet(&[_]Feature{
+            .@"64bit",
+            .adx,
+            .avxifma,
+            .avxneconvert,
+            .avxvnni,
+            .avxvnniint8,
+            .bmi,
+            .bmi2,
+            .cldemote,
+            .clflushopt,
+            .clwb,
+            .cmov,
+            .cmpccxadd,
+            .crc32,
+            .cx16,
+            .f16c,
+            .fast_movbe,
+            .fma,
+            .fsgsbase,
+            .fxsr,
+            .gfni,
+            .hreset,
+            .invpcid,
+            .lzcnt,
+            .mmx,
+            .movbe,
+            .movdir64b,
+            .movdiri,
+            .nopl,
+            .pconfig,
+            .pku,
+            .popcnt,
+            .prfchw,
+            .ptwrite,
+            .rdpid,
+            .rdrnd,
+            .rdseed,
+            .sahf,
+            .serialize,
+            .sha,
+            .shstk,
+            .slow_incdec,
+            .slow_lea,
+            .slow_two_mem_ops,
+            .use_glm_div_sqrt_costs,
+            .vaes,
+            .vpclmulqdq,
+            .vzeroupper,
+            .waitpkg,
+            .widekl,
+            .x87,
+            .xsavec,
+            .xsaveopt,
+            .xsaves,
+        }),
+    };
     pub const silvermont = CpuModel{
         .name = "silvermont",
         .llvm_name = "silvermont",
@@ -2825,6 +3299,7 @@ pub const cpu = struct {
             .@"64bit",
             .adx,
             .aes,
+            .allow_light_256_bit,
             .avx512bw,
             .avx512cd,
             .avx512dq,
@@ -2877,6 +3352,7 @@ pub const cpu = struct {
             .@"64bit",
             .adx,
             .aes,
+            .allow_light_256_bit,
             .avx2,
             .bmi,
             .bmi2,
@@ -2925,6 +3401,7 @@ pub const cpu = struct {
             .@"64bit",
             .adx,
             .aes,
+            .allow_light_256_bit,
             .avx512bw,
             .avx512cd,
             .avx512dq,
@@ -3007,6 +3484,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .@"64bit",
             .adx,
+            .allow_light_256_bit,
             .avx512bitalg,
             .avx512cd,
             .avx512dq,
@@ -3055,7 +3533,6 @@ pub const cpu = struct {
             .sahf,
             .sha,
             .shstk,
-            .slow_3ops_lea,
             .vaes,
             .vpclmulqdq,
             .vzeroupper,
@@ -3194,6 +3671,7 @@ pub const cpu = struct {
         .llvm_name = "x86-64-v3",
         .features = featureSet(&[_]Feature{
             .@"64bit",
+            .allow_light_256_bit,
             .avx2,
             .bmi,
             .bmi2,
@@ -3229,6 +3707,7 @@ pub const cpu = struct {
         .llvm_name = "x86-64-v4",
         .features = featureSet(&[_]Feature{
             .@"64bit",
+            .allow_light_256_bit,
             .avx512bw,
             .avx512cd,
             .avx512dq,
@@ -3284,6 +3763,7 @@ pub const cpu = struct {
             .@"64bit",
             .adx,
             .aes,
+            .allow_light_256_bit,
             .avx2,
             .bmi,
             .bmi2,
@@ -3334,6 +3814,7 @@ pub const cpu = struct {
             .@"64bit",
             .adx,
             .aes,
+            .allow_light_256_bit,
             .avx2,
             .bmi,
             .bmi2,
@@ -3387,6 +3868,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .@"64bit",
             .adx,
+            .allow_light_256_bit,
             .avx2,
             .bmi,
             .bmi2,
@@ -3439,4 +3921,72 @@ pub const cpu = struct {
             .xsaves,
         }),
     };
+    pub const znver4 = CpuModel{
+        .name = "znver4",
+        .llvm_name = "znver4",
+        .features = featureSet(&[_]Feature{
+            .@"64bit",
+            .adx,
+            .allow_light_256_bit,
+            .avx512bf16,
+            .avx512bitalg,
+            .avx512cd,
+            .avx512dq,
+            .avx512ifma,
+            .avx512vbmi,
+            .avx512vbmi2,
+            .avx512vl,
+            .avx512vnni,
+            .avx512vpopcntdq,
+            .bmi,
+            .bmi2,
+            .branchfusion,
+            .clflushopt,
+            .clwb,
+            .clzero,
+            .cmov,
+            .crc32,
+            .cx16,
+            .fast_15bytenop,
+            .fast_bextr,
+            .fast_lzcnt,
+            .fast_movbe,
+            .fast_scalar_fsqrt,
+            .fast_scalar_shift_masks,
+            .fast_variable_perlane_shuffle,
+            .fast_vector_fsqrt,
+            .fsgsbase,
+            .fsrm,
+            .fxsr,
+            .gfni,
+            .invpcid,
+            .lzcnt,
+            .macrofusion,
+            .mmx,
+            .movbe,
+            .mwaitx,
+            .nopl,
+            .pku,
+            .popcnt,
+            .prfchw,
+            .rdpid,
+            .rdpru,
+            .rdrnd,
+            .rdseed,
+            .sahf,
+            .sbb_dep_breaking,
+            .sha,
+            .shstk,
+            .slow_shld,
+            .sse4a,
+            .vaes,
+            .vpclmulqdq,
+            .vzeroupper,
+            .wbnoinvd,
+            .x87,
+            .xsavec,
+            .xsaveopt,
+            .xsaves,
+        }),
+    };
 };

lib/std/target/xtensa.zig

@@ -0,0 +1,39 @@
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
+const std = @import("../std.zig");
+const CpuFeature = std.Target.Cpu.Feature;
+const CpuModel = std.Target.Cpu.Model;
+
+pub const Feature = enum {
+    density,
+};
+
+pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;
+pub const featureSetHas = CpuFeature.feature_set_fns(Feature).featureSetHas;
+pub const featureSetHasAny = CpuFeature.feature_set_fns(Feature).featureSetHasAny;
+pub const featureSetHasAll = CpuFeature.feature_set_fns(Feature).featureSetHasAll;
+
+pub const all_features = blk: {
+    const len = @typeInfo(Feature).Enum.fields.len;
+    std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
+    var result: [len]CpuFeature = undefined;
+    result[@enumToInt(Feature.density)] = .{
+        .llvm_name = "density",
+        .description = "Enable Density instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    const ti = @typeInfo(Feature);
+    for (result) |*elem, i| {
+        elem.index = i;
+        elem.name = ti.Enum.fields[i].name;
+    }
+    break :blk result;
+};
+
+pub const cpu = struct {
+    pub const generic = CpuModel{
+        .name = "generic",
+        .llvm_name = "generic",
+        .features = featureSet(&[_]Feature{}),
+    };
+};

src/codegen/llvm.zig

@@ -78,6 +78,7 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![:0]u8 {
         .x86 => "i386",
         .x86_64 => "x86_64",
         .xcore => "xcore",
+        .xtensa => "xtensa",
         .nvptx => "nvptx",
         .nvptx64 => "nvptx64",
         .le32 => "le32",
@@ -88,6 +89,8 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![:0]u8 {
         .hsail64 => "hsail64",
         .spir => "spir",
         .spir64 => "spir64",
+        .spirv32 => "spirv32",
+        .spirv64 => "spirv64",
         .kalimba => "kalimba",
         .shave => "shave",
         .lanai => "lanai",
@@ -97,8 +100,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![:0]u8 {
         .renderscript64 => "renderscript64",
         .ve => "ve",
         .spu_2 => return error.@"LLVM backend does not support SPU Mark II",
-        .spirv32 => return error.@"LLVM backend does not support SPIR-V",
-        .spirv64 => return error.@"LLVM backend does not support SPIR-V",
     };
     try llvm_triple.appendSlice(llvm_arch);
     try llvm_triple.appendSlice("-unknown-");
@@ -169,6 +170,9 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![:0]u8 {
         .gnuabi64 => "gnuabi64",
         .gnueabi => "gnueabi",
         .gnueabihf => "gnueabihf",
+        .gnuf32 => "gnuf32",
+        .gnuf64 => "gnuf64",
+        .gnusf => "gnusf",
         .gnux32 => "gnux32",
         .gnuilp32 => "gnuilp32",
         .code16 => "code16",
@@ -290,6 +294,7 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
         .x86 => .x86,
         .x86_64 => .x86_64,
         .xcore => .xcore,
+        .xtensa => .xtensa,
         .nvptx => .nvptx,
         .nvptx64 => .nvptx64,
         .le32 => .le32,
@@ -10092,6 +10097,15 @@ fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
             llvm.LLVMInitializeX86AsmPrinter();
             llvm.LLVMInitializeX86AsmParser();
         },
+        .xtensa => {
+            if (build_options.llvm_has_xtensa) {
+                llvm.LLVMInitializeXtensaTarget();
+                llvm.LLVMInitializeXtensaTargetInfo();
+                llvm.LLVMInitializeXtensaTargetMC();
+                llvm.LLVMInitializeXtensaAsmPrinter();
+                llvm.LLVMInitializeXtensaAsmParser();
+            }
+        },
         .xcore => {
             llvm.LLVMInitializeXCoreTarget();
             llvm.LLVMInitializeXCoreTargetInfo();

src/codegen/llvm/bindings.zig

@@ -1133,6 +1133,7 @@ pub extern fn LLVMInitializeSystemZTargetInfo() void;
 pub extern fn LLVMInitializeWebAssemblyTargetInfo() void;
 pub extern fn LLVMInitializeX86TargetInfo() void;
 pub extern fn LLVMInitializeXCoreTargetInfo() void;
+pub extern fn LLVMInitializeXtensaTargetInfo() void;
 pub extern fn LLVMInitializeM68kTargetInfo() void;
 pub extern fn LLVMInitializeCSKYTargetInfo() void;
 pub extern fn LLVMInitializeVETargetInfo() void;
@@ -1155,6 +1156,7 @@ pub extern fn LLVMInitializeSystemZTarget() void;
 pub extern fn LLVMInitializeWebAssemblyTarget() void;
 pub extern fn LLVMInitializeX86Target() void;
 pub extern fn LLVMInitializeXCoreTarget() void;
+pub extern fn LLVMInitializeXtensaTarget() void;
 pub extern fn LLVMInitializeM68kTarget() void;
 pub extern fn LLVMInitializeVETarget() void;
 pub extern fn LLVMInitializeCSKYTarget() void;
@@ -1177,6 +1179,7 @@ pub extern fn LLVMInitializeSystemZTargetMC() void;
 pub extern fn LLVMInitializeWebAssemblyTargetMC() void;
 pub extern fn LLVMInitializeX86TargetMC() void;
 pub extern fn LLVMInitializeXCoreTargetMC() void;
+pub extern fn LLVMInitializeXtensaTargetMC() void;
 pub extern fn LLVMInitializeM68kTargetMC() void;
 pub extern fn LLVMInitializeCSKYTargetMC() void;
 pub extern fn LLVMInitializeVETargetMC() void;
@@ -1199,6 +1202,7 @@ pub extern fn LLVMInitializeSystemZAsmPrinter() void;
 pub extern fn LLVMInitializeWebAssemblyAsmPrinter() void;
 pub extern fn LLVMInitializeX86AsmPrinter() void;
 pub extern fn LLVMInitializeXCoreAsmPrinter() void;
+pub extern fn LLVMInitializeXtensaAsmPrinter() void;
 pub extern fn LLVMInitializeM68kAsmPrinter() void;
 pub extern fn LLVMInitializeVEAsmPrinter() void;
 pub extern fn LLVMInitializeARCAsmPrinter() void;
@@ -1218,6 +1222,7 @@ pub extern fn LLVMInitializeSparcAsmParser() void;
 pub extern fn LLVMInitializeSystemZAsmParser() void;
 pub extern fn LLVMInitializeWebAssemblyAsmParser() void;
 pub extern fn LLVMInitializeX86AsmParser() void;
+pub extern fn LLVMInitializeXtensaAsmParser() void;
 pub extern fn LLVMInitializeM68kAsmParser() void;
 pub extern fn LLVMInitializeCSKYAsmParser() void;
 pub extern fn LLVMInitializeVEAsmParser() void;

src/target.zig

@@ -88,6 +88,9 @@ pub fn libCGenericName(target: std.Target) [:0]const u8 {
         .gnuabi64,
         .gnueabi,
         .gnueabihf,
+        .gnuf32,
+        .gnuf64,
+        .gnusf,
         .gnux32,
         .gnuilp32,
         => return "glibc",
@@ -286,6 +289,7 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
         .x86,
         .x86_64,
         .xcore,
+        .xtensa,
         .nvptx,
         .nvptx64,
         .le32,
@@ -296,6 +300,8 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
         .hsail64,
         .spir,
         .spir64,
+        .spirv32,
+        .spirv64,
         .kalimba,
         .shave,
         .lanai,
@@ -306,10 +312,7 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
         .ve,
         => true,
 
-        .spu_2,
+        .spu_2 => false,
-        .spirv32,
-        .spirv64,
-        => false,
     };
 }
 
@@ -566,6 +569,7 @@ pub fn atomicPtrAlignment(
         .spirv32,
         .dxil,
         .loongarch32,
+        .xtensa,
         => 32,
 
         .aarch64,

src/type.zig

@@ -7051,6 +7051,7 @@ pub const CType = enum {
                 .renderscript32,
                 .ve,
                 .spu_2,
+                .xtensa,
                 => 4,
 
                 .aarch64_32,

stage1/config.zig.in

@@ -2,6 +2,7 @@ pub const have_llvm = true;
 pub const llvm_has_m68k = false;
 pub const llvm_has_csky = false;
 pub const llvm_has_arc = false;
+pub const llvm_has_xtensa = false;
 pub const version: [:0]const u8 = "@RESOLVED_ZIG_VERSION@";
 pub const semver = @import("std").SemanticVersion.parse(version) catch unreachable;
 pub const enable_logging: bool = false;

tools/update_cpu_features.zig

@@ -79,6 +79,10 @@ const llvm_targets = [_]LlvmTarget{
                 .llvm_name = "neoversev1",
                 .flatten = true,
             },
+            .{
+                .llvm_name = "neoversev2",
+                .flatten = true,
+            },
             .{
                 .llvm_name = "neoverse512tvb",
                 .flatten = true,
@@ -137,6 +141,14 @@ const llvm_targets = [_]LlvmTarget{
                 .llvm_name = "a77",
                 .flatten = true,
             },
+            .{
+                .llvm_name = "a715",
+                .flatten = true,
+            },
+            .{
+                .llvm_name = "ampere1a",
+                .flatten = true,
+            },
             .{
                 .llvm_name = "apple-a7",
                 .flatten = true,
@@ -161,6 +173,14 @@ const llvm_targets = [_]LlvmTarget{
                 .llvm_name = "apple-a14",
                 .flatten = true,
             },
+            .{
+                .llvm_name = "apple-a15",
+                .flatten = true,
+            },
+            .{
+                .llvm_name = "apple-a16",
+                .flatten = true,
+            },
             .{
                 .llvm_name = "apple-a7-sysreg",
                 .flatten = true,
@@ -181,6 +201,10 @@ const llvm_targets = [_]LlvmTarget{
                 .llvm_name = "cortex-x2",
                 .flatten = true,
             },
+            .{
+                .llvm_name = "cortex-x3",
+                .flatten = true,
+            },
             .{
                 .llvm_name = "falkor",
                 .flatten = true,
@@ -594,6 +618,10 @@ const llvm_targets = [_]LlvmTarget{
                 .llvm_name = "armv8.8-a",
                 .zig_name = "v8_8a",
             },
+            .{
+                .llvm_name = "armv8.9-a",
+                .zig_name = "v8_9a",
+            },
             .{
                 .llvm_name = "armv8-a",
                 .zig_name = "v8a",
@@ -622,6 +650,10 @@ const llvm_targets = [_]LlvmTarget{
                 .llvm_name = "armv9.3-a",
                 .zig_name = "v9_3a",
             },
+            .{
+                .llvm_name = "armv9.4-a",
+                .zig_name = "v9_4a",
+            },
             .{
                 .llvm_name = "armv9-a",
                 .zig_name = "v9a",
@@ -710,6 +742,10 @@ const llvm_targets = [_]LlvmTarget{
                 .llvm_name = "v8.8a",
                 .zig_name = "has_v8_8a",
             },
+            .{
+                .llvm_name = "v8.9a",
+                .zig_name = "has_v8_9a",
+            },
             .{
                 .llvm_name = "v9a",
                 .zig_name = "has_v9a",
@@ -726,6 +762,33 @@ const llvm_targets = [_]LlvmTarget{
                 .llvm_name = "v9.3a",
                 .zig_name = "has_v9_3a",
             },
+            .{
+                .llvm_name = "v9.4a",
+                .zig_name = "has_v9_4a",
+            },
+        },
+        // LLVM removed support for v2 and v3 but zig wants to support targeting old hardware
+        .extra_features = &.{
+            .{
+                .zig_name = "v2",
+                .desc = "ARMv2 architecture",
+                .deps = &.{"strict_align"},
+            },
+            .{
+                .zig_name = "v2a",
+                .desc = "ARMv2a architecture",
+                .deps = &.{"strict_align"},
+            },
+            .{
+                .zig_name = "v3",
+                .desc = "ARMv3 architecture",
+                .deps = &.{"strict_align"},
+            },
+            .{
+                .zig_name = "v3m",
+                .desc = "ARMv3m architecture",
+                .deps = &.{"strict_align"},
+            },
         },
     },
     .{
@@ -753,6 +816,11 @@ const llvm_targets = [_]LlvmTarget{
         .llvm_name = "Lanai",
         .td_name = "Lanai.td",
     },
+    .{
+        .zig_name = "loongarch",
+        .llvm_name = "LoongArch",
+        .td_name = "LoongArch.td",
+    },
     .{
         .zig_name = "m68k",
         .llvm_name = "M68k",
@@ -812,6 +880,12 @@ const llvm_targets = [_]LlvmTarget{
         .llvm_name = "Sparc",
         .td_name = "Sparc.td",
     },
+    // TODO: merge tools/update_spirv_features.zig into this script
+    //.{
+    //    .zig_name = "spirv",
+    //    .llvm_name = "SPIRV",
+    //    .td_name = "SPIRV.td",
+    //},
     .{
         .zig_name = "s390x",
         .llvm_name = "SystemZ",
@@ -847,6 +921,11 @@ const llvm_targets = [_]LlvmTarget{
         .llvm_name = "XCore",
         .td_name = "XCore.td",
     },
+    .{
+        .zig_name = "xtensa",
+        .llvm_name = "Xtensa",
+        .td_name = "Xtensa.td",
+    },
 };
 
 pub fn main() anyerror!void {