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feat: init x86_16 arch via CBE
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GasInfinity
parent
9d3bd3c502
commit
104c272ae5
11 changed files with 63 additions and 9 deletions
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@ -1101,7 +1101,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
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.sparc => if (target.cpu.has(.sparc, .v9)) .SPARC32PLUS else .SPARC,
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.sparc64 => .SPARCV9,
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.ve => .VE,
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.x86 => .@"386",
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.x86_16, .x86 => .@"386",
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.x86_64 => .X86_64,
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.xcore => .XCORE,
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.xtensa, .xtensaeb => .XTENSA,
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@ -1172,6 +1172,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
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.ve,
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.wasm32,
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.wasm64,
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.x86_16,
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.xcore,
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.xtensa,
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.xtensaeb,
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@ -1394,6 +1395,7 @@ pub const Cpu = struct {
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ve,
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wasm32,
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wasm64,
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x86_16,
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x86,
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x86_64,
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xcore,
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@ -1485,7 +1487,7 @@ pub const Cpu = struct {
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.spirv32, .spirv64 => .spirv,
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.ve => .ve,
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.wasm32, .wasm64 => .wasm,
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.x86, .x86_64 => .x86,
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.x86_16, .x86, .x86_64 => .x86,
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.xcore => .xcore,
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.xtensa, .xtensaeb => .xtensa,
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};
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@ -1493,7 +1495,7 @@ pub const Cpu = struct {
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pub inline fn isX86(arch: Arch) bool {
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return switch (arch) {
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.x86, .x86_64 => true,
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.x86_16, .x86, .x86_64 => true,
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else => false,
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};
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}
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@ -1687,6 +1689,7 @@ pub const Cpu = struct {
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.ve,
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.wasm32,
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.wasm64,
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.x86_16,
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.x86,
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.x86_64,
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.xcore,
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@ -1807,6 +1810,12 @@ pub const Cpu = struct {
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.x86_interrupt,
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=> &.{.x86},
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.x86_16_cdecl,
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.x86_16_stdcall,
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.x86_16_regparmcall,
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.x86_16_interrupt,
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=> &.{.x86_16},
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.aarch64_aapcs,
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.aarch64_aapcs_darwin,
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.aarch64_aapcs_win,
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@ -1989,6 +1998,7 @@ pub const Cpu = struct {
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.riscv64, .riscv64be => &riscv.cpu.generic_rv64,
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.sparc64 => &sparc.cpu.v9, // SPARC can only be 64-bit from v9 and up.
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.wasm32, .wasm64 => &wasm.cpu.mvp,
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.x86_16 => &x86.cpu.i86,
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.x86 => &x86.cpu.i386,
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.x86_64 => &x86.cpu.x86_64,
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inline else => |a| &@field(Target, @tagName(a.family())).cpu.generic,
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@ -2260,7 +2270,10 @@ pub fn supportsAddressSpace(
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return switch (address_space) {
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.generic => true,
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.fs, .gs, .ss => (arch == .x86_64 or arch == .x86) and (context == null or context == .pointer),
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.fs, .gs, .ss => (arch == .x86_64 or arch == .x86 or arch == .x86_16) and (context == null or context == .pointer),
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// Technically x86 can use segmentation...
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.far => (arch == .x86_16),
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.flash, .flash1, .flash2, .flash3, .flash4, .flash5 => arch == .avr, // TODO this should also check how many flash banks the cpu has
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.cog, .hub => arch == .propeller,
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.lut => arch == .propeller and std.Target.propeller.featureSetHas(target.cpu.features, .p2),
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@ -2833,6 +2846,7 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
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return switch (cpu_arch) {
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.avr,
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.msp430,
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.x86_16,
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=> 16,
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.arc,
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@ -3046,7 +3060,7 @@ pub fn cTypeByteSize(t: *const Target, c_type: CType) u16 {
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pub fn cTypeBitSize(target: *const Target, c_type: CType) u16 {
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switch (target.os.tag) {
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.freestanding, .other => switch (target.cpu.arch) {
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.msp430 => switch (c_type) {
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.msp430, .x86_16 => switch (c_type) {
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.char => return 8,
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.short, .ushort, .int, .uint => return 16,
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.float, .long, .ulong => return 32,
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@ -3404,6 +3418,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
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std.math.ceilPowerOfTwoAssert(u16, (cTypeBitSize(target, c_type) + 7) / 8),
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@as(u16, switch (target.cpu.arch) {
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.msp430,
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.x86_16,
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=> 2,
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.arc,
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@ -3511,7 +3526,7 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
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return @min(
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std.math.ceilPowerOfTwoAssert(u16, (cTypeBitSize(target, c_type) + 7) / 8),
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@as(u16, switch (target.cpu.arch) {
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.msp430 => 2,
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.x86_16, .msp430 => 2,
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.arc,
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.arceb,
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@ -3583,7 +3598,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
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return switch (target.cpu.arch) {
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.avr => 1,
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.msp430 => 2,
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.msp430, .x86_16 => 2,
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.arc,
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.arceb,
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@ -3660,6 +3675,7 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
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.windows, .uefi => .{ .x86_win = .{} },
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else => .{ .x86_sysv = .{} },
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},
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.x86_16 => .{ .x86_16_cdecl = .{} },
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.aarch64, .aarch64_be => if (target.os.tag.isDarwin())
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.{ .aarch64_aapcs_darwin = .{} }
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else switch (target.os.tag) {
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@ -3081,6 +3081,11 @@ pub const cpu = struct {
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.xsaveopt,
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}),
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};
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pub const @"i86": CpuModel = .{
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.name = "i86",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{}),
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};
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pub const @"i386": CpuModel = .{
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.name = "i386",
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.llvm_name = "i386",
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@ -223,6 +223,13 @@ pub const CallingConvention = union(enum(u8)) {
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x86_vectorcall: CommonOptions,
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x86_interrupt: CommonOptions,
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// Calling conventions for the `x86_16` architecture.
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x86_16_cdecl: CommonOptions,
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x86_16_stdcall: CommonOptions,
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x86_16_regparmcall: CommonOptions,
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x86_16_interrupt: CommonOptions,
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// Calling conventions for the `aarch64` and `aarch64_be` architectures.
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aarch64_aapcs: CommonOptions,
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aarch64_aapcs_darwin: CommonOptions,
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@ -523,6 +530,10 @@ pub const AddressSpace = enum(u5) {
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fs,
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ss,
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// x86_16 extra address spaces.
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/// Allows addressing the entire address space by storing both segment and offset.
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far,
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// GPU address spaces.
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global,
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constant,
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@ -1,5 +1,5 @@
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pub const Clobbers = switch (@import("builtin").cpu.arch) {
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.x86, .x86_64 => packed struct {
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.x86_16, .x86, .x86_64 => packed struct {
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/// Whether the inline assembly code may perform stores to memory
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/// addresses other than those derived from input pointer provenance.
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memory: bool = false,
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@ -386,6 +386,11 @@ pub fn resolveTargetQuery(query: Target.Query) DetectError!Target {
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// However, the "mode" flags can be used as overrides, so if the user explicitly
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// sets one of them, that takes precedence.
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switch (query_cpu_arch) {
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.x86_16 => {
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cpu.features.addFeature(
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@intFromEnum(Target.x86.Feature.@"16bit_mode"),
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);
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},
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.x86 => {
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if (!Target.x86.featureSetHasAny(query.cpu_features_add, .{
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.@"16bit_mode", .@"32bit_mode",
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@ -9034,6 +9034,7 @@ pub fn handleExternLibName(
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/// Any calling conventions not included here are either not yet verified to work with variadic
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/// functions or there are no more other calling conventions that support variadic functions.
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const calling_conventions_supporting_var_args = [_]std.builtin.CallingConvention.Tag{
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.x86_16_cdecl,
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.x86_64_sysv,
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.x86_64_x32,
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.x86_64_win,
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@ -4406,6 +4406,10 @@ pub fn callconvSupported(zcu: *Zcu, cc: std.builtin.CallingConvention) union(enu
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}
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}
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break :ok switch (cc) {
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.x86_16_cdecl,
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.x86_16_stdcall,
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.x86_16_regparmcall,
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.x86_16_interrupt,
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.x86_64_sysv,
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.x86_64_win,
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.x86_64_vectorcall,
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@ -8055,9 +8055,11 @@ fn toCallingConvention(cc: std.builtin.CallingConvention, zcu: *Zcu) ?[]const u8
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return switch (cc) {
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.auto, .naked => null,
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.x86_16_cdecl => "cdecl",
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.x86_16_regparmcall => "regparmcall",
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.x86_64_sysv, .x86_sysv => "sysv_abi",
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.x86_64_win, .x86_win => "ms_abi",
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.x86_stdcall => "stdcall",
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.x86_16_stdcall, .x86_stdcall => "stdcall",
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.x86_fastcall => "fastcall",
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.x86_thiscall => "thiscall",
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@ -8127,6 +8129,7 @@ fn toCallingConvention(cc: std.builtin.CallingConvention, zcu: *Zcu) ?[]const u8
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.csky_interrupt,
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.m68k_interrupt,
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.msp430_interrupt,
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.x86_16_interrupt,
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.x86_interrupt,
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.x86_64_interrupt,
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=> "interrupt",
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@ -117,6 +117,7 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8
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.propeller,
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.sh,
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.sheb,
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.x86_16,
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.xtensaeb,
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=> unreachable, // Gated by hasLlvmSupport().
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};
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@ -493,6 +494,7 @@ pub fn dataLayout(target: *const std.Target) []const u8 {
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.propeller,
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.sh,
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.sheb,
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.x86_16,
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.xtensaeb,
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=> unreachable, // Gated by hasLlvmSupport().
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};
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@ -11919,6 +11921,10 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: *const s
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// All the calling conventions which LLVM does not have a general representation for.
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// Note that these are often still supported through the `cCallingConvention` path above via `ccc`.
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.x86_16_cdecl,
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.x86_16_stdcall,
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.x86_16_regparmcall,
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.x86_16_interrupt,
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.x86_sysv,
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.x86_win,
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.x86_thiscall_mingw,
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@ -13148,6 +13154,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
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.propeller,
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.sh,
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.sheb,
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.x86_16,
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.xtensaeb,
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=> unreachable,
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}
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@ -927,6 +927,7 @@ pub fn storageClass(module: *Module, as: std.builtin.AddressSpace) spec.StorageC
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.gs,
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.fs,
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.ss,
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.far,
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.param,
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.flash,
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.flash1,
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@ -227,6 +227,7 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat)
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.propeller,
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.sh,
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.sheb,
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.x86_16,
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.xtensaeb,
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=> false,
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};
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