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codegen: fix x86-64 backend crc32 inline asm

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David Rubin 2025-11-27 17:43:15 -08:00
parent 7e0d86638f
commit 2e341a7173
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GPG key ID: 5CF5B5A4747520AA
2 changed files with 5 additions and 1 deletions
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2
lib/std/hash/crc.zig
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@ -14,7 +14,7 @@ test {
_ = @import("crc/test.zig");
}
pub const Crc32Iscsi = switch (builtin.cpu.hasAll(.x86, &.{ .@"64bit", .crc32 }) and builtin.zig_backend == .stage2_llvm) {
pub const Crc32Iscsi = switch (builtin.cpu.hasAll(.x86, &.{ .@"64bit", .crc32 })) {
true => @import("crc/crc32c.zig").Wrapper,
else => Crc(u32, .{
.polynomial = 0x1edc6f41,

4
src/codegen/x86_64/CodeGen.zig
View file

@ -177437,6 +177437,10 @@ fn airAsm(self: *CodeGen, inst: Air.Inst.Index) !void {
fixed_mnem_size: {
const fixed_mnem_size: Memory.Size = switch (mnem_tag) {
.clflush => .byte,
.crc32 => {
mnem_size.op_has_size.unset(1);
break :fixed_mnem_size;
},
.fldcw, .fnstcw, .fstcw, .fnstsw, .fstsw => .word,
.fldenv, .fnstenv, .fstenv => .none,
.frstor, .fsave, .fnsave, .fxrstor, .fxrstor64, .fxsave, .fxsave64 => .none,