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test: Disable a bunch of vector behavior tests for hexagon.
Most of the failures are: * https://github.com/llvm/llvm-project/issues/118879 * https://github.com/llvm/llvm-project/issues/134659 But some are also miscompilations leading to wrong results. I'm not going to investigate the latter further until all the backend crashes have been resolved.
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0a5c088ecc
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5 changed files with 13 additions and 1 deletions
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@ -104,7 +104,11 @@ test {
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_ = @import("behavior/union_with_members.zig");
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_ = @import("behavior/union_with_members.zig");
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_ = @import("behavior/usingnamespace.zig");
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_ = @import("behavior/usingnamespace.zig");
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_ = @import("behavior/var_args.zig");
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_ = @import("behavior/var_args.zig");
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// https://github.com/llvm/llvm-project/issues/118879
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// https://github.com/llvm/llvm-project/issues/134659
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if (!(builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon)) {
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_ = @import("behavior/vector.zig");
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_ = @import("behavior/vector.zig");
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}
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_ = @import("behavior/void.zig");
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_ = @import("behavior/void.zig");
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_ = @import("behavior/while.zig");
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_ = @import("behavior/while.zig");
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_ = @import("behavior/widening.zig");
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_ = @import("behavior/widening.zig");
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@ -621,6 +621,7 @@ test "@intCast on vector" {
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if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;
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const S = struct {
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const S = struct {
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fn doTheTest() !void {
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fn doTheTest() !void {
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@ -2697,6 +2698,7 @@ test "@intCast vector of signed integer" {
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if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;
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var x: @Vector(4, i32) = .{ 1, 2, 3, 4 };
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var x: @Vector(4, i32) = .{ 1, 2, 3, 4 };
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_ = &x;
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_ = &x;
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@ -241,6 +241,7 @@ test "vector cmp f16" {
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if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
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if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
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if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
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if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
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if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;
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try testCmpVector(f16);
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try testCmpVector(f16);
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try comptime testCmpVector(f16);
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try comptime testCmpVector(f16);
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@ -254,6 +255,7 @@ test "vector cmp f32" {
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if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
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if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
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if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
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if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
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if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;
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try testCmpVector(f32);
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try testCmpVector(f32);
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try comptime testCmpVector(f32);
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try comptime testCmpVector(f32);
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@ -266,6 +268,7 @@ test "vector cmp f64" {
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if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
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if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
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if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
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if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
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if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;
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try testCmpVector(f64);
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try testCmpVector(f64);
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try comptime testCmpVector(f64);
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try comptime testCmpVector(f64);
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@ -281,6 +284,7 @@ test "vector cmp f128" {
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if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
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if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
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if (builtin.cpu.arch.isArm()) return error.SkipZigTest;
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if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
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if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;
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try testCmpVector(f128);
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try testCmpVector(f128);
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try comptime testCmpVector(f128);
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try comptime testCmpVector(f128);
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@ -1899,6 +1899,7 @@ test "partially-runtime integer vector division would be illegal if vector eleme
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if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;
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var lhs: @Vector(2, i8) = .{ -128, 5 };
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var lhs: @Vector(2, i8) = .{ -128, 5 };
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const rhs: @Vector(2, i8) = .{ 1, -1 };
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const rhs: @Vector(2, i8) = .{ 1, -1 };
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@ -71,6 +71,7 @@ test "@select compare result" {
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if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf and builtin.target.ofmt != .macho) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf and builtin.target.ofmt != .macho) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon) return error.SkipZigTest;
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const S = struct {
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const S = struct {
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fn min(comptime V: type, lhs: V, rhs: V) V {
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fn min(comptime V: type, lhs: V, rhs: V) V {
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