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std.Target: add CPU features and models for hppa

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Alex Rønne Petersen 2025-11-13 22:29:12 +01:00
parent 2b23f98d2c
commit 39e91deb77
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3 changed files with 328 additions and 1 deletions
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5
lib/std/Target.zig
View file

@ -708,7 +708,7 @@ pub const avr = @import("Target/avr.zig");
pub const bpf = @import("Target/bpf.zig"); pub const bpf = @import("Target/bpf.zig");
pub const csky = @import("Target/csky.zig"); pub const csky = @import("Target/csky.zig");
pub const hexagon = @import("Target/hexagon.zig"); pub const hexagon = @import("Target/hexagon.zig");
pub const hppa = @import("Target/generic.zig"); pub const hppa = @import("Target/hppa.zig");
pub const kalimba = @import("Target/generic.zig"); pub const kalimba = @import("Target/generic.zig");
pub const kvx = @import("Target/kvx.zig"); pub const kvx = @import("Target/kvx.zig");
pub const lanai = @import("Target/lanai.zig"); pub const lanai = @import("Target/lanai.zig");
@ -1947,6 +1947,8 @@ pub const Cpu = struct {
.alpha => &alpha.cpu.ev4, .alpha => &alpha.cpu.ev4,
.amdgcn => &amdgcn.cpu.gfx600, .amdgcn => &amdgcn.cpu.gfx600,
.avr => &avr.cpu.avr1, .avr => &avr.cpu.avr1,
.hppa => &hppa.cpu.ts_1,
.hppa64 => &hppa.cpu.pa_8000,
.kvx => &kvx.cpu.coolidge_v1, .kvx => &kvx.cpu.coolidge_v1,
.loongarch32 => &loongarch.cpu.generic_la32, .loongarch32 => &loongarch.cpu.generic_la32,
.loongarch64 => &loongarch.cpu.generic_la64, .loongarch64 => &loongarch.cpu.generic_la64,
@ -2000,6 +2002,7 @@ pub const Cpu = struct {
.bpfel, .bpfeb => &bpf.cpu.v3, .bpfel, .bpfeb => &bpf.cpu.v3,
.csky => &csky.cpu.ck810, // gcc/clang do not have a generic csky model. .csky => &csky.cpu.ck810, // gcc/clang do not have a generic csky model.
.hexagon => &hexagon.cpu.hexagonv68, // gcc/clang do not have a generic hexagon model. .hexagon => &hexagon.cpu.hexagonv68, // gcc/clang do not have a generic hexagon model.
.hppa => &hppa.cpu.pa_7300lc,
.kvx => &kvx.cpu.coolidge_v2, .kvx => &kvx.cpu.coolidge_v2,
.lanai => &lanai.cpu.v11, // clang does not have a generic lanai model. .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model.
.loongarch64 => &loongarch.cpu.la64v1_0, .loongarch64 => &loongarch.cpu.la64v1_0,

178
lib/std/Target/hppa.zig Normal file
View file

@ -0,0 +1,178 @@
//! This file is auto-generated by tools/update_cpu_features.zig.
const std = @import("../std.zig");
const CpuFeature = std.Target.Cpu.Feature;
const CpuModel = std.Target.Cpu.Model;
pub const Feature = enum {
@"64bit",
max_1,
max_2,
v1_1,
v2_0,
};
pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
pub const all_features = blk: {
const len = @typeInfo(Feature).@"enum".fields.len;
std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
var result: [len]CpuFeature = undefined;
result[@intFromEnum(Feature.@"64bit")] = .{
.llvm_name = null,
.description = "Enable 64-bit PA-RISC 2.0",
.dependencies = featureSet(&[_]Feature{
.v2_0,
}),
};
result[@intFromEnum(Feature.max_1)] = .{
.llvm_name = null,
.description = "Enable MAX-1 multimedia acceleration extensions",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.max_2)] = .{
.llvm_name = null,
.description = "Enable MAX-2 multimedia acceleration extensions",
.dependencies = featureSet(&[_]Feature{
.max_1,
}),
};
result[@intFromEnum(Feature.v1_1)] = .{
.llvm_name = null,
.description = "Enable ISA v1.1",
.dependencies = featureSet(&[_]Feature{}),
};
result[@intFromEnum(Feature.v2_0)] = .{
.llvm_name = null,
.description = "Enable ISA v2.0",
.dependencies = featureSet(&[_]Feature{
.max_2,
.v1_1,
}),
};
const ti = @typeInfo(Feature);
for (&result, 0..) |*elem, i| {
elem.index = i;
elem.name = ti.@"enum".fields[i].name;
}
break :blk result;
};
pub const cpu = struct {
pub const ns_1: CpuModel = .{
.name = "ns_1",
.llvm_name = null,
.features = featureSet(&[_]Feature{}),
};
pub const ns_2: CpuModel = .{
.name = "ns_2",
.llvm_name = null,
.features = featureSet(&[_]Feature{}),
};
pub const pa_7000: CpuModel = .{
.name = "pa_7000",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.v1_1,
}),
};
pub const pa_7100: CpuModel = .{
.name = "pa_7100",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.v1_1,
}),
};
pub const pa_7100lc: CpuModel = .{
.name = "pa_7100lc",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.max_1,
.v1_1,
}),
};
pub const pa_7150: CpuModel = .{
.name = "pa_7150",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.v1_1,
}),
};
pub const pa_7200: CpuModel = .{
.name = "pa_7200",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.v1_1,
}),
};
pub const pa_7300lc: CpuModel = .{
.name = "pa_7300lc",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.max_1,
.v1_1,
}),
};
pub const pa_8000: CpuModel = .{
.name = "pa_8000",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"64bit",
}),
};
pub const pa_8200: CpuModel = .{
.name = "pa_8200",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"64bit",
}),
};
pub const pa_8500: CpuModel = .{
.name = "pa_8500",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"64bit",
}),
};
pub const pa_8600: CpuModel = .{
.name = "pa_8600",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"64bit",
}),
};
pub const pa_8700: CpuModel = .{
.name = "pa_8700",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"64bit",
}),
};
pub const pa_8800: CpuModel = .{
.name = "pa_8800",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"64bit",
}),
};
pub const pa_8900: CpuModel = .{
.name = "pa_8900",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"64bit",
}),
};
pub const pcx: CpuModel = .{
.name = "pcx",
.llvm_name = null,
.features = featureSet(&[_]Feature{}),
};
pub const ts_1: CpuModel = .{
.name = "ts_1",
.llvm_name = null,
.features = featureSet(&[_]Feature{}),
};
};

146
tools/update_cpu_features.zig
View file

@ -1050,6 +1050,152 @@ const targets = [_]ArchTarget{
.td_name = "Hexagon", .td_name = "Hexagon",
}, },
}, },
.{
.zig_name = "hppa",
.llvm = null,
.extra_features = &.{
.{
.zig_name = "64bit",
.desc = "Enable 64-bit PA-RISC 2.0",
.deps = &.{"v2_0"},
},
.{
.zig_name = "max_1",
.desc = "Enable MAX-1 multimedia acceleration extensions",
.deps = &.{},
},
.{
.zig_name = "max_2",
.desc = "Enable MAX-2 multimedia acceleration extensions",
.deps = &.{"max_1"},
},
.{
.zig_name = "v1_1",
.desc = "Enable ISA v1.1",
.deps = &.{},
},
.{
.zig_name = "v2_0",
.desc = "Enable ISA v2.0",
.deps = &.{ "max_2", "v1_1" },
},
},
.extra_cpus = &.{
.{
.llvm_name = null,
.zig_name = "ts_1",
.features = &.{},
},
.{
.llvm_name = null,
.zig_name = "ns_1",
.features = &.{},
},
.{
.llvm_name = null,
.zig_name = "ns_2",
.features = &.{},
},
.{
.llvm_name = null,
.zig_name = "pcx",
.features = &.{},
},
.{
.llvm_name = null,
.zig_name = "pa_7000",
.features = &.{
"v1_1",
},
},
.{
.llvm_name = null,
.zig_name = "pa_7100",
.features = &.{
"v1_1",
},
},
.{
.llvm_name = null,
.zig_name = "pa_7150",
.features = &.{
"v1_1",
},
},
.{
.llvm_name = null,
.zig_name = "pa_7100lc",
.features = &.{
"max_1",
"v1_1",
},
},
.{
.llvm_name = null,
.zig_name = "pa_7200",
.features = &.{
"v1_1",
},
},
.{
.llvm_name = null,
.zig_name = "pa_7300lc",
.features = &.{
"max_1",
"v1_1",
},
},
.{
.llvm_name = null,
.zig_name = "pa_8000",
.features = &.{
"64bit",
},
},
.{
.llvm_name = null,
.zig_name = "pa_8200",
.features = &.{
"64bit",
},
},
.{
.llvm_name = null,
.zig_name = "pa_8500",
.features = &.{
"64bit",
},
},
.{
.llvm_name = null,
.zig_name = "pa_8600",
.features = &.{
"64bit",
},
},
.{
.llvm_name = null,
.zig_name = "pa_8700",
.features = &.{
"64bit",
},
},
.{
.llvm_name = null,
.zig_name = "pa_8800",
.features = &.{
"64bit",
},
},
.{
.llvm_name = null,
.zig_name = "pa_8900",
.features = &.{
"64bit",
},
},
},
},
.{ .{
.zig_name = "kvx", .zig_name = "kvx",
.llvm = null, .llvm = null,