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std.Target: add arceb and xtensaeb Cpu.Arch tags

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Alex Rønne Petersen 2025-10-19 23:32:47 +02:00
parent dda05b29c0
commit 3e2daa509a
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16 changed files with 180 additions and 122 deletions
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229
lib/std/Target.zig
View file

@ -860,12 +860,14 @@ pub const Abi = enum {
// No musl support.
.arc,
.arceb,
=> .gnu,
.csky,
=> .gnueabi,
// No glibc or musl support.
.xtensa,
.xtensaeb,
=> .none,
else => .musl,
@ -1061,12 +1063,12 @@ pub const ObjectFormat = enum {
pub fn toElfMachine(target: *const Target) std.elf.EM {
return switch (target.cpu.arch) {
.amdgcn => .AMDGPU,
.arc => .ARC_COMPACT,
.arm, .armeb, .thumb, .thumbeb => .ARM,
.aarch64, .aarch64_be => .AARCH64,
.amdgcn => .AMDGPU,
.arc, .arceb => .ARC_COMPACT,
.arm, .armeb, .thumb, .thumbeb => .ARM,
.avr => .AVR,
.bpfel, .bpfeb => .BPF,
.bpfeb, .bpfel => .BPF,
.csky => .CSKY,
.hexagon => .QDSP6,
.kalimba => .CSR_KALIMBA,
@ -1087,7 +1089,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
.x86 => .@"386",
.x86_64 => .X86_64,
.xcore => .XCORE,
.xtensa => .XTENSA,
.xtensa, .xtensaeb => .XTENSA,
.nvptx,
.nvptx64,
@ -1118,6 +1120,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
.aarch64_be,
.amdgcn,
.arc,
.arceb,
.armeb,
.avr,
.bpfeb,
@ -1149,6 +1152,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
.wasm64,
.xcore,
.xtensa,
.xtensaeb,
=> .UNKNOWN,
};
}
@ -1317,17 +1321,16 @@ pub const Cpu = struct {
};
pub const Arch = enum {
amdgcn,
arc,
arm,
armeb,
thumb,
thumbeb,
aarch64,
aarch64_be,
amdgcn,
arc,
arceb,
arm,
armeb,
avr,
bpfel,
bpfeb,
bpfel,
csky,
hexagon,
kalimba,
@ -1340,9 +1343,9 @@ pub const Cpu = struct {
mips64,
mips64el,
msp430,
or1k,
nvptx,
nvptx64,
or1k,
powerpc,
powerpcle,
powerpc64,
@ -1357,6 +1360,8 @@ pub const Cpu = struct {
sparc64,
spirv32,
spirv64,
thumb,
thumbeb,
ve,
wasm32,
wasm64,
@ -1364,6 +1369,7 @@ pub const Cpu = struct {
x86_64,
xcore,
xtensa,
xtensaeb,
// LLVM tags deliberately omitted:
// - aarch64_32
@ -1418,12 +1424,12 @@ pub const Cpu = struct {
pub inline fn family(arch: Arch) Family {
return switch (arch) {
.amdgcn => .amdgcn,
.arc => .arc,
.arm, .armeb, .thumb, .thumbeb => .arm,
.aarch64, .aarch64_be => .aarch64,
.amdgcn => .amdgcn,
.arc, .arceb => .arc,
.arm, .armeb, .thumb, .thumbeb => .arm,
.avr => .avr,
.bpfel, .bpfeb => .bpf,
.bpfeb, .bpfel => .bpf,
.csky => .csky,
.hexagon => .hexagon,
.kalimba => .kalimba,
@ -1444,7 +1450,7 @@ pub const Cpu = struct {
.wasm32, .wasm64 => .wasm,
.x86, .x86_64 => .x86,
.xcore => .xcore,
.xtensa => .xtensa,
.xtensa, .xtensaeb => .xtensa,
};
}
@ -1477,6 +1483,13 @@ pub const Cpu = struct {
};
}
pub inline fn isArc(arch: Arch) bool {
return switch (arch) {
.arc, .arceb => true,
else => false,
};
}
pub inline fn isWasm(arch: Arch) bool {
return switch (arch) {
.wasm32, .wasm64 => true,
@ -1573,6 +1586,13 @@ pub const Cpu = struct {
};
}
pub inline fn isXtensa(arch: Arch) bool {
return switch (arch) {
.xtensa, .xtensaeb => true,
else => false,
};
}
pub fn parseCpuModel(arch: Arch, cpu_name: []const u8) !*const Cpu.Model {
for (arch.allCpuModels()) |cpu| {
if (std.mem.eql(u8, cpu_name, cpu.name)) {
@ -1584,43 +1604,39 @@ pub const Cpu = struct {
pub fn endian(arch: Arch) std.builtin.Endian {
return switch (arch) {
.avr,
.arm,
.aarch64,
.amdgcn,
.arm,
.arc,
.avr,
.bpfel,
.csky,
.xtensa,
.hexagon,
.kalimba,
.loongarch32,
.loongarch64,
.mipsel,
.mips64el,
.msp430,
.nvptx,
.nvptx64,
.powerpcle,
.powerpc64le,
.propeller,
.riscv32,
.riscv64,
.x86,
.x86_64,
.wasm32,
.wasm64,
.xcore,
.thumb,
.ve,
// GPU bitness is opaque. For now, assume little endian.
.spirv32,
.spirv64,
.loongarch32,
.loongarch64,
.arc,
.propeller,
.wasm32,
.wasm64,
.x86,
.x86_64,
.xcore,
.xtensa,
=> .little,
.armeb,
.aarch64_be,
.arceb,
.armeb,
.bpfeb,
.lanai,
.m68k,
.mips,
.mips64,
@ -1629,12 +1645,20 @@ pub const Cpu = struct {
.powerpc64,
.riscv32be,
.riscv64be,
.s390x,
.thumbeb,
.sparc,
.sparc64,
.lanai,
.s390x,
.xtensaeb,
=> .big,
// GPU endianness is opaque. For now, assume little endian.
.amdgcn,
.nvptx,
.nvptx64,
.spirv32,
.spirv64,
=> .little,
};
}
@ -1770,7 +1794,7 @@ pub const Cpu = struct {
.arc_sysv,
.arc_interrupt,
=> &.{.arc},
=> &.{ .arc, .arceb },
.avr_gnu,
.avr_builtin,
@ -1826,7 +1850,7 @@ pub const Cpu = struct {
.xtensa_call0,
.xtensa_windowed,
=> &.{.xtensa},
=> &.{ .xtensa, .xtensaeb },
.amdgcn_device,
.amdgcn_kernel,
@ -2418,9 +2442,10 @@ pub const DynamicLinker = struct {
}
else if (abi.isGnu())
switch (cpu.arch) {
// TODO: `eb` architecture support.
// TODO: `700` ABI support.
.arc => if (abi == .gnu) init("/lib/ld-linux-arc.so.2") else none,
.arc,
.arceb,
=> |arch| if (abi == .gnu) initFmt("/lib/ld-linux-{t}.so.2", .{arch}) else none,
.arm,
.armeb,
@ -2450,7 +2475,10 @@ pub const DynamicLinker = struct {
else => return none,
}}),
.m68k => if (abi == .gnu) init("/lib/ld.so.1") else none,
.m68k,
.xtensa,
.xtensaeb,
=> if (abi == .gnu) init("/lib/ld.so.1") else none,
.mips,
.mipsel,
@ -2480,6 +2508,7 @@ pub const DynamicLinker = struct {
=> init("/lib/ld.so.1"),
else => none,
},
.powerpc64,
.powerpc64le,
=> if (abi == .gnu) init("/lib64/ld64.so.2") else none,
@ -2512,8 +2541,6 @@ pub const DynamicLinker = struct {
else => none,
},
.xtensa => if (abi == .gnu) init("/lib/ld.so.1") else none,
else => none,
}
else
@ -2680,52 +2707,54 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
=> 16,
.arc,
.arceb,
.arm,
.armeb,
.csky,
.hexagon,
.kalimba,
.lanai,
.loongarch32,
.m68k,
.mips,
.mipsel,
.nvptx,
.or1k,
.powerpc,
.powerpcle,
.propeller,
.riscv32,
.riscv32be,
.thumb,
.thumbeb,
.x86,
.xcore,
.nvptx,
.kalimba,
.lanai,
.wasm32,
.sparc,
.spirv32,
.loongarch32,
.thumb,
.thumbeb,
.wasm32,
.x86,
.xcore,
.xtensa,
.propeller,
.xtensaeb,
=> 32,
.aarch64,
.aarch64_be,
.amdgcn,
.bpfeb,
.bpfel,
.loongarch64,
.mips64,
.mips64el,
.nvptx64,
.powerpc64,
.powerpc64le,
.riscv64,
.riscv64be,
.x86_64,
.nvptx64,
.wasm64,
.amdgcn,
.bpfel,
.bpfeb,
.sparc64,
.s390x,
.ve,
.sparc64,
.spirv64,
.loongarch64,
.ve,
.wasm64,
.x86_64,
=> 64,
};
}
@ -2788,13 +2817,12 @@ pub fn cCharSignedness(target: *const Target) std.builtin.Signedness {
if (target.os.tag.isDarwin() or target.os.tag == .windows or target.os.tag == .uefi) return .signed;
return switch (target.cpu.arch) {
.arm,
.armeb,
.thumb,
.thumbeb,
.aarch64,
.aarch64_be,
.arm,
.armeb,
.arc,
.arceb,
.csky,
.hexagon,
.msp430,
@ -2807,8 +2835,11 @@ pub fn cCharSignedness(target: *const Target) std.builtin.Signedness {
.riscv32be,
.riscv64,
.riscv64be,
.thumb,
.thumbeb,
.xcore,
.xtensa,
.xtensaeb,
=> .unsigned,
else => .signed,
};
@ -3217,31 +3248,33 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
=> 2,
.arc,
.arceb,
.csky,
.kalimba,
.or1k,
.propeller,
.x86,
.xcore,
.or1k,
.kalimba,
.xtensa,
.propeller,
.xtensaeb,
=> 4,
.amdgcn,
.arm,
.armeb,
.thumb,
.thumbeb,
.amdgcn,
.bpfel,
.bpfeb,
.bpfel,
.hexagon,
.lanai,
.m68k,
.mips,
.mipsel,
.sparc,
.lanai,
.nvptx,
.nvptx64,
.s390x,
.sparc,
.thumb,
.thumbeb,
=> 8,
.aarch64,
@ -3261,10 +3294,10 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
.sparc64,
.spirv32,
.spirv64,
.x86_64,
.ve,
.wasm32,
.wasm64,
.x86_64,
=> 16,
.avr,
@ -3276,7 +3309,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
// Overrides for unusual alignments
switch (target.cpu.arch) {
.arc => switch (c_type) {
.arc, .arceb => switch (c_type) {
.longdouble => return 4,
else => {},
},
@ -3315,31 +3348,33 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
.msp430 => 2,
.arc,
.arceb,
.csky,
.xcore,
.or1k,
.kalimba,
.xtensa,
.or1k,
.propeller,
.xcore,
.xtensa,
.xtensaeb,
=> 4,
.amdgcn,
.arm,
.armeb,
.thumb,
.thumbeb,
.amdgcn,
.bpfel,
.bpfeb,
.bpfel,
.hexagon,
.x86,
.lanai,
.m68k,
.mips,
.mipsel,
.sparc,
.lanai,
.nvptx,
.nvptx64,
.s390x,
.sparc,
.thumb,
.thumbeb,
.x86,
=> 8,
.aarch64,
@ -3359,10 +3394,10 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
.sparc64,
.spirv32,
.spirv64,
.x86_64,
.ve,
.wasm32,
.wasm64,
.x86_64,
=> 16,
.avr,
@ -3378,6 +3413,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
.msp430 => 2,
.arc,
.arceb,
.csky,
.kalimba,
.or1k,
@ -3403,6 +3439,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
.thumbeb,
.x86,
.xtensa,
.xtensaeb,
=> 8,
.aarch64,
@ -3440,9 +3477,9 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
.windows, .uefi => .{ .x86_win = .{} },
else => .{ .x86_sysv = .{} },
},
.aarch64, .aarch64_be => if (target.os.tag.isDarwin()) cc: {
break :cc .{ .aarch64_aapcs_darwin = .{} };
} else switch (target.os.tag) {
.aarch64, .aarch64_be => if (target.os.tag.isDarwin())
.{ .aarch64_aapcs_darwin = .{} }
else switch (target.os.tag) {
.windows => .{ .aarch64_aapcs_win = .{} },
else => .{ .aarch64_aapcs = .{} },
},
@ -3469,7 +3506,7 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
else => .{ .powerpc_sysv = .{} },
},
.wasm32, .wasm64 => .{ .wasm_mvp = .{} },
.arc => .{ .arc_sysv = .{} },
.arc, .arceb => .{ .arc_sysv = .{} },
.avr => .avr_gnu,
.bpfel, .bpfeb => .{ .bpf_std = .{} },
.csky => .{ .csky_sysv = .{} },
@ -3488,7 +3525,7 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
.s390x => .{ .s390x_sysv = .{} },
.ve => .{ .ve_sysv = .{} },
.xcore => .{ .xcore_xs1 = .{} },
.xtensa => .{ .xtensa_call0 = .{} },
.xtensa, .xtensaeb => .{ .xtensa_call0 = .{} },
.amdgcn => .{ .amdgcn_device = .{} },
.nvptx, .nvptx64 => .nvptx_device,
.spirv32, .spirv64 => .spirv_device,

1
lib/std/atomic.zig
View file

@ -419,6 +419,7 @@ pub fn cacheLineForCpu(cpu: std.Target.Cpu) u16 {
.aarch64,
.aarch64_be,
.arc,
.arceb,
.powerpc64,
.powerpc64le,
=> 128,

7
lib/std/builtin.zig
View file

@ -275,7 +275,7 @@ pub const CallingConvention = union(enum(u8)) {
/// The standard `wasm32` and `wasm64` calling convention, as specified in the WebAssembly Tool Conventions.
wasm_mvp: CommonOptions,
/// The standard `arc` calling convention.
/// The standard `arc`/`arceb` calling convention.
arc_sysv: CommonOptions,
arc_interrupt: ArcInterruptOptions,
@ -331,7 +331,7 @@ pub const CallingConvention = union(enum(u8)) {
xcore_xs1: CommonOptions,
xcore_xs2: CommonOptions,
// Calling conventions for the `xtensa` architecture.
// Calling conventions for the `xtensa`/`xtensaeb` architecture.
xtensa_call0: CommonOptions,
xtensa_windowed: CommonOptions,
@ -920,6 +920,7 @@ pub const VaList = switch (builtin.cpu.arch) {
.x86,
=> *u8,
.arc,
.arceb,
.avr,
.bpfel,
.bpfeb,
@ -966,7 +967,7 @@ pub const VaList = switch (builtin.cpu.arch) {
},
else => VaListX86_64,
},
.xtensa => VaListXtensa,
.xtensa, .xtensaeb => VaListXtensa,
else => @compileError("VaList not supported for this target yet"),
};

4
lib/std/builtin/assembly.zig
View file

@ -779,7 +779,7 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) {
lr: bool = false,
sr: bool = false,
},
.xtensa => packed struct {
.xtensa, .xtensaeb => packed struct {
/// Whether the inline assembly code may perform stores to memory
/// addresses other than those derived from input pointer provenance.
memory: bool = false,
@ -1591,7 +1591,7 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) {
vr30: bool = false,
vr31: bool = false,
},
.arc => packed struct {
.arc, .arceb => packed struct {
/// Whether the inline assembly code may perform stores to memory
/// addresses other than those derived from input pointer provenance.
memory: bool = false,

6
lib/std/debug/Dwarf.zig
View file

@ -1430,7 +1430,7 @@ pub fn compactUnwindToDwarfRegNumber(unwind_reg_number: u3) !u16 {
pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
return switch (arch) {
.aarch64, .aarch64_be => 32,
.arc => 160,
.arc, .arceb => 160,
.arm, .armeb, .thumb, .thumbeb => 15,
.csky => 64,
.hexagon => 76,
@ -1453,7 +1453,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
return switch (arch) {
.aarch64, .aarch64_be => 29,
.arc => 27,
.arc, .arceb => 27,
.arm, .armeb, .thumb, .thumbeb => 11,
.csky => 14,
.hexagon => 30,
@ -1476,7 +1476,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {
return switch (arch) {
.aarch64, .aarch64_be => 31,
.arc => 28,
.arc, .arceb => 28,
.arm, .armeb, .thumb, .thumbeb => 13,
.csky => 14,
.hexagon => 29,

2
lib/std/debug/SelfInfo/Elf.zig
View file

@ -102,7 +102,7 @@ pub const can_unwind: bool = s: {
.x86,
.x86_64,
},
// Not supported yet: arm/armeb/thumb/thumbeb, xtensa
// Not supported yet: arm/armeb/thumb/thumbeb, xtensa/xtensaeb
.linux => &.{
.aarch64,
.aarch64_be,

10
lib/std/debug/cpu_context.zig
View file

@ -5,7 +5,7 @@ pub const Native = if (@hasDecl(root, "debug") and @hasDecl(root.debug, "CpuCont
root.debug.CpuContext
else switch (native_arch) {
.aarch64, .aarch64_be => Aarch64,
.arc => Arc,
.arc, .arceb => Arc,
.arm, .armeb, .thumb, .thumbeb => Arm,
.csky => Csky,
.hexagon => Hexagon,
@ -36,7 +36,7 @@ pub fn fromPosixSignalContext(ctx_ptr: ?*const anyopaque) ?Native {
const uc: *const signal_ucontext_t = @ptrCast(@alignCast(ctx_ptr));
// Deal with some special cases first.
if (native_arch == .arc and native_os == .linux) {
if (native_arch.isArc() and native_os == .linux) {
var native: Native = .{
.r = [_]u32{ uc.mcontext.r31, uc.mcontext.r30, 0, uc.mcontext.r28 } ++
uc.mcontext.r27_26 ++
@ -1553,6 +1553,7 @@ const signal_ucontext_t = switch (native_os) {
},
// https://github.com/torvalds/linux/blob/cd5a0afbdf8033dc83786315d63f8b325bdba2fd/include/uapi/asm-generic/ucontext.h
.arc,
.arceb,
.csky,
.hexagon,
.m68k,
@ -1565,13 +1566,14 @@ const signal_ucontext_t = switch (native_os) {
.x86,
.x86_64,
.xtensa,
.xtensaeb,
=> extern struct {
_flags: usize,
_link: ?*signal_ucontext_t,
_stack: std.os.linux.stack_t,
mcontext: switch (native_arch) {
// https://github.com/torvalds/linux/blob/cd5a0afbdf8033dc83786315d63f8b325bdba2fd/arch/arc/include/uapi/asm/sigcontext.h
.arc => extern struct {
.arc, .arceb => extern struct {
_pad1: u32,
_bta: u32,
_lp: extern struct {
@ -1691,7 +1693,7 @@ const signal_ucontext_t = switch (native_os) {
rip: u64,
},
// https://github.com/torvalds/linux/blob/cd5a0afbdf8033dc83786315d63f8b325bdba2fd/arch/xtensa/include/uapi/asm/sigcontext.h
.xtensa => extern struct {
.xtensa, .xtensaeb => extern struct {
pc: u32,
_ps: u32,
_l: extern struct {

8
lib/std/heap.zig
View file

@ -824,7 +824,7 @@ const page_size_min_default: ?usize = switch (builtin.os.tag) {
.emscripten => 64 << 10,
.linux => switch (builtin.cpu.arch) {
// Linux/arch/*/Kconfig
.arc => 4 << 10,
.arc, .arceb => 4 << 10,
.thumb, .thumbeb, .arm, .armeb => 4 << 10,
.aarch64, .aarch64_be => 4 << 10,
.csky => 4 << 10,
@ -839,7 +839,7 @@ const page_size_min_default: ?usize = switch (builtin.os.tag) {
.sparc => 4 << 10,
.sparc64 => 8 << 10,
.x86, .x86_64 => 4 << 10,
.xtensa => 4 << 10,
.xtensa, .xtensaeb => 4 << 10,
else => null,
},
.freestanding, .other => switch (builtin.cpu.arch) {
@ -972,7 +972,7 @@ const page_size_max_default: ?usize = switch (builtin.os.tag) {
.emscripten => 64 << 10,
.linux => switch (builtin.cpu.arch) {
// Linux/arch/*/Kconfig
.arc => 16 << 10,
.arc, .arceb => 16 << 10,
.thumb, .thumbeb, .arm, .armeb => 4 << 10,
.aarch64, .aarch64_be => 64 << 10,
.csky => 4 << 10,
@ -987,7 +987,7 @@ const page_size_max_default: ?usize = switch (builtin.os.tag) {
.sparc => 4 << 10,
.sparc64 => 8 << 10,
.x86, .x86_64 => 4 << 10,
.xtensa => 4 << 10,
.xtensa, .xtensaeb => 4 << 10,
else => null,
},
.freestanding => switch (builtin.cpu.arch) {

11
lib/std/os/linux.zig
View file

@ -116,7 +116,7 @@ pub const SECCOMP = @import("linux/seccomp.zig");
pub const syscalls = @import("linux/syscalls.zig");
pub const SYS = switch (native_arch) {
.arc => syscalls.Arc,
.arc, .arceb => syscalls.Arc,
.aarch64, .aarch64_be => syscalls.Arm64,
.arm, .armeb, .thumb, .thumbeb => syscalls.Arm,
.csky => syscalls.CSky,
@ -141,7 +141,7 @@ pub const SYS = switch (native_arch) {
.gnux32, .muslx32 => syscalls.X32,
else => syscalls.X64,
},
.xtensa => syscalls.Xtensa,
.xtensa, .xtensaeb => syscalls.Xtensa,
else => @compileError("The Zig Standard Library is missing syscall definitions for the target CPU architecture"),
};
@ -3686,7 +3686,7 @@ pub const PROT = struct {
pub const EXEC = 0x4;
/// page may be used for atomic ops
pub const SEM = switch (native_arch) {
.mips, .mipsel, .mips64, .mips64el, .xtensa => 0x10,
.mips, .mipsel, .mips64, .mips64el, .xtensa, .xtensaeb => 0x10,
else => 0x8,
};
/// mprotect flag: extend change to start of growsdown vma
@ -6161,6 +6161,7 @@ pub fn CPU_COUNT(set: cpu_set_t) cpu_count_t {
pub const MINSIGSTKSZ = switch (native_arch) {
.arc,
.arceb,
.arm,
.armeb,
.csky,
@ -6181,6 +6182,7 @@ pub const MINSIGSTKSZ = switch (native_arch) {
.x86,
.x86_64,
.xtensa,
.xtensaeb,
=> 2048,
.loongarch64,
.sparc,
@ -6196,6 +6198,7 @@ pub const MINSIGSTKSZ = switch (native_arch) {
};
pub const SIGSTKSZ = switch (native_arch) {
.arc,
.arceb,
.arm,
.armeb,
.csky,
@ -6216,6 +6219,7 @@ pub const SIGSTKSZ = switch (native_arch) {
.x86,
.x86_64,
.xtensa,
.xtensaeb,
=> 8192,
.aarch64,
.aarch64_be,
@ -9740,6 +9744,7 @@ pub const AUDIT = struct {
.armeb, .thumbeb => .ARMEB,
.aarch64 => .AARCH64,
.arc => .ARCV2,
.arceb => .ARCV2BE,
.csky => .CSKY,
.hexagon => .HEXAGON,
.loongarch32 => .LOONGARCH32,

3
lib/std/os/linux/tls.zig
View file

@ -64,6 +64,7 @@ const Variant = enum {
const current_variant: Variant = switch (native_arch) {
.arc,
.arceb,
.arm,
.armeb,
.aarch64,
@ -243,7 +244,7 @@ pub fn setThreadPointer(addr: usize) void {
: [addr] "r" (addr),
);
},
.arc => {
.arc, .arceb => {
// We apparently need to both set r25 (TP) *and* inform the kernel...
asm volatile (
\\ mov r25, %[addr]

4
lib/std/pie.zig
View file

@ -22,7 +22,7 @@ const R_SPARC_RELATIVE = 22;
const R_RELATIVE = switch (builtin.cpu.arch) {
.x86 => R_386_RELATIVE,
.x86_64 => R_AMD64_RELATIVE,
.arc => R_ARC_RELATIVE,
.arc, .arceb => R_ARC_RELATIVE,
.arm, .armeb, .thumb, .thumbeb => R_ARM_RELATIVE,
.aarch64, .aarch64_be => R_AARCH64_RELATIVE,
.csky => R_CSKY_RELATIVE,
@ -58,7 +58,7 @@ inline fn getDynamicSymbol() [*]const elf.Dyn {
\\ lea _DYNAMIC(%%rip), %[ret]
: [ret] "=r" (-> [*]const elf.Dyn),
),
.arc => asm volatile (
.arc, .arceb => asm volatile (
\\ .weak _DYNAMIC
\\ .hidden _DYNAMIC
\\ add %[ret], pcl, _DYNAMIC@pcl

4
lib/std/start.zig
View file

@ -195,7 +195,7 @@ fn _start() callconv(.naked) noreturn {
// This is the first userspace frame. Prevent DWARF-based unwinders from unwinding further. We
// prevent FP-based unwinders from unwinding further by zeroing the register below.
if (builtin.unwind_tables != .none or !builtin.strip_debug_info) asm volatile (switch (native_arch) {
.arc => ".cfi_undefined blink",
.arc, .arceb => ".cfi_undefined blink",
.arm, .armeb, .thumb, .thumbeb => "", // https://github.com/llvm/llvm-project/issues/115891
.aarch64, .aarch64_be => ".cfi_undefined lr",
.csky => ".cfi_undefined lr",
@ -253,7 +253,7 @@ fn _start() callconv(.naked) noreturn {
\\ and sp, x0, #-16
\\ b %[posixCallMainAndExit]
,
.arc =>
.arc, .arceb =>
// ARC v1 and v2 had a very low stack alignment requirement of 4; v3 increased it to 16.
\\ mov fp, 0
\\ mov blink, 0

1
lib/std/zig/system.zig
View file

@ -119,6 +119,7 @@ pub fn getExternalExecutor(
.thumb,
.thumbeb,
.xtensa,
.xtensaeb,
=> |t| switch (candidate.os.tag) {
.linux,
=> .{ .qemu = switch (t) {

6
src/codegen/llvm.zig
View file

@ -106,9 +106,11 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8
.wasm64 => "wasm64",
.ve => "ve",
.arceb,
.kalimba,
.or1k,
.propeller,
.xtensaeb,
=> unreachable, // Gated by hasLlvmSupport().
};
@ -473,9 +475,11 @@ pub fn dataLayout(target: *const std.Target) []const u8 {
.loongarch64 => "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128",
.xtensa => "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32",
.arceb,
.kalimba,
.or1k,
.propeller,
.xtensaeb,
=> unreachable, // Gated by hasLlvmSupport().
};
}
@ -13107,9 +13111,11 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
},
// LLVM does does not have a backend for these.
.arceb,
.kalimba,
.or1k,
.propeller,
.xtensaeb,
=> unreachable,
}
}

4
src/target.zig
View file

@ -216,9 +216,11 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat)
=> false,
// No LLVM backend exists.
.arceb,
.kalimba,
.or1k,
.propeller,
.xtensaeb,
=> false,
};
}
@ -711,6 +713,7 @@ pub fn minFunctionAlignment(target: *const std.Target) Alignment {
.xcore,
=> .@"2",
.arc,
.arceb,
.arm,
.armeb,
.aarch64,
@ -728,6 +731,7 @@ pub fn minFunctionAlignment(target: *const std.Target) Alignment {
.sparc,
.sparc64,
.xtensa,
.xtensaeb,
=> .@"4",
.bpfel,
.bpfeb,

2
test/tests.zig
View file

@ -1550,7 +1550,7 @@ const CAbiTarget = struct {
};
const c_abi_targets = blk: {
@setEvalBranchQuota(20000);
@setEvalBranchQuota(30000);
break :blk [_]CAbiTarget{
// Native Targets