mirror of
https://codeberg.org/ziglang/zig.git
synced 2025-12-06 05:44:20 +00:00
update_cpu_features: Handle targets that don't have LLVM data.
This commit is contained in:
Alex Rønne Petersen
parent
b541a7af11
commit
5248f0a909
1 changed files with 343 additions and 286 deletions
|
|
@ -34,10 +34,12 @@ const Feature = struct {
|
|||
flatten: bool = false,
|
||||
};
|
||||
|
||||
const LlvmTarget = struct {
|
||||
const ArchTarget = struct {
|
||||
zig_name: []const u8,
|
||||
llvm_name: []const u8,
|
||||
llvm: ?struct {
|
||||
name: []const u8,
|
||||
td_name: []const u8,
|
||||
},
|
||||
feature_overrides: []const FeatureOverride = &.{},
|
||||
extra_cpus: []const Cpu = &.{},
|
||||
extra_features: []const Feature = &.{},
|
||||
|
|
@ -45,11 +47,13 @@ const LlvmTarget = struct {
|
|||
branch_quota: ?usize = null,
|
||||
};
|
||||
|
||||
const llvm_targets = [_]LlvmTarget{
|
||||
const targets = [_]ArchTarget{
|
||||
.{
|
||||
.zig_name = "aarch64",
|
||||
.llvm_name = "AArch64",
|
||||
.td_name = "AArch64.td",
|
||||
.llvm = .{
|
||||
.name = "AArch64",
|
||||
.td_name = "AArch64",
|
||||
},
|
||||
.branch_quota = 2000,
|
||||
.feature_overrides = &.{
|
||||
.{
|
||||
|
|
@ -391,8 +395,10 @@ const llvm_targets = [_]LlvmTarget{
|
|||
},
|
||||
.{
|
||||
.zig_name = "amdgcn",
|
||||
.llvm_name = "AMDGPU",
|
||||
.td_name = "AMDGPU.td",
|
||||
.llvm = .{
|
||||
.name = "AMDGPU",
|
||||
.td_name = "AMDGPU",
|
||||
},
|
||||
.feature_overrides = &.{
|
||||
.{
|
||||
.llvm_name = "DumpCode",
|
||||
|
|
@ -418,13 +424,17 @@ const llvm_targets = [_]LlvmTarget{
|
|||
},
|
||||
.{
|
||||
.zig_name = "arc",
|
||||
.llvm_name = "ARC",
|
||||
.td_name = "ARC.td",
|
||||
.llvm = .{
|
||||
.name = "ARC",
|
||||
.td_name = "ARC",
|
||||
},
|
||||
},
|
||||
.{
|
||||
.zig_name = "arm",
|
||||
.llvm_name = "ARM",
|
||||
.td_name = "ARM.td",
|
||||
.llvm = .{
|
||||
.name = "ARM",
|
||||
.td_name = "ARM",
|
||||
},
|
||||
.branch_quota = 10000,
|
||||
.feature_overrides = &.{
|
||||
.{
|
||||
|
|
@ -928,66 +938,90 @@ const llvm_targets = [_]LlvmTarget{
|
|||
},
|
||||
.{
|
||||
.zig_name = "avr",
|
||||
.llvm_name = "AVR",
|
||||
.td_name = "AVR.td",
|
||||
.llvm = .{
|
||||
.name = "AVR",
|
||||
.td_name = "AVR",
|
||||
},
|
||||
},
|
||||
.{
|
||||
.zig_name = "bpf",
|
||||
.llvm_name = "BPF",
|
||||
.td_name = "BPF.td",
|
||||
.llvm = .{
|
||||
.name = "BPF",
|
||||
.td_name = "BPF",
|
||||
},
|
||||
},
|
||||
.{
|
||||
.zig_name = "csky",
|
||||
.llvm_name = "CSKY",
|
||||
.td_name = "CSKY.td",
|
||||
.llvm = .{
|
||||
.name = "CSKY",
|
||||
.td_name = "CSKY",
|
||||
},
|
||||
},
|
||||
.{
|
||||
.zig_name = "hexagon",
|
||||
.llvm_name = "Hexagon",
|
||||
.td_name = "Hexagon.td",
|
||||
.llvm = .{
|
||||
.name = "Hexagon",
|
||||
.td_name = "Hexagon",
|
||||
},
|
||||
},
|
||||
.{
|
||||
.zig_name = "lanai",
|
||||
.llvm_name = "Lanai",
|
||||
.td_name = "Lanai.td",
|
||||
.llvm = .{
|
||||
.name = "Lanai",
|
||||
.td_name = "Lanai",
|
||||
},
|
||||
},
|
||||
.{
|
||||
.zig_name = "loongarch",
|
||||
.llvm_name = "LoongArch",
|
||||
.td_name = "LoongArch.td",
|
||||
.llvm = .{
|
||||
.name = "LoongArch",
|
||||
.td_name = "LoongArch",
|
||||
},
|
||||
},
|
||||
.{
|
||||
.zig_name = "m68k",
|
||||
.llvm_name = "M68k",
|
||||
.td_name = "M68k.td",
|
||||
.llvm = .{
|
||||
.name = "M68k",
|
||||
.td_name = "M68k",
|
||||
},
|
||||
},
|
||||
.{
|
||||
.zig_name = "msp430",
|
||||
.llvm_name = "MSP430",
|
||||
.td_name = "MSP430.td",
|
||||
.llvm = .{
|
||||
.name = "MSP430",
|
||||
.td_name = "MSP430",
|
||||
},
|
||||
},
|
||||
.{
|
||||
.zig_name = "mips",
|
||||
.llvm_name = "Mips",
|
||||
.td_name = "Mips.td",
|
||||
.llvm = .{
|
||||
.name = "Mips",
|
||||
.td_name = "Mips",
|
||||
},
|
||||
},
|
||||
.{
|
||||
.zig_name = "nvptx",
|
||||
.llvm_name = "NVPTX",
|
||||
.td_name = "NVPTX.td",
|
||||
.llvm = .{
|
||||
.name = "NVPTX",
|
||||
.td_name = "NVPTX",
|
||||
},
|
||||
},
|
||||
.{
|
||||
.zig_name = "powerpc",
|
||||
.llvm_name = "PowerPC",
|
||||
.td_name = "PPC.td",
|
||||
.llvm = .{
|
||||
.name = "PowerPC",
|
||||
.td_name = "PPC",
|
||||
},
|
||||
.omit_cpus = &.{
|
||||
"ppc32",
|
||||
},
|
||||
},
|
||||
.{
|
||||
.zig_name = "riscv",
|
||||
.llvm_name = "RISCV",
|
||||
.td_name = "RISCV.td",
|
||||
.llvm = .{
|
||||
.name = "RISCV",
|
||||
.td_name = "RISCV",
|
||||
},
|
||||
.branch_quota = 2000,
|
||||
.feature_overrides = &.{
|
||||
.{
|
||||
|
|
@ -1010,29 +1044,38 @@ const llvm_targets = [_]LlvmTarget{
|
|||
},
|
||||
.{
|
||||
.zig_name = "sparc",
|
||||
.llvm_name = "Sparc",
|
||||
.td_name = "Sparc.td",
|
||||
.llvm = .{
|
||||
.name = "Sparc",
|
||||
.td_name = "Sparc",
|
||||
},
|
||||
},
|
||||
// TODO: merge tools/update_spirv_features.zig into this script
|
||||
//.{
|
||||
// .zig_name = "spirv",
|
||||
// .llvm_name = "SPIRV",
|
||||
// .td_name = "SPIRV.td",
|
||||
// .llvm = .{
|
||||
// .name = "SPIRV",
|
||||
// },
|
||||
//},
|
||||
.{
|
||||
.zig_name = "s390x",
|
||||
.llvm_name = "SystemZ",
|
||||
.td_name = "SystemZ.td",
|
||||
.llvm = .{
|
||||
.name = "SystemZ",
|
||||
.td_name = "SystemZ",
|
||||
},
|
||||
},
|
||||
.{
|
||||
.zig_name = "ve",
|
||||
.llvm_name = "VE",
|
||||
.td_name = "VE.td",
|
||||
.llvm = .{
|
||||
.name = "VE",
|
||||
.td_name = "VE",
|
||||
},
|
||||
},
|
||||
.{
|
||||
.zig_name = "wasm",
|
||||
.llvm_name = "WebAssembly",
|
||||
.td_name = "WebAssembly.td",
|
||||
.llvm = .{
|
||||
.name = "WebAssembly",
|
||||
.td_name = "WebAssembly",
|
||||
},
|
||||
.extra_features = &.{
|
||||
.{
|
||||
.zig_name = "nontrapping_bulk_memory_len0",
|
||||
|
|
@ -1057,8 +1100,10 @@ const llvm_targets = [_]LlvmTarget{
|
|||
},
|
||||
.{
|
||||
.zig_name = "x86",
|
||||
.llvm_name = "X86",
|
||||
.td_name = "X86.td",
|
||||
.llvm = .{
|
||||
.name = "X86",
|
||||
.td_name = "X86",
|
||||
},
|
||||
.feature_overrides = &.{
|
||||
.{
|
||||
.llvm_name = "64bit-mode",
|
||||
|
|
@ -1362,13 +1407,17 @@ const llvm_targets = [_]LlvmTarget{
|
|||
},
|
||||
.{
|
||||
.zig_name = "xcore",
|
||||
.llvm_name = "XCore",
|
||||
.td_name = "XCore.td",
|
||||
.llvm = .{
|
||||
.name = "XCore",
|
||||
.td_name = "XCore",
|
||||
},
|
||||
},
|
||||
.{
|
||||
.zig_name = "xtensa",
|
||||
.llvm_name = "Xtensa",
|
||||
.td_name = "Xtensa.td",
|
||||
.llvm = .{
|
||||
.name = "Xtensa",
|
||||
.td_name = "Xtensa",
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -1413,33 +1462,33 @@ pub fn main() anyerror!void {
|
|||
var zig_src_dir = try fs.cwd().openDir(zig_src_root, .{});
|
||||
defer zig_src_dir.close();
|
||||
|
||||
const root_progress = std.Progress.start(.{ .estimated_total_items = llvm_targets.len });
|
||||
const root_progress = std.Progress.start(.{ .estimated_total_items = targets.len });
|
||||
defer root_progress.end();
|
||||
|
||||
if (builtin.single_threaded) {
|
||||
for (llvm_targets) |llvm_target| {
|
||||
if (filter) |zig_name| if (!std.mem.eql(u8, llvm_target.zig_name, zig_name)) continue;
|
||||
for (targets) |target| {
|
||||
if (filter) |zig_name| if (!std.mem.eql(u8, target.zig_name, zig_name)) continue;
|
||||
try processOneTarget(.{
|
||||
.llvm_tblgen_exe = llvm_tblgen_exe,
|
||||
.llvm_src_root = llvm_src_root,
|
||||
.zig_src_dir = zig_src_dir,
|
||||
.root_progress = root_progress,
|
||||
.llvm_target = llvm_target,
|
||||
.target = target,
|
||||
});
|
||||
}
|
||||
} else {
|
||||
var pool: std.Thread.Pool = undefined;
|
||||
try pool.init(.{ .allocator = arena, .n_jobs = llvm_targets.len });
|
||||
try pool.init(.{ .allocator = arena, .n_jobs = targets.len });
|
||||
defer pool.deinit();
|
||||
|
||||
for (llvm_targets) |llvm_target| {
|
||||
if (filter) |zig_name| if (!std.mem.eql(u8, llvm_target.zig_name, zig_name)) continue;
|
||||
for (targets) |target| {
|
||||
if (filter) |zig_name| if (!std.mem.eql(u8, target.zig_name, zig_name)) continue;
|
||||
const job = Job{
|
||||
.llvm_tblgen_exe = llvm_tblgen_exe,
|
||||
.llvm_src_root = llvm_src_root,
|
||||
.zig_src_dir = zig_src_dir,
|
||||
.root_progress = root_progress,
|
||||
.llvm_target = llvm_target,
|
||||
.target = target,
|
||||
};
|
||||
try pool.spawn(processOneTarget, .{job});
|
||||
}
|
||||
|
|
@ -1451,33 +1500,38 @@ const Job = struct {
|
|||
llvm_src_root: []const u8,
|
||||
zig_src_dir: std.fs.Dir,
|
||||
root_progress: std.Progress.Node,
|
||||
llvm_target: LlvmTarget,
|
||||
target: ArchTarget,
|
||||
};
|
||||
|
||||
fn processOneTarget(job: Job) void {
|
||||
errdefer |err| std.debug.panic("panic: {s}", .{@errorName(err)});
|
||||
const llvm_target = job.llvm_target;
|
||||
const target = job.target;
|
||||
|
||||
var arena_state = std.heap.ArenaAllocator.init(std.heap.page_allocator);
|
||||
defer arena_state.deinit();
|
||||
const arena = arena_state.allocator();
|
||||
|
||||
const progress_node = job.root_progress.start(llvm_target.zig_name, 3);
|
||||
const progress_node = job.root_progress.start(target.zig_name, 3);
|
||||
defer progress_node.end();
|
||||
|
||||
var features_table = std.StringHashMap(Feature).init(arena);
|
||||
var all_features = std.ArrayList(Feature).init(arena);
|
||||
var all_cpus = std.ArrayList(Cpu).init(arena);
|
||||
|
||||
if (target.llvm) |llvm| {
|
||||
const tblgen_progress = progress_node.start("running llvm-tblgen", 0);
|
||||
|
||||
const child_args = [_][]const u8{
|
||||
job.llvm_tblgen_exe,
|
||||
"--dump-json",
|
||||
try std.fmt.allocPrint(arena, "{s}/llvm/lib/Target/{s}/{s}", .{
|
||||
try std.fmt.allocPrint(arena, "{s}/llvm/lib/Target/{s}/{s}.td", .{
|
||||
job.llvm_src_root,
|
||||
llvm_target.llvm_name,
|
||||
llvm_target.td_name,
|
||||
llvm.name,
|
||||
llvm.td_name,
|
||||
}),
|
||||
try std.fmt.allocPrint(arena, "-I={s}/llvm/include", .{job.llvm_src_root}),
|
||||
try std.fmt.allocPrint(arena, "-I={s}/llvm/lib/Target/{s}", .{
|
||||
job.llvm_src_root, llvm_target.llvm_name,
|
||||
job.llvm_src_root, llvm.name,
|
||||
}),
|
||||
};
|
||||
|
||||
|
|
@ -1509,7 +1563,7 @@ fn processOneTarget(job: Job) void {
|
|||
const root_map = &parsed.value.object;
|
||||
json_parse_progress.end();
|
||||
|
||||
const render_progress = progress_node.start("rendering Zig code", 0);
|
||||
const collate_progress = progress_node.start("collating LLVM data", 0);
|
||||
|
||||
// So far, LLVM only has a few aliases for the same CPU.
|
||||
var cpu_aliases = std.StringHashMap(std.SegmentedList(struct {
|
||||
|
|
@ -1541,9 +1595,6 @@ fn processOneTarget(job: Job) void {
|
|||
}
|
||||
}
|
||||
|
||||
var features_table = std.StringHashMap(Feature).init(arena);
|
||||
var all_features = std.ArrayList(Feature).init(arena);
|
||||
var all_cpus = std.ArrayList(Cpu).init(arena);
|
||||
{
|
||||
var it = root_map.iterator();
|
||||
while (it.next()) |kv| {
|
||||
|
|
@ -1561,7 +1612,7 @@ fn processOneTarget(job: Job) void {
|
|||
var flatten = false;
|
||||
var omit_deps: []const []const u8 = &.{};
|
||||
var extra_deps: []const []const u8 = &.{};
|
||||
for (llvm_target.feature_overrides) |feature_override| {
|
||||
for (target.feature_overrides) |feature_override| {
|
||||
if (mem.eql(u8, llvm_name, feature_override.llvm_name)) {
|
||||
if (feature_override.omit) {
|
||||
// Still put the feature into the table so that we can
|
||||
|
|
@ -1589,7 +1640,7 @@ fn processOneTarget(job: Job) void {
|
|||
const other_llvm_name = other_obj.get("Name").?.string;
|
||||
const other_zig_name = (try llvmFeatureNameToZigNameOmit(
|
||||
arena,
|
||||
llvm_target,
|
||||
target,
|
||||
other_llvm_name,
|
||||
)) orelse continue;
|
||||
for (omit_deps) |omit_dep| {
|
||||
|
|
@ -1606,7 +1657,7 @@ fn processOneTarget(job: Job) void {
|
|||
const other_llvm_name = other_obj.get("Name").?.string;
|
||||
const other_zig_name = (try llvmFeatureNameToZigNameOmit(
|
||||
arena,
|
||||
llvm_target,
|
||||
target,
|
||||
other_llvm_name,
|
||||
)) orelse continue;
|
||||
for (omit_deps) |omit_dep| {
|
||||
|
|
@ -1634,7 +1685,7 @@ fn processOneTarget(job: Job) void {
|
|||
if (hasSuperclass(&kv.value_ptr.object, "Processor")) {
|
||||
const llvm_name = kv.value_ptr.object.get("Name").?.string;
|
||||
if (llvm_name.len == 0) continue;
|
||||
const omitted = for (llvm_target.omit_cpus) |omit_cpu_name| {
|
||||
const omitted = for (target.omit_cpus) |omit_cpu_name| {
|
||||
if (mem.eql(u8, omit_cpu_name, llvm_name)) break true;
|
||||
} else false;
|
||||
if (omitted) continue;
|
||||
|
|
@ -1643,7 +1694,7 @@ fn processOneTarget(job: Job) void {
|
|||
var deps = std.ArrayList([]const u8).init(arena);
|
||||
var omit_deps: []const []const u8 = &.{};
|
||||
var extra_deps: []const []const u8 = &.{};
|
||||
for (llvm_target.feature_overrides) |feature_override| {
|
||||
for (target.feature_overrides) |feature_override| {
|
||||
if (mem.eql(u8, llvm_name, feature_override.llvm_name)) {
|
||||
if (feature_override.omit) {
|
||||
continue;
|
||||
|
|
@ -1664,7 +1715,7 @@ fn processOneTarget(job: Job) void {
|
|||
if (feature_llvm_name.len == 0) continue;
|
||||
const feature_zig_name = (try llvmFeatureNameToZigNameOmit(
|
||||
arena,
|
||||
llvm_target,
|
||||
target,
|
||||
feature_llvm_name,
|
||||
)) orelse continue;
|
||||
for (omit_deps) |omit_dep| {
|
||||
|
|
@ -1684,7 +1735,7 @@ fn processOneTarget(job: Job) void {
|
|||
if (feature_llvm_name.len == 0) continue;
|
||||
const feature_zig_name = (try llvmFeatureNameToZigNameOmit(
|
||||
arena,
|
||||
llvm_target,
|
||||
target,
|
||||
feature_llvm_name,
|
||||
)) orelse continue;
|
||||
try deps.append(feature_zig_name);
|
||||
|
|
@ -1699,7 +1750,7 @@ fn processOneTarget(job: Job) void {
|
|||
var alias_it = aliases.constIterator(0);
|
||||
|
||||
alias_it: while (alias_it.next()) |alias| {
|
||||
for (llvm_target.omit_cpus) |omit_cpu_name| {
|
||||
for (target.omit_cpus) |omit_cpu_name| {
|
||||
if (mem.eql(u8, omit_cpu_name, alias.llvm)) continue :alias_it;
|
||||
}
|
||||
|
||||
|
|
@ -1713,20 +1764,26 @@ fn processOneTarget(job: Job) void {
|
|||
}
|
||||
}
|
||||
}
|
||||
for (llvm_target.extra_features) |extra_feature| {
|
||||
|
||||
collate_progress.end();
|
||||
}
|
||||
|
||||
for (target.extra_features) |extra_feature| {
|
||||
try features_table.put(extra_feature.zig_name, extra_feature);
|
||||
try all_features.append(extra_feature);
|
||||
}
|
||||
for (llvm_target.extra_cpus) |extra_cpu| {
|
||||
for (target.extra_cpus) |extra_cpu| {
|
||||
try all_cpus.append(extra_cpu);
|
||||
}
|
||||
mem.sort(Feature, all_features.items, {}, featureLessThan);
|
||||
mem.sort(Cpu, all_cpus.items, {}, cpuLessThan);
|
||||
|
||||
const render_progress = progress_node.start("rendering Zig code", 0);
|
||||
|
||||
var target_dir = try job.zig_src_dir.openDir("lib/std/Target", .{});
|
||||
defer target_dir.close();
|
||||
|
||||
const zig_code_basename = try std.fmt.allocPrint(arena, "{s}.zig", .{llvm_target.zig_name});
|
||||
const zig_code_basename = try std.fmt.allocPrint(arena, "{s}.zig", .{target.zig_name});
|
||||
var zig_code_file = try target_dir.createFile(zig_code_basename, .{});
|
||||
defer zig_code_file.close();
|
||||
|
||||
|
|
@ -1760,7 +1817,7 @@ fn processOneTarget(job: Job) void {
|
|||
\\pub const all_features = blk: {
|
||||
\\
|
||||
);
|
||||
if (llvm_target.branch_quota) |branch_quota| {
|
||||
if (target.branch_quota) |branch_quota| {
|
||||
try w.print(" @setEvalBranchQuota({d});\n", .{branch_quota});
|
||||
}
|
||||
try w.writeAll(
|
||||
|
|
@ -1941,10 +1998,10 @@ fn llvmNameToZigName(arena: mem.Allocator, llvm_name: []const u8) ![]const u8 {
|
|||
|
||||
fn llvmFeatureNameToZigNameOmit(
|
||||
arena: mem.Allocator,
|
||||
llvm_target: LlvmTarget,
|
||||
target: ArchTarget,
|
||||
llvm_name: []const u8,
|
||||
) !?[]const u8 {
|
||||
for (llvm_target.feature_overrides) |feature_override| {
|
||||
for (target.feature_overrides) |feature_override| {
|
||||
if (mem.eql(u8, feature_override.llvm_name, llvm_name)) {
|
||||
if (feature_override.omit) return null;
|
||||
return feature_override.zig_name orelse break;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue