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https://codeberg.org/ziglang/zig.git
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riscv: PRO member function calls
this is enough progress for us to be able to call `stdout.write`!
This commit is contained in:
David Rubin
parent
c457f35da5
commit
55b28c7e44
2 changed files with 291 additions and 79 deletions
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@ -932,6 +932,25 @@ fn gen(self: *Self) !void {
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const backpatch_fp_add = try self.addPseudo(.pseudo_dead);
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const backpatch_spill_callee_preserved_regs = try self.addPseudo(.pseudo_dead);
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switch (self.ret_mcv.long) {
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.none, .unreach => {},
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.indirect => {
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// The address where to store the return value for the caller is in a
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// register which the callee is free to clobber. Therefore, we purposely
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// spill it to stack immediately.
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const frame_index = try self.allocFrameIndex(FrameAlloc.initSpill(Type.usize, mod));
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try self.genSetMem(
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.{ .frame = frame_index },
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0,
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Type.usize,
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self.ret_mcv.long.address().offset(-self.ret_mcv.short.indirect.off),
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);
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self.ret_mcv.long = .{ .load_frame = .{ .index = frame_index } };
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tracking_log.debug("spill {} to {}", .{ self.ret_mcv.long, frame_index });
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},
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else => unreachable,
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}
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try self.genBody(self.air.getMainBody());
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for (self.exitlude_jump_relocs.items) |jmp_reloc| {
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@ -1306,12 +1325,13 @@ fn genBody(self: *Self, body: []const Air.Inst.Index) InnerError!void {
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var it = self.register_manager.free_registers.iterator(.{ .kind = .unset });
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while (it.next()) |index| {
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const tracked_inst = self.register_manager.registers[index];
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tracking_log.debug("tracked inst: {}", .{tracked_inst});
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const tracking = self.getResolvedInstValue(tracked_inst);
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for (tracking.getRegs()) |reg| {
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if (RegisterManager.indexOfRegIntoTracked(reg).? == index) break;
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} else return self.fail(
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\\%{} takes up these regs: {any}, however those regs don't use it
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, .{ index, tracking.getRegs() });
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} else return std.debug.panic(
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\\%{} takes up these regs: {any}, however these regs {any}, don't use it
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, .{ tracked_inst, tracking.getRegs(), RegisterManager.regAtTrackedIndex(@intCast(index)) });
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}
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}
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}
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@ -1540,7 +1560,7 @@ fn symbolIndex(self: *Self) !u32 {
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const atom_index = try elf_file.zigObjectPtr().?.getOrCreateMetadataForDecl(elf_file, decl_index);
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break :blk atom_index;
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},
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else => return self.fail("TODO genSetReg load_symbol for {s}", .{@tagName(self.bin_file.tag)}),
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else => return self.fail("TODO symbolIndex {s}", .{@tagName(self.bin_file.tag)}),
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};
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}
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@ -1961,7 +1981,7 @@ fn binOp(
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switch (lhs_ty.zigTypeTag(zcu)) {
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.Float => return self.fail("TODO binary operations on floats", .{}),
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.Vector => return self.fail("TODO binary operations on vectors", .{}),
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.Int, .Enum => {
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.Int, .Enum, .ErrorSet => {
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assert(lhs_ty.eql(rhs_ty, zcu));
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const int_info = lhs_ty.intInfo(zcu);
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if (int_info.bits <= 64) {
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@ -2304,8 +2324,127 @@ fn airAddWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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}
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fn airSubWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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_ = inst;
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return self.fail("TODO implement airSubWithOverflow for {}", .{self.target.cpu.arch});
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const zcu = self.bin_file.comp.module.?;
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const ty_pl = self.air.instructions.items(.data)[@intFromEnum(inst)].ty_pl;
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const extra = self.air.extraData(Air.Bin, ty_pl.payload).data;
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const result: MCValue = if (self.liveness.isUnused(inst)) .unreach else result: {
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const lhs = try self.resolveInst(extra.lhs);
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const rhs = try self.resolveInst(extra.rhs);
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const lhs_ty = self.typeOf(extra.lhs);
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const rhs_ty = self.typeOf(extra.rhs);
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const int_info = lhs_ty.intInfo(zcu);
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if (!math.isPowerOfTwo(int_info.bits) or !(int_info.bits >= 8)) {
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return self.fail("TODO: airSubWithOverflow non-power of 2 and less than 8 bits", .{});
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}
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const tuple_ty = self.typeOfIndex(inst);
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const result_mcv = try self.allocRegOrMem(inst, false);
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const offset = result_mcv.load_frame;
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const lhs_reg, const lhs_lock = blk: {
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if (lhs == .register) break :blk .{ lhs.register, null };
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const lhs_reg, const lhs_lock = try self.allocReg();
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try self.genSetReg(lhs_ty, lhs_reg, lhs);
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break :blk .{ lhs_reg, lhs_lock };
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};
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defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
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const rhs_reg, const rhs_lock = blk: {
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if (rhs == .register) break :blk .{ rhs.register, null };
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const rhs_reg, const rhs_lock = try self.allocReg();
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try self.genSetReg(rhs_ty, rhs_reg, rhs);
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break :blk .{ rhs_reg, rhs_lock };
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};
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defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
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const dest_reg, const dest_lock = try self.allocReg();
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defer self.register_manager.unlockReg(dest_lock);
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switch (int_info.signedness) {
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.unsigned => return self.fail("TODO: airSubWithOverflow unsigned", .{}),
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.signed => {
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switch (int_info.bits) {
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64 => {
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// result
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_ = try self.addInst(.{
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.tag = .sub,
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.ops = .rrr,
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.data = .{ .r_type = .{
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.rd = dest_reg,
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.rs1 = lhs_reg,
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.rs2 = rhs_reg,
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} },
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});
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try self.genSetMem(
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.{ .frame = offset.index },
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offset.off + @as(i32, @intCast(tuple_ty.structFieldOffset(0, zcu))),
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lhs_ty,
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.{ .register = dest_reg },
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);
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// overflow check
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const overflow_reg = try self.copyToTmpRegister(Type.usize, .{ .immediate = 0 });
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_ = try self.addInst(.{
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.tag = .slt,
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.ops = .rrr,
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.data = .{ .r_type = .{
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.rd = overflow_reg,
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.rs1 = overflow_reg,
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.rs2 = rhs_reg,
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} },
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});
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_ = try self.addInst(.{
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.tag = .slt,
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.ops = .rrr,
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.data = .{ .r_type = .{
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.rd = rhs_reg,
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.rs1 = rhs_reg,
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.rs2 = lhs_reg,
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} },
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});
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_ = try self.addInst(.{
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.tag = .xor,
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.ops = .rrr,
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.data = .{ .r_type = .{
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.rd = lhs_reg,
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.rs1 = overflow_reg,
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.rs2 = rhs_reg,
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} },
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});
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const overflow_mcv = try self.binOp(
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.cmp_neq,
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.{ .register = overflow_reg },
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Type.usize,
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.{ .register = rhs_reg },
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Type.usize,
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);
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try self.genSetMem(
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.{ .frame = offset.index },
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offset.off + @as(i32, @intCast(tuple_ty.structFieldOffset(1, zcu))),
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Type.u1,
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overflow_mcv,
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);
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break :result result_mcv;
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},
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else => |int_bits| return self.fail("TODO: airSubWithOverflow signed {}", .{int_bits}),
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}
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},
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}
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};
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return self.finishAir(inst, result, .{ extra.lhs, extra.rhs, .none });
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}
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fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
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@ -2644,8 +2783,25 @@ fn airWrapOptional(self: *Self, inst: Air.Inst.Index) !void {
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/// T to E!T
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fn airWrapErrUnionPayload(self: *Self, inst: Air.Inst.Index) !void {
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const zcu = self.bin_file.comp.module.?;
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const ty_op = self.air.instructions.items(.data)[@intFromEnum(inst)].ty_op;
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const result: MCValue = if (self.liveness.isUnused(inst)) .unreach else return self.fail("TODO implement wrap errunion payload for {}", .{self.target.cpu.arch});
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const eu_ty = ty_op.ty.toType();
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const pl_ty = eu_ty.errorUnionPayload(zcu);
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const err_ty = eu_ty.errorUnionSet(zcu);
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const operand = try self.resolveInst(ty_op.operand);
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const result: MCValue = result: {
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if (!pl_ty.hasRuntimeBitsIgnoreComptime(zcu)) break :result .{ .immediate = 0 };
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const frame_index = try self.allocFrameIndex(FrameAlloc.initSpill(eu_ty, zcu));
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const pl_off: i32 = @intCast(errUnionPayloadOffset(pl_ty, zcu));
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const err_off: i32 = @intCast(errUnionErrorOffset(pl_ty, zcu));
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try self.genSetMem(.{ .frame = frame_index }, pl_off, pl_ty, operand);
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try self.genSetMem(.{ .frame = frame_index }, err_off, err_ty, .{ .immediate = 0 });
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break :result .{ .load_frame = .{ .index = frame_index } };
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};
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return self.finishAir(inst, result, .{ ty_op.operand, .none, .none });
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}
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@ -3361,8 +3517,6 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
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.rs1 = dst_reg,
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} },
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});
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return self.fail("TODO: airStructFieldVal register with field_off > 0", .{});
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}
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break :result if (field_off == 0) dst_mcv else try self.copyToNewRegister(inst, dst_mcv);
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@ -3444,7 +3598,6 @@ fn genArgDbgInfo(self: Self, inst: Air.Inst.Index, mcv: MCValue) !void {
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}
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fn airArg(self: *Self, inst: Air.Inst.Index) !void {
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const zcu = self.bin_file.comp.module.?;
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var arg_index = self.arg_index;
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// we skip over args that have no bits
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@ -3453,31 +3606,10 @@ fn airArg(self: *Self, inst: Air.Inst.Index) !void {
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const result: MCValue = if (self.liveness.isUnused(inst)) .unreach else result: {
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const src_mcv = self.args[arg_index];
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const arg_ty = self.typeOfIndex(inst);
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const dst_mcv = switch (src_mcv) {
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.register => dst: {
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const frame = try self.allocFrameIndex(FrameAlloc.init(.{
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.size = Type.usize.abiSize(zcu),
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.alignment = Type.usize.abiAlignment(zcu),
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}));
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const dst_mcv: MCValue = .{ .load_frame = .{ .index = frame } };
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try self.genCopy(Type.usize, dst_mcv, src_mcv);
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break :dst dst_mcv;
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},
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.register_pair => dst: {
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const frame = try self.allocFrameIndex(FrameAlloc.init(.{
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.size = Type.usize.abiSize(zcu) * 2,
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.alignment = Type.usize.abiAlignment(zcu),
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}));
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const dst_mcv: MCValue = .{ .load_frame = .{ .index = frame } };
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const dst_mcv = try self.allocRegOrMem(inst, false);
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try self.genCopy(arg_ty, dst_mcv, src_mcv);
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break :dst dst_mcv;
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},
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.load_frame => src_mcv,
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else => return self.fail("TODO: airArg {s}", .{@tagName(src_mcv)}),
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};
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try self.genArgDbgInfo(inst, src_mcv);
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break :result dst_mcv;
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@ -3612,7 +3744,68 @@ fn genCall(
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stack_frame_align.* = stack_frame_align.max(needed_call_frame.abi_align);
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}
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for (call_info.args, 0..) |mc_arg, arg_i| try self.genCopy(arg_tys[arg_i], mc_arg, args[arg_i]);
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var reg_locks = std.ArrayList(?RegisterLock).init(allocator);
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defer reg_locks.deinit();
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try reg_locks.ensureTotalCapacity(8);
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defer for (reg_locks.items) |reg_lock| if (reg_lock) |lock| self.register_manager.unlockReg(lock);
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const frame_indices = try allocator.alloc(FrameIndex, args.len);
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defer allocator.free(frame_indices);
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switch (call_info.return_value.long) {
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.none, .unreach => {},
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.indirect => |reg_off| try self.register_manager.getReg(reg_off.reg, null),
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else => unreachable,
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}
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for (call_info.args, args, arg_tys, frame_indices) |dst_arg, src_arg, arg_ty, *frame_index| {
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switch (dst_arg) {
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.none => {},
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.register => |reg| {
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try self.register_manager.getReg(reg, null);
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try reg_locks.append(self.register_manager.lockReg(reg));
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},
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.register_pair => |regs| {
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for (regs) |reg| try self.register_manager.getReg(reg, null);
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try reg_locks.appendSlice(&self.register_manager.lockRegs(2, regs));
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},
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.indirect => |reg_off| {
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frame_index.* = try self.allocFrameIndex(FrameAlloc.initType(arg_ty, zcu));
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try self.genSetMem(.{ .frame = frame_index.* }, 0, arg_ty, src_arg);
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try self.register_manager.getReg(reg_off.reg, null);
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try reg_locks.append(self.register_manager.lockReg(reg_off.reg));
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},
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else => return self.fail("TODO: genCall set arg {s}", .{@tagName(dst_arg)}),
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}
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}
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switch (call_info.return_value.long) {
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.none, .unreach => {},
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.indirect => |reg_off| {
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const ret_ty = Type.fromInterned(fn_info.return_type);
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const frame_index = try self.allocFrameIndex(FrameAlloc.initSpill(ret_ty, zcu));
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try self.genSetReg(Type.usize, reg_off.reg, .{
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.lea_frame = .{ .index = frame_index, .off = -reg_off.off },
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});
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call_info.return_value.short = .{ .load_frame = .{ .index = frame_index } };
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try reg_locks.append(self.register_manager.lockReg(reg_off.reg));
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},
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else => unreachable,
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}
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for (call_info.args, arg_tys, args, frame_indices) |dst_arg, arg_ty, src_arg, frame_index| {
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switch (dst_arg) {
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.register_pair => try self.genCopy(arg_ty, dst_arg, src_arg),
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.register => |dst_reg| try self.genSetReg(
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arg_ty,
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dst_reg,
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src_arg,
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),
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.indirect => |reg_off| try self.genSetReg(Type.usize, reg_off.reg, .{
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.lea_frame = .{ .index = frame_index, .off = -reg_off.off },
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}),
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else => return self.fail("TODO: genCall actual set {s}", .{@tagName(dst_arg)}),
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}
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}
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// Due to incremental compilation, how function calls are generated depends
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// on linking.
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@ -3715,9 +3908,10 @@ fn airRet(self: *Self, inst: Air.Inst.Index, safety: bool) !void {
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defer self.register_manager.unlockReg(lock);
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try self.genSetReg(Type.usize, reg_off.reg, self.ret_mcv.long);
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try self.genCopy(
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try self.genSetMem(
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.{ .reg = reg_off.reg },
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reg_off.off,
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ret_ty,
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.{ .register_offset = reg_off },
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.{ .air_ref = un_op },
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);
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},
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@ -3745,6 +3939,7 @@ fn airRetLoad(self: *Self, inst: Air.Inst.Index) !void {
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switch (self.ret_mcv.short) {
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.none => {},
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.register, .register_pair => try self.load(self.ret_mcv.short, ptr, ptr_ty),
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.indirect => |reg_off| try self.genSetReg(ptr_ty, reg_off.reg, ptr),
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else => unreachable,
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}
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self.ret_mcv.liveOut(self, inst);
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@ -4058,7 +4253,7 @@ fn isErr(self: *Self, maybe_inst: ?Air.Inst.Index, eu_ty: Type, eu_mcv: MCValue)
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_ = maybe_inst;
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const err_off = errUnionErrorOffset(eu_ty.errorUnionPayload(zcu), zcu);
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const err_off: u31 = @intCast(errUnionErrorOffset(eu_ty.errorUnionPayload(zcu), zcu));
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switch (eu_mcv) {
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.register => |reg| {
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@ -4081,15 +4276,25 @@ fn isErr(self: *Self, maybe_inst: ?Air.Inst.Index, eu_ty: Type, eu_mcv: MCValue)
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);
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}
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return_mcv = try self.binOp(
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return try self.binOp(
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.cmp_neq,
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return_mcv,
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Type.u16,
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.{ .immediate = 0 },
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Type.u16,
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);
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return return_mcv;
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},
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.load_frame => |frame_addr| {
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return self.binOp(
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.cmp_neq,
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.{ .load_frame = .{
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.index = frame_addr.index,
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.off = frame_addr.off + err_off,
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} },
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Type.anyerror,
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.{ .immediate = 0 },
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Type.anyerror,
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);
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},
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else => return self.fail("TODO implement isErr for {}", .{eu_mcv}),
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}
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@ -4839,7 +5044,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, src_mcv: MCValue) InnerError!
|
|||
const zcu = self.bin_file.comp.module.?;
|
||||
const abi_size: u32 = @intCast(ty.abiSize(zcu));
|
||||
|
||||
if (abi_size > 8) return self.fail("tried to set reg with size {}", .{abi_size});
|
||||
if (abi_size > 8) return std.debug.panic("tried to set reg with size {}", .{abi_size});
|
||||
|
||||
switch (src_mcv) {
|
||||
.dead => unreachable,
|
||||
|
|
@ -4924,7 +5129,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, src_mcv: MCValue) InnerError!
|
|||
if (src_reg.id() == reg.id())
|
||||
return;
|
||||
|
||||
// mov reg, src_reg
|
||||
// mv reg, src_reg
|
||||
_ = try self.addInst(.{
|
||||
.tag = .pseudo,
|
||||
.ops = .pseudo_mv,
|
||||
|
|
@ -4934,20 +5139,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, src_mcv: MCValue) InnerError!
|
|||
} },
|
||||
});
|
||||
},
|
||||
.register_pair => |pair| try self.genSetReg(ty, reg, .{ .register = pair[0] }),
|
||||
.memory => |addr| {
|
||||
try self.genSetReg(ty, reg, .{ .immediate = addr });
|
||||
|
||||
_ = try self.addInst(.{
|
||||
.tag = .ld,
|
||||
.ops = .rri,
|
||||
.data = .{ .i_type = .{
|
||||
.rd = reg,
|
||||
.rs1 = reg,
|
||||
.imm12 = Immediate.s(0),
|
||||
} },
|
||||
});
|
||||
},
|
||||
.register_pair => return self.fail("genSetReg should we allow reg -> reg_pair?", .{}),
|
||||
.load_frame => |frame| {
|
||||
_ = try self.addInst(.{
|
||||
.tag = .pseudo,
|
||||
|
|
@ -4966,13 +5158,36 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, src_mcv: MCValue) InnerError!
|
|||
} },
|
||||
});
|
||||
},
|
||||
.lea_frame => |frame| {
|
||||
.memory => |addr| {
|
||||
try self.genSetReg(ty, reg, .{ .immediate = addr });
|
||||
|
||||
_ = try self.addInst(.{
|
||||
.tag = .ld,
|
||||
.ops = .rri,
|
||||
.data = .{ .i_type = .{
|
||||
.rd = reg,
|
||||
.rs1 = reg,
|
||||
.imm12 = Immediate.s(0),
|
||||
} },
|
||||
});
|
||||
},
|
||||
.lea_frame, .register_offset => {
|
||||
_ = try self.addInst(.{
|
||||
.tag = .pseudo,
|
||||
.ops = .pseudo_lea_rm,
|
||||
.data = .{ .rm = .{
|
||||
.r = reg,
|
||||
.m = .{
|
||||
.m = switch (src_mcv) {
|
||||
.register_offset => |reg_off| .{
|
||||
.base = .{ .reg = reg_off.reg },
|
||||
.mod = .{
|
||||
.rm = .{
|
||||
.size = self.memSize(ty),
|
||||
.disp = reg_off.off,
|
||||
},
|
||||
},
|
||||
},
|
||||
.lea_frame => |frame| .{
|
||||
.base = .{ .frame = frame.index },
|
||||
.mod = .{
|
||||
.rm = .{
|
||||
|
|
@ -4981,13 +5196,11 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, src_mcv: MCValue) InnerError!
|
|||
},
|
||||
},
|
||||
},
|
||||
else => unreachable,
|
||||
},
|
||||
} },
|
||||
});
|
||||
},
|
||||
.load_symbol => {
|
||||
try self.genSetReg(ty, reg, src_mcv.address());
|
||||
try self.genSetReg(ty, reg, .{ .indirect = .{ .reg = reg } });
|
||||
},
|
||||
.indirect => |reg_off| {
|
||||
const load_tag: Mir.Inst.Tag = switch (abi_size) {
|
||||
1 => .lb,
|
||||
|
|
@ -5022,6 +5235,10 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, src_mcv: MCValue) InnerError!
|
|||
}) },
|
||||
});
|
||||
},
|
||||
.load_symbol => {
|
||||
try self.genSetReg(ty, reg, src_mcv.address());
|
||||
try self.genSetReg(ty, reg, .{ .indirect = .{ .reg = reg } });
|
||||
},
|
||||
.air_ref => |ref| try self.genSetReg(ty, reg, try self.resolveInst(ref)),
|
||||
else => return self.fail("TODO: genSetReg {s}", .{@tagName(src_mcv)}),
|
||||
}
|
||||
|
|
@ -5052,7 +5269,6 @@ fn genSetMem(
|
|||
src_mcv,
|
||||
.{ .immediate = abi_size },
|
||||
),
|
||||
|
||||
.register_offset,
|
||||
.memory,
|
||||
.indirect,
|
||||
|
|
@ -5100,14 +5316,15 @@ fn genSetMem(
|
|||
_ = try self.addInst(.{
|
||||
.tag = .pseudo,
|
||||
.ops = .pseudo_store_rm,
|
||||
.data = .{
|
||||
.rm = .{ .r = reg, .m = .{
|
||||
.data = .{ .rm = .{
|
||||
.r = reg,
|
||||
.m = .{
|
||||
.base = .{ .frame = frame_index },
|
||||
.mod = .{ .rm = .{
|
||||
.size = Memory.Size.fromByteSize(src_size),
|
||||
} },
|
||||
} },
|
||||
},
|
||||
} },
|
||||
});
|
||||
try self.genSetMem(base, disp, ty, frame_mcv);
|
||||
try self.freeValue(frame_mcv);
|
||||
|
|
|
|||
|
|
@ -149,12 +149,7 @@ pub fn classifySystem(ty: Type, zcu: *Module) [8]Class {
|
|||
// anyerror!void can fit into one register
|
||||
if (payload_bits == 0) return result;
|
||||
|
||||
if (payload_bits <= 64) {
|
||||
result[1] = .integer;
|
||||
return result;
|
||||
}
|
||||
|
||||
std.debug.panic("TODO: classifySystem ErrorUnion > 64 bit payload", .{});
|
||||
return memory_class;
|
||||
},
|
||||
.Struct => {
|
||||
const layout = ty.containerLayout(zcu);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue