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skip regressed LLVM 17 std lib test on powerpc

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Tracked by #16951
This commit is contained in:
Andrew Kelley 2023-08-24 14:38:58 -07:00
parent 66312c0b51
commit 5b8af7a2a9
1 changed files with 5 additions and 0 deletions
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5
lib/std/mem.zig
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@ -4490,6 +4490,11 @@ test "read/write(Var)PackedInt" {
else => {},
}
if (builtin.cpu.arch == .powerpc) {
// https://github.com/ziglang/zig/issues/16951
return error.SkipZigTest;
}
const foreign_endian: Endian = if (native_endian == .Big) .Little else .Big;
const expect = std.testing.expect;
var prng = std.rand.DefaultPrng.init(1234);