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test: Add riscv(32,64)-linux-(none,musl) with soft float to module tests.

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Alex Rønne Petersen 2024-10-06 11:12:54 +02:00
parent 0941364d70
commit 6302a90cbf
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1 changed files with 29 additions and 1 deletions
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30
test/tests.zig
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@ -579,6 +579,20 @@ const test_targets = blk: {
.link_libc = true, .link_libc = true,
}, },
.{
.target = std.Target.Query.parse(.{
.arch_os_abi = "riscv32-linux-none",
.cpu_features = "baseline-d-f",
}) catch unreachable,
},
.{
.target = std.Target.Query.parse(.{
.arch_os_abi = "riscv32-linux-musl",
.cpu_features = "baseline-d-f",
}) catch unreachable,
.link_libc = true,
},
.{ .{
.target = .{ .target = .{
.cpu_arch = .riscv32, .cpu_arch = .riscv32,
@ -603,6 +617,20 @@ const test_targets = blk: {
.link_libc = true, .link_libc = true,
}, },
.{
.target = std.Target.Query.parse(.{
.arch_os_abi = "riscv64-linux-none",
.cpu_features = "baseline-d-f",
}) catch unreachable,
},
.{
.target = std.Target.Query.parse(.{
.arch_os_abi = "riscv64-linux-musl",
.cpu_features = "baseline-d-f",
}) catch unreachable,
.link_libc = true,
},
.{ .{
.target = .{ .target = .{
.cpu_arch = .riscv64, .cpu_arch = .riscv64,
@ -631,7 +659,7 @@ const test_targets = blk: {
.target = std.Target.Query.parse(.{ .target = std.Target.Query.parse(.{
.arch_os_abi = "riscv64-linux-musl", .arch_os_abi = "riscv64-linux-musl",
.cpu_features = "baseline+v+zbb", .cpu_features = "baseline+v+zbb",
}) catch @panic("OOM"), }) catch unreachable,
.use_llvm = false, .use_llvm = false,
.use_lld = false, .use_lld = false,
}, },