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https://codeberg.org/ziglang/zig.git
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- add default register rule
- fixup eh pointer decoding
This commit is contained in:
kcbanner
parent
a0a40c2e7e
commit
69399fbb82
3 changed files with 95 additions and 53 deletions
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@ -1494,18 +1494,34 @@ pub const DwarfInfo = struct {
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}
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const id_len = @as(u8, if (is_64) 8 else 4);
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const entry_bytes = eh_frame[stream.pos..][0..length - id_len];
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const entry_bytes = eh_frame[stream.pos..][0 .. length - id_len];
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const id = try reader.readInt(u32, di.endian);
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// TODO: Get section_offset here (pass in from headers)
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if (id == 0) {
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const cie = try CommonInformationEntry.parse(entry_bytes, @ptrToInt(eh_frame.ptr), 0, length_offset, @sizeOf(usize), di.endian);
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const cie = try CommonInformationEntry.parse(
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entry_bytes,
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@ptrToInt(eh_frame.ptr),
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0,
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true,
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length_offset,
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@sizeOf(usize),
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di.endian,
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);
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try di.cie_map.put(allocator, length_offset, cie);
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} else {
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const cie_offset = stream.pos - 4 - id;
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const cie = di.cie_map.get(cie_offset) orelse return badDwarf();
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const fde = try FrameDescriptionEntry.parse(entry_bytes, @ptrToInt(eh_frame.ptr), 0, cie, @sizeOf(usize), di.endian);
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const fde = try FrameDescriptionEntry.parse(
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entry_bytes,
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@ptrToInt(eh_frame.ptr),
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0,
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true,
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cie,
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@sizeOf(usize),
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di.endian,
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);
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try di.fde_list.append(allocator, fde);
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}
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}
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@ -1557,6 +1573,11 @@ const EhPointerContext = struct {
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// The address of the pointer field itself
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pc_rel_base: u64,
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// Whether or not to follow indirect pointers. This should only be
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// used when decoding pointers at runtime using the current process's
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// debug info.
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follow_indirect: bool,
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// These relative addressing modes are only used in specific cases, and
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// might not be available / required in all parsing contexts
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data_rel_base: ?u64 = null,
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@ -1570,7 +1591,7 @@ fn readEhPointer(reader: anytype, enc: u8, addr_size_bytes: u8, ctx: EhPointerCo
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const value: union(enum) {
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signed: i64,
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unsigned: u64,
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} = switch (enc & 0x0f) {
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} = switch (enc & EH.PE.type_mask) {
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EH.PE.absptr => .{
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.unsigned = switch (addr_size_bytes) {
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2 => try reader.readInt(u16, endian),
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@ -1590,33 +1611,31 @@ fn readEhPointer(reader: anytype, enc: u8, addr_size_bytes: u8, ctx: EhPointerCo
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else => return badDwarf(),
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};
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const relative_to = enc & 0xf0;
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var base = switch (relative_to) {
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var base = switch (enc & EH.PE.rel_mask) {
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EH.PE.pcrel => ctx.pc_rel_base,
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EH.PE.textrel => ctx.text_rel_base orelse return error.PointerBaseNotSpecified,
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EH.PE.datarel => ctx.data_rel_base orelse return error.PointerBaseNotSpecified,
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EH.PE.funcrel => ctx.function_rel_base orelse return error.PointerBaseNotSpecified,
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EH.PE.indirect => {
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switch (addr_size_bytes) {
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2 => return @intToPtr(*const u16, value.unsigned).*,
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4 => return @intToPtr(*const u32, value.unsigned).*,
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8 => return @intToPtr(*const u64, value.unsigned).*,
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else => return error.UnsupportedAddrSize,
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}
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},
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else => null,
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};
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if (base) |b| {
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return switch (value) {
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const ptr = if (base) |b| switch (value) {
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.signed => |s| @intCast(u64, s + @intCast(i64, b)),
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.unsigned => |u| u + b,
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};
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} else {
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return switch (value) {
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} else switch (value) {
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.signed => |s| @intCast(u64, s),
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.unsigned => |u| u,
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};
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if ((enc & EH.PE.indirect) > 0 and ctx.follow_indirect) {
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return switch (addr_size_bytes) {
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2 => return @intToPtr(*const u16, ptr).*,
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4 => return @intToPtr(*const u32, ptr).*,
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8 => return @intToPtr(*const u64, ptr).*,
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else => return error.UnsupportedAddrSize,
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};
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} else {
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return ptr;
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}
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}
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@ -1668,6 +1687,7 @@ pub const CommonInformationEntry = struct {
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cie_bytes: []const u8,
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section_base: u64,
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section_offset: u64,
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is_runtime: bool,
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length_offset: u64,
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addr_size_bytes: u8,
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endian: std.builtin.Endian,
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@ -1735,7 +1755,10 @@ pub const CommonInformationEntry = struct {
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reader,
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personality_enc.?,
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addr_size_bytes,
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.{ .pc_rel_base = @ptrToInt(&cie_bytes[stream.pos]) - section_base + section_offset },
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.{
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.pc_rel_base = @ptrToInt(&cie_bytes[stream.pos]) - section_base + section_offset,
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.follow_indirect = is_runtime,
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},
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endian,
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);
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},
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@ -1785,6 +1808,7 @@ pub const FrameDescriptionEntry = struct {
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fde_bytes: []const u8,
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section_base: u64,
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section_offset: u64,
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is_runtime: bool,
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cie: CommonInformationEntry,
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addr_size_bytes: u8,
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endian: std.builtin.Endian,
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@ -1798,15 +1822,21 @@ pub const FrameDescriptionEntry = struct {
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reader,
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cie.fde_pointer_enc,
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addr_size_bytes,
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.{ .pc_rel_base = @ptrToInt(&fde_bytes[stream.pos]) - section_base + section_offset },
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.{
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.pc_rel_base = @ptrToInt(&fde_bytes[stream.pos]) - section_base + section_offset,
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.follow_indirect = is_runtime,
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},
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endian,
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) orelse return badDwarf();
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const pc_range = try readEhPointer(
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reader,
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cie.fde_pointer_enc & 0x0f,
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cie.fde_pointer_enc,
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addr_size_bytes,
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.{ .pc_rel_base = @ptrToInt(&fde_bytes[stream.pos]) - section_base + section_offset },
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.{
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.pc_rel_base = 0,
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.follow_indirect = false,
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},
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endian,
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) orelse return badDwarf();
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@ -1819,9 +1849,12 @@ pub const FrameDescriptionEntry = struct {
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const lsda_pointer = if (cie.lsda_pointer_enc != EH.PE.omit)
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try readEhPointer(
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reader,
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cie.lsda_pointer_enc & 0x0f,
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cie.lsda_pointer_enc,
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addr_size_bytes,
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.{ .pc_rel_base = @ptrToInt(&fde_bytes[stream.pos]) },
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.{
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.pc_rel_base = @ptrToInt(&fde_bytes[stream.pos]) - section_base + section_offset,
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.follow_indirect = is_runtime,
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},
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endian,
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)
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else
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@ -1,6 +1,10 @@
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pub const PE = struct {
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pub const absptr = 0x00;
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pub const size_mask = 0x7;
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pub const sign_mask = 0x8;
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pub const type_mask = size_mask | sign_mask;
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pub const uleb128 = 0x01;
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pub const udata2 = 0x02;
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pub const udata4 = 0x03;
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@ -10,11 +14,13 @@ pub const PE = struct {
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pub const sdata4 = 0x0B;
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pub const sdata8 = 0x0C;
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pub const rel_mask = 0x70;
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pub const pcrel = 0x10;
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pub const textrel = 0x20;
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pub const datarel = 0x30;
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pub const funcrel = 0x40;
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pub const aligned = 0x50;
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pub const indirect = 0x80;
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pub const omit = 0xff;
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@ -216,16 +216,35 @@ pub const Instruction = union(Opcode) {
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}
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};
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/// See section 6.4.1 of the DWARF5 specification
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/// This is a virtual machine that runs DWARF call frame instructions.
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/// See section 6.4.1 of the DWARF5 specification.
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pub const VirtualMachine = struct {
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const RegisterRule = union(enum) {
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// The spec says that the default rule for each column is the undefined rule.
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// However, it also allows ABI / compiler authors to specify alternate defaults, so
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// there is a distinction made here.
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default: void,
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undefined: void,
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same_value: void,
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// offset(N)
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offset: i64,
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// val_offset(N)
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val_offset: i64,
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// register(R)
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register: u8,
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// expression(E)
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expression: []const u8,
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// val_expression(E)
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val_expression: []const u8,
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// Augmenter-defined rule
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architectural: void,
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};
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@ -248,7 +267,7 @@ pub const VirtualMachine = struct {
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pub const Column = struct {
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/// Register can only null in the case of the CFA column
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register: ?u8 = null,
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rule: RegisterRule = .{ .undefined = {} },
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rule: RegisterRule = .{ .default = {} },
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};
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const ColumnRange = struct {
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@ -264,13 +283,6 @@ pub const VirtualMachine = struct {
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/// The result of executing the CIE's initial_instructions
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cie_row: ?Row = null,
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pub fn reset(self: *VirtualMachine) void {
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self.stack.clearRetainingCapacity();
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self.columns.clearRetainingCapacity();
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self.current_row = .{};
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self.cie_row = null;
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}
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pub fn deinit(self: *VirtualMachine, allocator: std.mem.Allocator) void {
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self.stack.deinit(allocator);
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self.columns.deinit(allocator);
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@ -357,7 +369,7 @@ pub const VirtualMachine = struct {
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/// Executes a single instruction.
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/// If this instruction is from the CIE, `is_initial` should be set.
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/// Returns the value of `current_row` before executing this instruction
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/// Returns the value of `current_row` before executing this instruction.
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pub fn step(
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self: *VirtualMachine,
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allocator: std.mem.Allocator,
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@ -367,13 +379,16 @@ pub const VirtualMachine = struct {
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) !Row {
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// CIE instructions must be run before FDE instructions
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assert(!is_initial or self.cie_row == null);
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if (!is_initial and self.cie_row == null) self.cie_row = self.current_row;
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if (!is_initial and self.cie_row == null) {
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self.cie_row = self.current_row;
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self.current_row.copy_on_write = true;
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}
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const prev_row = self.current_row;
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switch (instruction) {
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.set_loc => |i| {
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if (i.operands.address <= self.current_row.offset) return error.InvalidOperation;
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// TODO: Check cie.segment_selector_size != for DWARFV4
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// TODO: Check cie.segment_selector_size != 0 for DWARFV4
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self.current_row.offset = i.operands.address;
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},
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inline .advance_loc,
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@ -392,11 +407,6 @@ pub const VirtualMachine = struct {
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const column = try self.getOrAddColumn(allocator, i.operands.register);
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column.rule = .{ .offset = @intCast(i64, i.operands.offset) * cie.data_alignment_factor };
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},
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// .offset_extended_sf => |i| {
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// try self.resolveCopyOnWrite(allocator);
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// const column = try self.getOrAddColumn(allocator, i.operands.register);
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// column.rule = .{ .offset = i.operands.offset * cie.data_alignment_factor };
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// },
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inline .restore,
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.restore_extended,
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=> |i| {
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@ -405,7 +415,7 @@ pub const VirtualMachine = struct {
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const column = try self.getOrAddColumn(allocator, i.operands.register);
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column.rule = for (self.rowColumns(cie_row)) |cie_column| {
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if (cie_column.register == i.operands.register) break cie_column.rule;
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} else .{ .undefined = {} };
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} else .{ .default = {} };
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} else return error.InvalidOperation;
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},
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.nop => {},
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@ -427,13 +437,6 @@ pub const VirtualMachine = struct {
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.remember_state => {
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try self.stack.append(allocator, self.current_row.columns);
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self.current_row.copy_on_write = true;
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// const new_start = self.columns.items.len;
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// if (self.current_row.columns.len > 0) {
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// try self.columns.ensureUnusedCapacity(allocator, self.current_row.columns.len);
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// self.columns.appendSliceAssumeCapacity(self.rowColumns(self.current_row));
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// self.current_row.columns.start = new_start;
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// }
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},
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.restore_state => {
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const restored_columns = self.stack.popOrNull() orelse return error.InvalidOperation;
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