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https://codeberg.org/ziglang/zig.git
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llvm: fix data layout calculation for experimental llvm targets
Closes #16616
This commit is contained in:
Jacob Young
Andrew Kelley
parent
4f6013bf50
commit
9e0a34f329
8 changed files with 133 additions and 229 deletions
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@ -435,7 +435,13 @@ pub fn build(b: *std.Build) !void {
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}).step);
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const test_cases_step = b.step("test-cases", "Run the main compiler test cases");
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try tests.addCases(b, test_cases_step, test_filter, check_case_exe);
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try tests.addCases(b, test_cases_step, test_filter, check_case_exe, .{
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.enable_llvm = enable_llvm,
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.llvm_has_m68k = llvm_has_m68k,
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.llvm_has_csky = llvm_has_csky,
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.llvm_has_arc = llvm_has_arc,
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.llvm_has_xtensa = llvm_has_xtensa,
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});
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test_step.dependOn(test_cases_step);
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test_step.dependOn(tests.addModuleTests(b, .{
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@ -1154,9 +1154,9 @@ pub const Target = struct {
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.dxil,
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.loongarch32,
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.loongarch64,
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.arc,
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=> .Little,
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.arc,
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.armeb,
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.aarch64_be,
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.bpfeb,
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@ -1911,6 +1911,7 @@ pub const Target = struct {
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pub fn stackAlignment(target: Target) u16 {
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return switch (target.cpu.arch) {
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.m68k => 2,
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.amdgcn => 4,
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.x86 => switch (target.os.tag) {
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.windows, .uefi => 4,
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@ -374,6 +374,8 @@ const DataLayoutBuilder = struct {
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},
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})}),
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}
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const stack_abi = self.target.stackAlignment() * 8;
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if (self.target.cpu.arch == .csky) try writer.print("-S{d}", .{stack_abi});
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var any_non_integral = false;
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const ptr_bit_width = self.target.ptrBitWidth();
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var default_info = struct { size: u16, abi: u16, pref: u16, idx: u16 }{
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@ -420,14 +422,19 @@ const DataLayoutBuilder = struct {
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if (self.target.cpu.arch.isArmOrThumb())
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try writer.writeAll("-Fi8"); // for thumb interwork
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if (self.target.cpu.arch != .hexagon) {
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if (self.target.cpu.arch == .s390x) try self.typeAlignment(.integer, 1, 8, 8, false, writer);
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if (self.target.cpu.arch == .arc or self.target.cpu.arch == .s390x)
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try self.typeAlignment(.integer, 1, 8, 8, false, writer);
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try self.typeAlignment(.integer, 8, 8, 8, false, writer);
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try self.typeAlignment(.integer, 16, 16, 16, false, writer);
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try self.typeAlignment(.integer, 32, 32, 32, false, writer);
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if (self.target.cpu.arch == .arc)
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try self.typeAlignment(.float, 32, 32, 32, false, writer);
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try self.typeAlignment(.integer, 64, 32, 64, false, writer);
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try self.typeAlignment(.integer, 128, 32, 64, false, writer);
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if (backendSupportsF16(self.target)) try self.typeAlignment(.float, 16, 16, 16, false, writer);
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try self.typeAlignment(.float, 32, 32, 32, false, writer);
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if (backendSupportsF16(self.target))
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try self.typeAlignment(.float, 16, 16, 16, false, writer);
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if (self.target.cpu.arch != .arc)
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try self.typeAlignment(.float, 32, 32, 32, false, writer);
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try self.typeAlignment(.float, 64, 64, 64, false, writer);
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if (self.target.cpu.arch.isX86()) try self.typeAlignment(.float, 80, 0, 0, false, writer);
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try self.typeAlignment(.float, 128, 128, 128, false, writer);
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@ -458,15 +465,18 @@ const DataLayoutBuilder = struct {
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.uefi, .windows => true,
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else => false,
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},
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.avr => true,
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.avr, .m68k => true,
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else => false,
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};
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if (!swap_agg_nat) try self.typeAlignment(.aggregate, 0, 0, 64, false, writer);
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if (self.target.cpu.arch == .csky) try writer.writeAll("-Fi32");
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for (@as([]const u24, switch (self.target.cpu.arch) {
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.avr => &.{8},
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.msp430 => &.{ 8, 16 },
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.arc,
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.arm,
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.armeb,
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.csky,
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.mips,
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.mipsel,
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.powerpc,
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@ -476,6 +486,7 @@ const DataLayoutBuilder = struct {
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.sparcel,
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.thumb,
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.thumbeb,
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.xtensa,
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=> &.{32},
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.aarch64,
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.aarch64_be,
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@ -495,7 +506,9 @@ const DataLayoutBuilder = struct {
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.wasm64,
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=> &.{ 32, 64 },
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.hexagon => &.{ 16, 32 },
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.x86 => &.{ 8, 16, 32 },
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.m68k,
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.x86,
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=> &.{ 8, 16, 32 },
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.nvptx,
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.nvptx64,
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=> &.{ 16, 32, 64 },
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@ -514,9 +527,8 @@ const DataLayoutBuilder = struct {
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try self.typeAlignment(.float, 32, 32, 32, true, writer);
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try self.typeAlignment(.float, 64, 64, 64, true, writer);
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}
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const stack_abi = self.target.stackAlignment() * 8;
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if (self.target.os.tag == .uefi or self.target.os.tag == .windows or
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self.target.cpu.arch == .msp430 or stack_abi != ptr_bit_width)
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if (stack_abi != ptr_bit_width or self.target.cpu.arch == .msp430 or
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self.target.os.tag == .uefi or self.target.os.tag == .windows)
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try writer.print("-S{d}", .{stack_abi});
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switch (self.target.cpu.arch) {
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.hexagon, .ve => {
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@ -592,6 +604,12 @@ const DataLayoutBuilder = struct {
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},
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else => pref = @max(pref, 32),
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},
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.arc => if (size <= 64) {
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abi = @min((std.math.divCeil(u24, size, 8) catch unreachable) * 8, 32);
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pref = 32;
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force_abi = true;
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force_pref = size <= 32;
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},
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.bpfeb,
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.bpfel,
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.nvptx,
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@ -601,22 +619,37 @@ const DataLayoutBuilder = struct {
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abi = size;
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pref = size;
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},
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.csky => if (size == 32 or size == 64) {
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abi = 32;
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pref = 32;
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force_abi = true;
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force_pref = true;
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},
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.hexagon => force_abi = true,
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.m68k => if (size <= 32) {
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abi = @min(size, 16);
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pref = size;
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force_abi = true;
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force_pref = true;
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} else if (size == 64) {
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abi = 32;
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pref = size;
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},
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.mips,
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.mipsel,
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=> pref = @max(pref, 32),
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.mips64,
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.mips64el,
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=> if (size <= 32) {
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pref = 32;
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},
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.s390x => if (size <= 16) {
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pref = 16;
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},
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=> pref = @max(pref, 32),
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.s390x => pref = @max(pref, 16),
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.ve => if (size == 64) {
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abi = size;
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pref = size;
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},
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.xtensa => if (size <= 64) {
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pref = @max(size, 32);
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abi = size;
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force_abi = size == 64;
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},
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else => {},
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}
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},
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@ -634,6 +667,10 @@ const DataLayoutBuilder = struct {
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pref = size;
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} else if (self.target.cpu.arch == .amdgcn and size <= 2048) {
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force_abi = true;
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} else if (self.target.cpu.arch == .csky and (size == 64 or size == 128)) {
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abi = 32;
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pref = 32;
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force_pref = true;
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} else if (self.target.cpu.arch == .hexagon and
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((size >= 32 and size <= 64) or (size >= 512 and size <= 2048)))
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{
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@ -651,11 +688,27 @@ const DataLayoutBuilder = struct {
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force_pref = true;
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},
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.float => switch (self.target.cpu.arch) {
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.aarch64_32, .amdgcn => if (size == 128) {
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abi = size;
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pref = size;
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},
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.arc => if (size == 32 or size == 64) {
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abi = 32;
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pref = 32;
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force_abi = true;
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force_pref = size == 32;
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},
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.avr, .msp430, .sparc64 => if (size != 32 and size != 64) return,
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.csky => if (size == 32 or size == 64) {
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abi = 32;
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pref = 32;
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force_abi = true;
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force_pref = true;
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},
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.hexagon => if (size == 32 or size == 64) {
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force_abi = true;
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},
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.aarch64_32, .amdgcn => if (size == 128) {
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.ve, .xtensa => if (size == 64) {
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abi = size;
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pref = size;
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},
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@ -663,25 +716,34 @@ const DataLayoutBuilder = struct {
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abi = 64;
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pref = 64;
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},
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.ve => if (size == 64) {
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abi = size;
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pref = size;
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},
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else => {},
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},
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.aggregate => if (self.target.os.tag == .uefi or self.target.os.tag == .windows or
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self.target.cpu.arch.isArmOrThumb())
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{
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pref = @min(pref, self.target.ptrBitWidth());
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} else if (self.target.cpu.arch == .hexagon) {
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abi = 0;
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pref = 0;
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} else if (self.target.cpu.arch == .s390x) {
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abi = 8;
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pref = 16;
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} else if (self.target.cpu.arch == .msp430) {
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abi = 8;
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pref = 8;
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} else switch (self.target.cpu.arch) {
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.arc, .csky => {
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abi = 0;
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pref = 32;
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},
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.hexagon => {
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abi = 0;
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pref = 0;
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},
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.m68k => {
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abi = 0;
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pref = 16;
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},
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.msp430 => {
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abi = 8;
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pref = 8;
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},
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.s390x => {
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abi = 8;
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pref = 16;
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},
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else => {},
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},
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}
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if (kind != .vector and self.target.cpu.arch == .avr) {
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@ -11005,198 +11067,6 @@ pub const FuncGen = struct {
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}
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};
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fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
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switch (arch) {
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.aarch64, .aarch64_be, .aarch64_32 => {
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llvm.LLVMInitializeAArch64Target();
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llvm.LLVMInitializeAArch64TargetInfo();
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llvm.LLVMInitializeAArch64TargetMC();
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llvm.LLVMInitializeAArch64AsmPrinter();
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llvm.LLVMInitializeAArch64AsmParser();
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},
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.amdgcn => {
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llvm.LLVMInitializeAMDGPUTarget();
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llvm.LLVMInitializeAMDGPUTargetInfo();
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llvm.LLVMInitializeAMDGPUTargetMC();
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llvm.LLVMInitializeAMDGPUAsmPrinter();
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llvm.LLVMInitializeAMDGPUAsmParser();
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},
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.thumb, .thumbeb, .arm, .armeb => {
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llvm.LLVMInitializeARMTarget();
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llvm.LLVMInitializeARMTargetInfo();
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llvm.LLVMInitializeARMTargetMC();
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llvm.LLVMInitializeARMAsmPrinter();
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llvm.LLVMInitializeARMAsmParser();
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},
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.avr => {
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llvm.LLVMInitializeAVRTarget();
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llvm.LLVMInitializeAVRTargetInfo();
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llvm.LLVMInitializeAVRTargetMC();
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llvm.LLVMInitializeAVRAsmPrinter();
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llvm.LLVMInitializeAVRAsmParser();
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},
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.bpfel, .bpfeb => {
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llvm.LLVMInitializeBPFTarget();
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llvm.LLVMInitializeBPFTargetInfo();
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llvm.LLVMInitializeBPFTargetMC();
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llvm.LLVMInitializeBPFAsmPrinter();
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llvm.LLVMInitializeBPFAsmParser();
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},
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.hexagon => {
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llvm.LLVMInitializeHexagonTarget();
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llvm.LLVMInitializeHexagonTargetInfo();
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llvm.LLVMInitializeHexagonTargetMC();
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llvm.LLVMInitializeHexagonAsmPrinter();
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llvm.LLVMInitializeHexagonAsmParser();
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},
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.lanai => {
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llvm.LLVMInitializeLanaiTarget();
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llvm.LLVMInitializeLanaiTargetInfo();
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llvm.LLVMInitializeLanaiTargetMC();
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llvm.LLVMInitializeLanaiAsmPrinter();
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llvm.LLVMInitializeLanaiAsmParser();
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},
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.mips, .mipsel, .mips64, .mips64el => {
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llvm.LLVMInitializeMipsTarget();
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llvm.LLVMInitializeMipsTargetInfo();
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llvm.LLVMInitializeMipsTargetMC();
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llvm.LLVMInitializeMipsAsmPrinter();
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llvm.LLVMInitializeMipsAsmParser();
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},
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.msp430 => {
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llvm.LLVMInitializeMSP430Target();
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llvm.LLVMInitializeMSP430TargetInfo();
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llvm.LLVMInitializeMSP430TargetMC();
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llvm.LLVMInitializeMSP430AsmPrinter();
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llvm.LLVMInitializeMSP430AsmParser();
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},
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.nvptx, .nvptx64 => {
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llvm.LLVMInitializeNVPTXTarget();
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llvm.LLVMInitializeNVPTXTargetInfo();
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llvm.LLVMInitializeNVPTXTargetMC();
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llvm.LLVMInitializeNVPTXAsmPrinter();
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// There is no LLVMInitializeNVPTXAsmParser function available.
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},
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.powerpc, .powerpcle, .powerpc64, .powerpc64le => {
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llvm.LLVMInitializePowerPCTarget();
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llvm.LLVMInitializePowerPCTargetInfo();
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llvm.LLVMInitializePowerPCTargetMC();
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llvm.LLVMInitializePowerPCAsmPrinter();
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llvm.LLVMInitializePowerPCAsmParser();
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},
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.riscv32, .riscv64 => {
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llvm.LLVMInitializeRISCVTarget();
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llvm.LLVMInitializeRISCVTargetInfo();
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llvm.LLVMInitializeRISCVTargetMC();
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llvm.LLVMInitializeRISCVAsmPrinter();
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llvm.LLVMInitializeRISCVAsmParser();
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},
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.sparc, .sparc64, .sparcel => {
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llvm.LLVMInitializeSparcTarget();
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llvm.LLVMInitializeSparcTargetInfo();
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llvm.LLVMInitializeSparcTargetMC();
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llvm.LLVMInitializeSparcAsmPrinter();
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llvm.LLVMInitializeSparcAsmParser();
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},
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.s390x => {
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llvm.LLVMInitializeSystemZTarget();
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llvm.LLVMInitializeSystemZTargetInfo();
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llvm.LLVMInitializeSystemZTargetMC();
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llvm.LLVMInitializeSystemZAsmPrinter();
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llvm.LLVMInitializeSystemZAsmParser();
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},
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.wasm32, .wasm64 => {
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llvm.LLVMInitializeWebAssemblyTarget();
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llvm.LLVMInitializeWebAssemblyTargetInfo();
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llvm.LLVMInitializeWebAssemblyTargetMC();
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llvm.LLVMInitializeWebAssemblyAsmPrinter();
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llvm.LLVMInitializeWebAssemblyAsmParser();
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},
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.x86, .x86_64 => {
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llvm.LLVMInitializeX86Target();
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llvm.LLVMInitializeX86TargetInfo();
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llvm.LLVMInitializeX86TargetMC();
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llvm.LLVMInitializeX86AsmPrinter();
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llvm.LLVMInitializeX86AsmParser();
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},
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.xtensa => {
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if (build_options.llvm_has_xtensa) {
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llvm.LLVMInitializeXtensaTarget();
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llvm.LLVMInitializeXtensaTargetInfo();
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llvm.LLVMInitializeXtensaTargetMC();
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llvm.LLVMInitializeXtensaAsmPrinter();
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llvm.LLVMInitializeXtensaAsmParser();
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}
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},
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.xcore => {
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llvm.LLVMInitializeXCoreTarget();
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llvm.LLVMInitializeXCoreTargetInfo();
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llvm.LLVMInitializeXCoreTargetMC();
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llvm.LLVMInitializeXCoreAsmPrinter();
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// There is no LLVMInitializeXCoreAsmParser function.
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},
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.m68k => {
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if (build_options.llvm_has_m68k) {
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llvm.LLVMInitializeM68kTarget();
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llvm.LLVMInitializeM68kTargetInfo();
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llvm.LLVMInitializeM68kTargetMC();
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llvm.LLVMInitializeM68kAsmPrinter();
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llvm.LLVMInitializeM68kAsmParser();
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}
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},
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.csky => {
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if (build_options.llvm_has_csky) {
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llvm.LLVMInitializeCSKYTarget();
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llvm.LLVMInitializeCSKYTargetInfo();
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llvm.LLVMInitializeCSKYTargetMC();
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// There is no LLVMInitializeCSKYAsmPrinter function.
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llvm.LLVMInitializeCSKYAsmParser();
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}
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},
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.ve => {
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llvm.LLVMInitializeVETarget();
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llvm.LLVMInitializeVETargetInfo();
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llvm.LLVMInitializeVETargetMC();
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llvm.LLVMInitializeVEAsmPrinter();
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llvm.LLVMInitializeVEAsmParser();
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},
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.arc => {
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if (build_options.llvm_has_arc) {
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llvm.LLVMInitializeARCTarget();
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llvm.LLVMInitializeARCTargetInfo();
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llvm.LLVMInitializeARCTargetMC();
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llvm.LLVMInitializeARCAsmPrinter();
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// There is no LLVMInitializeARCAsmParser function.
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}
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},
|
||||
|
||||
// LLVM backends that have no initialization functions.
|
||||
.tce,
|
||||
.tcele,
|
||||
.r600,
|
||||
.le32,
|
||||
.le64,
|
||||
.amdil,
|
||||
.amdil64,
|
||||
.hsail,
|
||||
.hsail64,
|
||||
.shave,
|
||||
.spir,
|
||||
.spir64,
|
||||
.kalimba,
|
||||
.renderscript32,
|
||||
.renderscript64,
|
||||
.dxil,
|
||||
.loongarch32,
|
||||
.loongarch64,
|
||||
=> {},
|
||||
|
||||
.spu_2 => unreachable, // LLVM does not support this backend
|
||||
.spirv32 => unreachable, // LLVM does not support this backend
|
||||
.spirv64 => unreachable, // LLVM does not support this backend
|
||||
}
|
||||
}
|
||||
|
||||
fn toLlvmAtomicOrdering(atomic_order: std.builtin.AtomicOrder) Builder.AtomicOrdering {
|
||||
return switch (atomic_order) {
|
||||
.Unordered => .unordered,
|
||||
|
|
@ -11318,6 +11188,9 @@ fn llvmAddrSpaceInfo(target: std.Target) []const AddrSpaceInfo {
|
|||
.{ .zig = null, .llvm = Builder.AddrSpace.wasm.externref, .non_integral = true, .size = 8, .abi = 8 },
|
||||
.{ .zig = null, .llvm = Builder.AddrSpace.wasm.funcref, .non_integral = true, .size = 8, .abi = 8 },
|
||||
},
|
||||
.m68k => &.{
|
||||
.{ .zig = .generic, .llvm = .default, .abi = 16, .pref = 32 },
|
||||
},
|
||||
else => &.{
|
||||
.{ .zig = .generic, .llvm = .default },
|
||||
},
|
||||
|
|
|
|||
|
|
@ -6366,7 +6366,7 @@ pub fn initializeLLVMTarget(self: *const Builder, arch: std.Target.Cpu.Arch) voi
|
|||
llvm.LLVMInitializeXtensaTarget();
|
||||
llvm.LLVMInitializeXtensaTargetInfo();
|
||||
llvm.LLVMInitializeXtensaTargetMC();
|
||||
llvm.LLVMInitializeXtensaAsmPrinter();
|
||||
// There is no LLVMInitializeXtensaAsmPrinter function.
|
||||
llvm.LLVMInitializeXtensaAsmParser();
|
||||
}
|
||||
},
|
||||
|
|
|
|||
|
|
@ -1337,7 +1337,6 @@ pub extern fn LLVMInitializeSystemZAsmPrinter() void;
|
|||
pub extern fn LLVMInitializeWebAssemblyAsmPrinter() void;
|
||||
pub extern fn LLVMInitializeX86AsmPrinter() void;
|
||||
pub extern fn LLVMInitializeXCoreAsmPrinter() void;
|
||||
pub extern fn LLVMInitializeXtensaAsmPrinter() void;
|
||||
pub extern fn LLVMInitializeM68kAsmPrinter() void;
|
||||
pub extern fn LLVMInitializeVEAsmPrinter() void;
|
||||
pub extern fn LLVMInitializeARCAsmPrinter() void;
|
||||
|
|
|
|||
|
|
@ -1,9 +1,17 @@
|
|||
const std = @import("std");
|
||||
const Cases = @import("src/Cases.zig");
|
||||
|
||||
pub fn addCases(cases: *Cases) !void {
|
||||
pub const BuildOptions = struct {
|
||||
enable_llvm: bool,
|
||||
llvm_has_m68k: bool,
|
||||
llvm_has_csky: bool,
|
||||
llvm_has_arc: bool,
|
||||
llvm_has_xtensa: bool,
|
||||
};
|
||||
|
||||
pub fn addCases(cases: *Cases, build_options: BuildOptions) !void {
|
||||
try @import("compile_errors.zig").addCases(cases);
|
||||
try @import("cbe.zig").addCases(cases);
|
||||
try @import("llvm_targets.zig").addCases(cases);
|
||||
try @import("llvm_targets.zig").addCases(cases, build_options);
|
||||
try @import("nvptx.zig").addCases(cases);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -18,6 +18,8 @@ const targets = [_]std.zig.CrossTarget{
|
|||
.{ .cpu_arch = .amdgcn, .os_tag = .amdpal, .abi = .none },
|
||||
.{ .cpu_arch = .amdgcn, .os_tag = .linux, .abi = .none },
|
||||
//.{ .cpu_arch = .amdgcn, .os_tag = .mesa3d, .abi = .none },
|
||||
.{ .cpu_arch = .arc, .os_tag = .freestanding, .abi = .none },
|
||||
.{ .cpu_arch = .arc, .os_tag = .linux, .abi = .none },
|
||||
.{ .cpu_arch = .arm, .os_tag = .freestanding, .abi = .none },
|
||||
.{ .cpu_arch = .arm, .os_tag = .linux, .abi = .none },
|
||||
.{ .cpu_arch = .arm, .os_tag = .uefi, .abi = .none },
|
||||
|
|
@ -30,7 +32,11 @@ const targets = [_]std.zig.CrossTarget{
|
|||
.{ .cpu_arch = .bpfel, .os_tag = .linux, .abi = .none },
|
||||
.{ .cpu_arch = .bpfeb, .os_tag = .linux, .abi = .gnu },
|
||||
.{ .cpu_arch = .bpfeb, .os_tag = .linux, .abi = .none },
|
||||
.{ .cpu_arch = .csky, .os_tag = .freestanding, .abi = .none },
|
||||
.{ .cpu_arch = .csky, .os_tag = .linux, .abi = .none },
|
||||
.{ .cpu_arch = .hexagon, .os_tag = .linux, .abi = .none },
|
||||
.{ .cpu_arch = .m68k, .os_tag = .freestanding, .abi = .none },
|
||||
.{ .cpu_arch = .m68k, .os_tag = .linux, .abi = .none },
|
||||
.{ .cpu_arch = .mips, .os_tag = .linux, .abi = .gnueabihf },
|
||||
.{ .cpu_arch = .mips, .os_tag = .linux, .abi = .musl },
|
||||
.{ .cpu_arch = .mips, .os_tag = .linux, .abi = .none },
|
||||
|
|
@ -117,10 +123,20 @@ const targets = [_]std.zig.CrossTarget{
|
|||
.{ .cpu_arch = .x86_64, .os_tag = .uefi, .abi = .none },
|
||||
.{ .cpu_arch = .x86_64, .os_tag = .windows, .abi = .gnu },
|
||||
.{ .cpu_arch = .x86_64, .os_tag = .windows, .abi = .msvc },
|
||||
.{ .cpu_arch = .xtensa, .os_tag = .freestanding, .abi = .none },
|
||||
.{ .cpu_arch = .xtensa, .os_tag = .linux, .abi = .none },
|
||||
};
|
||||
|
||||
pub fn addCases(ctx: *Cases) !void {
|
||||
pub fn addCases(ctx: *Cases, build_options: @import("cases.zig").BuildOptions) !void {
|
||||
if (!build_options.enable_llvm) return;
|
||||
for (targets) |target| {
|
||||
if (target.cpu_arch) |arch| switch (arch) {
|
||||
.m68k => if (!build_options.llvm_has_m68k) continue,
|
||||
.csky => if (!build_options.llvm_has_csky) continue,
|
||||
.arc => if (!build_options.llvm_has_arc) continue,
|
||||
.xtensa => if (!build_options.llvm_has_xtensa) continue,
|
||||
else => {},
|
||||
};
|
||||
var case = ctx.noEmitUsingLlvmBackend("llvm_targets", target);
|
||||
case.addCompile("");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1156,6 +1156,7 @@ pub fn addCases(
|
|||
parent_step: *Step,
|
||||
opt_test_filter: ?[]const u8,
|
||||
check_case_exe: *std.Build.Step.Compile,
|
||||
build_options: @import("cases.zig").BuildOptions,
|
||||
) !void {
|
||||
const arena = b.allocator;
|
||||
const gpa = b.allocator;
|
||||
|
|
@ -1166,7 +1167,7 @@ pub fn addCases(
|
|||
defer dir.close();
|
||||
|
||||
cases.addFromDir(dir);
|
||||
try @import("cases.zig").addCases(&cases);
|
||||
try @import("cases.zig").addCases(&cases, build_options);
|
||||
|
||||
const cases_dir_path = try b.build_root.join(b.allocator, &.{ "test", "cases" });
|
||||
cases.lowerToBuildSteps(
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue