mirror of
https://codeberg.org/ziglang/zig.git
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compiler: delete arm backend
this backend was abandoned before it was completed, and it is not worth salvaging.
This commit is contained in:
Andrew Kelley
parent
20a543097b
commit
a13f0d40eb
8 changed files with 5 additions and 8997 deletions
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@ -549,11 +549,6 @@ set(ZIG_STAGE2_SOURCES
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src/Value.zig
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src/Zcu.zig
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src/Zcu/PerThread.zig
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src/arch/arm/CodeGen.zig
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src/arch/arm/Emit.zig
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src/arch/arm/Mir.zig
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src/arch/arm/abi.zig
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src/arch/arm/bits.zig
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src/arch/riscv64/abi.zig
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src/arch/riscv64/bits.zig
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src/arch/riscv64/CodeGen.zig
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File diff suppressed because it is too large
Load diff
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@ -1,712 +0,0 @@
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//! This file contains the functionality for lowering AArch32 MIR into
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//! machine code
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const Emit = @This();
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const builtin = @import("builtin");
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const std = @import("std");
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const math = std.math;
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const Mir = @import("Mir.zig");
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const bits = @import("bits.zig");
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const link = @import("../../link.zig");
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const Zcu = @import("../../Zcu.zig");
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const Type = @import("../../Type.zig");
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const ErrorMsg = Zcu.ErrorMsg;
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const Target = std.Target;
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const assert = std.debug.assert;
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const Instruction = bits.Instruction;
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const Register = bits.Register;
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const log = std.log.scoped(.aarch32_emit);
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const CodeGen = @import("CodeGen.zig");
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mir: Mir,
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bin_file: *link.File,
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debug_output: link.File.DebugInfoOutput,
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target: *const std.Target,
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err_msg: ?*ErrorMsg = null,
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src_loc: Zcu.LazySrcLoc,
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code: *std.ArrayListUnmanaged(u8),
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prev_di_line: u32,
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prev_di_column: u32,
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/// Relative to the beginning of `code`.
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prev_di_pc: usize,
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/// The amount of stack space consumed by the saved callee-saved
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/// registers in bytes
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saved_regs_stack_space: u32,
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/// The final stack frame size of the function (already aligned to the
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/// respective stack alignment). Does not include prologue stack space.
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stack_size: u32,
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/// The branch type of every branch
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branch_types: std.AutoHashMapUnmanaged(Mir.Inst.Index, BranchType) = .empty,
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/// For every forward branch, maps the target instruction to a list of
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/// branches which branch to this target instruction
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branch_forward_origins: std.AutoHashMapUnmanaged(Mir.Inst.Index, std.ArrayListUnmanaged(Mir.Inst.Index)) = .empty,
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/// For backward branches: stores the code offset of the target
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/// instruction
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///
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/// For forward branches: stores the code offset of the branch
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/// instruction
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code_offset_mapping: std.AutoHashMapUnmanaged(Mir.Inst.Index, usize) = .empty,
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const InnerError = error{
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OutOfMemory,
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EmitFail,
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};
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const BranchType = enum {
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b,
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fn default(tag: Mir.Inst.Tag) BranchType {
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return switch (tag) {
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.b => .b,
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else => unreachable,
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};
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}
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};
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pub fn emitMir(
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emit: *Emit,
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) !void {
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const mir_tags = emit.mir.instructions.items(.tag);
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// Find smallest lowerings for branch instructions
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try emit.lowerBranches();
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// Emit machine code
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for (mir_tags, 0..) |tag, index| {
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const inst = @as(u32, @intCast(index));
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switch (tag) {
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.add => try emit.mirDataProcessing(inst),
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.adds => try emit.mirDataProcessing(inst),
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.@"and" => try emit.mirDataProcessing(inst),
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.cmp => try emit.mirDataProcessing(inst),
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.eor => try emit.mirDataProcessing(inst),
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.mov => try emit.mirDataProcessing(inst),
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.mvn => try emit.mirDataProcessing(inst),
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.orr => try emit.mirDataProcessing(inst),
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.rsb => try emit.mirDataProcessing(inst),
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.sub => try emit.mirDataProcessing(inst),
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.subs => try emit.mirDataProcessing(inst),
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.sub_sp_scratch_r4 => try emit.mirSubStackPointer(inst),
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.asr => try emit.mirShift(inst),
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.lsl => try emit.mirShift(inst),
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.lsr => try emit.mirShift(inst),
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.b => try emit.mirBranch(inst),
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.undefined_instruction => try emit.mirUndefinedInstruction(),
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.bkpt => try emit.mirExceptionGeneration(inst),
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.blx => try emit.mirBranchExchange(inst),
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.bx => try emit.mirBranchExchange(inst),
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.dbg_line => try emit.mirDbgLine(inst),
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.dbg_prologue_end => try emit.mirDebugPrologueEnd(),
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.dbg_epilogue_begin => try emit.mirDebugEpilogueBegin(),
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.ldr => try emit.mirLoadStore(inst),
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.ldrb => try emit.mirLoadStore(inst),
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.str => try emit.mirLoadStore(inst),
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.strb => try emit.mirLoadStore(inst),
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.ldr_ptr_stack_argument => try emit.mirLoadStackArgument(inst),
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.ldr_stack_argument => try emit.mirLoadStackArgument(inst),
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.ldrb_stack_argument => try emit.mirLoadStackArgument(inst),
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.ldrh_stack_argument => try emit.mirLoadStackArgument(inst),
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.ldrsb_stack_argument => try emit.mirLoadStackArgument(inst),
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.ldrsh_stack_argument => try emit.mirLoadStackArgument(inst),
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.ldrh => try emit.mirLoadStoreExtra(inst),
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.ldrsb => try emit.mirLoadStoreExtra(inst),
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.ldrsh => try emit.mirLoadStoreExtra(inst),
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.strh => try emit.mirLoadStoreExtra(inst),
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.movw => try emit.mirSpecialMove(inst),
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.movt => try emit.mirSpecialMove(inst),
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.mul => try emit.mirMultiply(inst),
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.smulbb => try emit.mirMultiply(inst),
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.smull => try emit.mirMultiplyLong(inst),
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.umull => try emit.mirMultiplyLong(inst),
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.nop => try emit.mirNop(),
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.pop => try emit.mirBlockDataTransfer(inst),
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.push => try emit.mirBlockDataTransfer(inst),
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.svc => try emit.mirSupervisorCall(inst),
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.sbfx => try emit.mirBitFieldExtract(inst),
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.ubfx => try emit.mirBitFieldExtract(inst),
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}
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}
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}
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pub fn deinit(emit: *Emit) void {
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const comp = emit.bin_file.comp;
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const gpa = comp.gpa;
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var iter = emit.branch_forward_origins.valueIterator();
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while (iter.next()) |origin_list| {
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origin_list.deinit(gpa);
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}
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emit.branch_types.deinit(gpa);
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emit.branch_forward_origins.deinit(gpa);
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emit.code_offset_mapping.deinit(gpa);
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emit.* = undefined;
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}
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fn optimalBranchType(emit: *Emit, tag: Mir.Inst.Tag, offset: i64) !BranchType {
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assert(std.mem.isAlignedGeneric(i64, offset, 4)); // misaligned offset
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switch (tag) {
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.b => {
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if (std.math.cast(i24, @divExact(offset, 4))) |_| {
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return BranchType.b;
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} else {
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return emit.fail("TODO support larger branches", .{});
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}
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},
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else => unreachable,
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}
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}
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fn instructionSize(emit: *Emit, inst: Mir.Inst.Index) usize {
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const tag = emit.mir.instructions.items(.tag)[inst];
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if (isBranch(tag)) {
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switch (emit.branch_types.get(inst).?) {
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.b => return 4,
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}
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}
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switch (tag) {
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.dbg_line,
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.dbg_epilogue_begin,
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.dbg_prologue_end,
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=> return 0,
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.sub_sp_scratch_r4 => {
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const imm32 = emit.mir.instructions.items(.data)[inst].imm32;
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if (imm32 == 0) {
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return 0 * 4;
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} else if (Instruction.Operand.fromU32(imm32) != null) {
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// sub
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return 1 * 4;
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} else if (emit.target.cpu.has(.arm, .has_v7)) {
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// movw; movt; sub
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return 3 * 4;
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} else {
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// mov; orr; orr; orr; sub
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return 5 * 4;
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}
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},
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else => return 4,
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}
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}
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fn isBranch(tag: Mir.Inst.Tag) bool {
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return switch (tag) {
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.b => true,
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else => false,
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};
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}
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fn branchTarget(emit: *Emit, inst: Mir.Inst.Index) Mir.Inst.Index {
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const tag = emit.mir.instructions.items(.tag)[inst];
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switch (tag) {
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.b => return emit.mir.instructions.items(.data)[inst].inst,
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else => unreachable,
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}
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}
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fn lowerBranches(emit: *Emit) !void {
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const comp = emit.bin_file.comp;
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const gpa = comp.gpa;
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const mir_tags = emit.mir.instructions.items(.tag);
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// First pass: Note down all branches and their target
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// instructions, i.e. populate branch_types,
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// branch_forward_origins, and code_offset_mapping
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//
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// TODO optimization opportunity: do this in codegen while
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// generating MIR
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for (mir_tags, 0..) |tag, index| {
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const inst = @as(u32, @intCast(index));
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if (isBranch(tag)) {
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const target_inst = emit.branchTarget(inst);
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// Remember this branch instruction
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try emit.branch_types.put(gpa, inst, BranchType.default(tag));
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// Forward branches require some extra stuff: We only
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// know their offset once we arrive at the target
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// instruction. Therefore, we need to be able to
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// access the branch instruction when we visit the
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// target instruction in order to manipulate its type
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// etc.
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if (target_inst > inst) {
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// Remember the branch instruction index
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try emit.code_offset_mapping.put(gpa, inst, 0);
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if (emit.branch_forward_origins.getPtr(target_inst)) |origin_list| {
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try origin_list.append(gpa, inst);
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} else {
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var origin_list: std.ArrayListUnmanaged(Mir.Inst.Index) = .empty;
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try origin_list.append(gpa, inst);
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try emit.branch_forward_origins.put(gpa, target_inst, origin_list);
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}
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}
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// Remember the target instruction index so that we
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// update the real code offset in all future passes
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//
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// putNoClobber may not be used as the put operation
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// may clobber the entry when multiple branches branch
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// to the same target instruction
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try emit.code_offset_mapping.put(gpa, target_inst, 0);
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}
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}
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// Further passes: Until all branches are lowered, interate
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// through all instructions and calculate new offsets and
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// potentially new branch types
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var all_branches_lowered = false;
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while (!all_branches_lowered) {
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all_branches_lowered = true;
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var current_code_offset: usize = 0;
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for (mir_tags, 0..) |tag, index| {
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const inst = @as(u32, @intCast(index));
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// If this instruction contained in the code offset
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// mapping (when it is a target of a branch or if it is a
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// forward branch), update the code offset
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if (emit.code_offset_mapping.getPtr(inst)) |offset| {
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offset.* = current_code_offset;
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}
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// If this instruction is a backward branch, calculate the
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// offset, which may potentially update the branch type
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if (isBranch(tag)) {
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const target_inst = emit.branchTarget(inst);
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if (target_inst < inst) {
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const target_offset = emit.code_offset_mapping.get(target_inst).?;
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const offset = @as(i64, @intCast(target_offset)) - @as(i64, @intCast(current_code_offset + 8));
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const branch_type = emit.branch_types.getPtr(inst).?;
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const optimal_branch_type = try emit.optimalBranchType(tag, offset);
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if (branch_type.* != optimal_branch_type) {
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branch_type.* = optimal_branch_type;
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all_branches_lowered = false;
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}
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log.debug("lowerBranches: branch {} has offset {}", .{ inst, offset });
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}
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}
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// If this instruction is the target of one or more
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// forward branches, calculate the offset, which may
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// potentially update the branch type
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if (emit.branch_forward_origins.get(inst)) |origin_list| {
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for (origin_list.items) |forward_branch_inst| {
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const branch_tag = emit.mir.instructions.items(.tag)[forward_branch_inst];
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const forward_branch_inst_offset = emit.code_offset_mapping.get(forward_branch_inst).?;
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const offset = @as(i64, @intCast(current_code_offset)) - @as(i64, @intCast(forward_branch_inst_offset + 8));
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const branch_type = emit.branch_types.getPtr(forward_branch_inst).?;
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const optimal_branch_type = try emit.optimalBranchType(branch_tag, offset);
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if (branch_type.* != optimal_branch_type) {
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branch_type.* = optimal_branch_type;
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all_branches_lowered = false;
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}
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log.debug("lowerBranches: branch {} has offset {}", .{ forward_branch_inst, offset });
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}
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}
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// Increment code offset
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current_code_offset += emit.instructionSize(inst);
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}
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}
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}
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fn writeInstruction(emit: *Emit, instruction: Instruction) !void {
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const comp = emit.bin_file.comp;
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const gpa = comp.gpa;
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const endian = emit.target.cpu.arch.endian();
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std.mem.writeInt(u32, try emit.code.addManyAsArray(gpa, 4), instruction.toU32(), endian);
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}
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fn fail(emit: *Emit, comptime format: []const u8, args: anytype) InnerError {
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@branchHint(.cold);
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assert(emit.err_msg == null);
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const comp = emit.bin_file.comp;
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const gpa = comp.gpa;
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emit.err_msg = try ErrorMsg.create(gpa, emit.src_loc, format, args);
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return error.EmitFail;
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}
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fn dbgAdvancePCAndLine(self: *Emit, line: u32, column: u32) !void {
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const delta_line = @as(i32, @intCast(line)) - @as(i32, @intCast(self.prev_di_line));
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const delta_pc: usize = self.code.items.len - self.prev_di_pc;
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switch (self.debug_output) {
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.dwarf => |dw| {
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try dw.advancePCAndLine(delta_line, delta_pc);
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self.prev_di_line = line;
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self.prev_di_column = column;
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self.prev_di_pc = self.code.items.len;
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},
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.plan9 => |dbg_out| {
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if (delta_pc <= 0) return; // only do this when the pc changes
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// increasing the line number
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try link.File.Plan9.changeLine(&dbg_out.dbg_line, delta_line);
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// increasing the pc
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const d_pc_p9 = @as(i64, @intCast(delta_pc)) - dbg_out.pc_quanta;
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if (d_pc_p9 > 0) {
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// minus one because if its the last one, we want to leave space to change the line which is one pc quanta
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try dbg_out.dbg_line.append(@as(u8, @intCast(@divExact(d_pc_p9, dbg_out.pc_quanta) + 128)) - dbg_out.pc_quanta);
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if (dbg_out.pcop_change_index) |pci|
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dbg_out.dbg_line.items[pci] += 1;
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dbg_out.pcop_change_index = @as(u32, @intCast(dbg_out.dbg_line.items.len - 1));
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} else if (d_pc_p9 == 0) {
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// we don't need to do anything, because adding the pc quanta does it for us
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} else unreachable;
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if (dbg_out.start_line == null)
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dbg_out.start_line = self.prev_di_line;
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dbg_out.end_line = line;
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// only do this if the pc changed
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self.prev_di_line = line;
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self.prev_di_column = column;
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self.prev_di_pc = self.code.items.len;
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},
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.none => {},
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}
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}
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fn mirDataProcessing(emit: *Emit, inst: Mir.Inst.Index) !void {
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const tag = emit.mir.instructions.items(.tag)[inst];
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const cond = emit.mir.instructions.items(.cond)[inst];
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switch (tag) {
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.add,
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.adds,
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.@"and",
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.eor,
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.orr,
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.rsb,
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.sub,
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.subs,
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=> {
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const rr_op = emit.mir.instructions.items(.data)[inst].rr_op;
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switch (tag) {
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.add => try emit.writeInstruction(Instruction.add(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.adds => try emit.writeInstruction(Instruction.adds(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.@"and" => try emit.writeInstruction(Instruction.@"and"(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.eor => try emit.writeInstruction(Instruction.eor(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.orr => try emit.writeInstruction(Instruction.orr(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.rsb => try emit.writeInstruction(Instruction.rsb(cond, rr_op.rd, rr_op.rn, rr_op.op)),
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.sub => try emit.writeInstruction(Instruction.sub(cond, rr_op.rd, rr_op.rn, rr_op.op)),
|
||||
.subs => try emit.writeInstruction(Instruction.subs(cond, rr_op.rd, rr_op.rn, rr_op.op)),
|
||||
else => unreachable,
|
||||
}
|
||||
},
|
||||
.cmp => {
|
||||
const r_op_cmp = emit.mir.instructions.items(.data)[inst].r_op_cmp;
|
||||
try emit.writeInstruction(Instruction.cmp(cond, r_op_cmp.rn, r_op_cmp.op));
|
||||
},
|
||||
.mov,
|
||||
.mvn,
|
||||
=> {
|
||||
const r_op_mov = emit.mir.instructions.items(.data)[inst].r_op_mov;
|
||||
switch (tag) {
|
||||
.mov => try emit.writeInstruction(Instruction.mov(cond, r_op_mov.rd, r_op_mov.op)),
|
||||
.mvn => try emit.writeInstruction(Instruction.mvn(cond, r_op_mov.rd, r_op_mov.op)),
|
||||
else => unreachable,
|
||||
}
|
||||
},
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn mirSubStackPointer(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const cond = emit.mir.instructions.items(.cond)[inst];
|
||||
const imm32 = emit.mir.instructions.items(.data)[inst].imm32;
|
||||
|
||||
switch (tag) {
|
||||
.sub_sp_scratch_r4 => {
|
||||
if (imm32 == 0) return;
|
||||
|
||||
const operand = Instruction.Operand.fromU32(imm32) orelse blk: {
|
||||
const scratch: Register = .r4;
|
||||
|
||||
if (emit.target.cpu.has(.arm, .has_v7)) {
|
||||
try emit.writeInstruction(Instruction.movw(cond, scratch, @as(u16, @truncate(imm32))));
|
||||
try emit.writeInstruction(Instruction.movt(cond, scratch, @as(u16, @truncate(imm32 >> 16))));
|
||||
} else {
|
||||
try emit.writeInstruction(Instruction.mov(cond, scratch, Instruction.Operand.imm(@as(u8, @truncate(imm32)), 0)));
|
||||
try emit.writeInstruction(Instruction.orr(cond, scratch, scratch, Instruction.Operand.imm(@as(u8, @truncate(imm32 >> 8)), 12)));
|
||||
try emit.writeInstruction(Instruction.orr(cond, scratch, scratch, Instruction.Operand.imm(@as(u8, @truncate(imm32 >> 16)), 8)));
|
||||
try emit.writeInstruction(Instruction.orr(cond, scratch, scratch, Instruction.Operand.imm(@as(u8, @truncate(imm32 >> 24)), 4)));
|
||||
}
|
||||
|
||||
break :blk Instruction.Operand.reg(scratch, Instruction.Operand.Shift.none);
|
||||
};
|
||||
|
||||
try emit.writeInstruction(Instruction.sub(cond, .sp, .sp, operand));
|
||||
},
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn mirShift(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const cond = emit.mir.instructions.items(.cond)[inst];
|
||||
const rr_shift = emit.mir.instructions.items(.data)[inst].rr_shift;
|
||||
|
||||
switch (tag) {
|
||||
.asr => try emit.writeInstruction(Instruction.asr(cond, rr_shift.rd, rr_shift.rm, rr_shift.shift_amount)),
|
||||
.lsl => try emit.writeInstruction(Instruction.lsl(cond, rr_shift.rd, rr_shift.rm, rr_shift.shift_amount)),
|
||||
.lsr => try emit.writeInstruction(Instruction.lsr(cond, rr_shift.rd, rr_shift.rm, rr_shift.shift_amount)),
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn mirBranch(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const cond = emit.mir.instructions.items(.cond)[inst];
|
||||
const target_inst = emit.mir.instructions.items(.data)[inst].inst;
|
||||
|
||||
const offset = @as(i64, @intCast(emit.code_offset_mapping.get(target_inst).?)) - @as(i64, @intCast(emit.code.items.len + 8));
|
||||
const branch_type = emit.branch_types.get(inst).?;
|
||||
|
||||
switch (branch_type) {
|
||||
.b => switch (tag) {
|
||||
.b => try emit.writeInstruction(Instruction.b(cond, @as(i26, @intCast(offset)))),
|
||||
else => unreachable,
|
||||
},
|
||||
}
|
||||
}
|
||||
|
||||
fn mirUndefinedInstruction(emit: *Emit) !void {
|
||||
try emit.writeInstruction(Instruction.undefinedInstruction());
|
||||
}
|
||||
|
||||
fn mirExceptionGeneration(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const imm16 = emit.mir.instructions.items(.data)[inst].imm16;
|
||||
|
||||
switch (tag) {
|
||||
.bkpt => try emit.writeInstruction(Instruction.bkpt(imm16)),
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn mirBranchExchange(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const cond = emit.mir.instructions.items(.cond)[inst];
|
||||
const reg = emit.mir.instructions.items(.data)[inst].reg;
|
||||
|
||||
switch (tag) {
|
||||
.blx => try emit.writeInstruction(Instruction.blx(cond, reg)),
|
||||
.bx => try emit.writeInstruction(Instruction.bx(cond, reg)),
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn mirDbgLine(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const dbg_line_column = emit.mir.instructions.items(.data)[inst].dbg_line_column;
|
||||
|
||||
switch (tag) {
|
||||
.dbg_line => try emit.dbgAdvancePCAndLine(dbg_line_column.line, dbg_line_column.column),
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn mirDebugPrologueEnd(emit: *Emit) !void {
|
||||
switch (emit.debug_output) {
|
||||
.dwarf => |dw| {
|
||||
try dw.setPrologueEnd();
|
||||
try emit.dbgAdvancePCAndLine(emit.prev_di_line, emit.prev_di_column);
|
||||
},
|
||||
.plan9 => {},
|
||||
.none => {},
|
||||
}
|
||||
}
|
||||
|
||||
fn mirDebugEpilogueBegin(emit: *Emit) !void {
|
||||
switch (emit.debug_output) {
|
||||
.dwarf => |dw| {
|
||||
try dw.setEpilogueBegin();
|
||||
try emit.dbgAdvancePCAndLine(emit.prev_di_line, emit.prev_di_column);
|
||||
},
|
||||
.plan9 => {},
|
||||
.none => {},
|
||||
}
|
||||
}
|
||||
|
||||
fn mirLoadStore(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const cond = emit.mir.instructions.items(.cond)[inst];
|
||||
const rr_offset = emit.mir.instructions.items(.data)[inst].rr_offset;
|
||||
|
||||
switch (tag) {
|
||||
.ldr => try emit.writeInstruction(Instruction.ldr(cond, rr_offset.rt, rr_offset.rn, rr_offset.offset)),
|
||||
.ldrb => try emit.writeInstruction(Instruction.ldrb(cond, rr_offset.rt, rr_offset.rn, rr_offset.offset)),
|
||||
.str => try emit.writeInstruction(Instruction.str(cond, rr_offset.rt, rr_offset.rn, rr_offset.offset)),
|
||||
.strb => try emit.writeInstruction(Instruction.strb(cond, rr_offset.rt, rr_offset.rn, rr_offset.offset)),
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn mirLoadStackArgument(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const cond = emit.mir.instructions.items(.cond)[inst];
|
||||
const r_stack_offset = emit.mir.instructions.items(.data)[inst].r_stack_offset;
|
||||
const rt = r_stack_offset.rt;
|
||||
|
||||
const raw_offset = emit.stack_size + emit.saved_regs_stack_space + r_stack_offset.stack_offset;
|
||||
switch (tag) {
|
||||
.ldr_ptr_stack_argument => {
|
||||
const operand = Instruction.Operand.fromU32(raw_offset) orelse
|
||||
return emit.fail("TODO mirLoadStack larger offsets", .{});
|
||||
|
||||
try emit.writeInstruction(Instruction.add(cond, rt, .sp, operand));
|
||||
},
|
||||
.ldr_stack_argument,
|
||||
.ldrb_stack_argument,
|
||||
=> {
|
||||
const offset = if (raw_offset <= math.maxInt(u12)) blk: {
|
||||
break :blk Instruction.Offset.imm(@as(u12, @intCast(raw_offset)));
|
||||
} else return emit.fail("TODO mirLoadStack larger offsets", .{});
|
||||
|
||||
switch (tag) {
|
||||
.ldr_stack_argument => try emit.writeInstruction(Instruction.ldr(cond, rt, .sp, .{ .offset = offset })),
|
||||
.ldrb_stack_argument => try emit.writeInstruction(Instruction.ldrb(cond, rt, .sp, .{ .offset = offset })),
|
||||
else => unreachable,
|
||||
}
|
||||
},
|
||||
.ldrh_stack_argument,
|
||||
.ldrsb_stack_argument,
|
||||
.ldrsh_stack_argument,
|
||||
=> {
|
||||
const offset = if (raw_offset <= math.maxInt(u8)) blk: {
|
||||
break :blk Instruction.ExtraLoadStoreOffset.imm(@as(u8, @intCast(raw_offset)));
|
||||
} else return emit.fail("TODO mirLoadStack larger offsets", .{});
|
||||
|
||||
switch (tag) {
|
||||
.ldrh_stack_argument => try emit.writeInstruction(Instruction.ldrh(cond, rt, .sp, .{ .offset = offset })),
|
||||
.ldrsb_stack_argument => try emit.writeInstruction(Instruction.ldrsb(cond, rt, .sp, .{ .offset = offset })),
|
||||
.ldrsh_stack_argument => try emit.writeInstruction(Instruction.ldrsh(cond, rt, .sp, .{ .offset = offset })),
|
||||
else => unreachable,
|
||||
}
|
||||
},
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn mirLoadStoreExtra(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const cond = emit.mir.instructions.items(.cond)[inst];
|
||||
const rr_extra_offset = emit.mir.instructions.items(.data)[inst].rr_extra_offset;
|
||||
|
||||
switch (tag) {
|
||||
.ldrh => try emit.writeInstruction(Instruction.ldrh(cond, rr_extra_offset.rt, rr_extra_offset.rn, rr_extra_offset.offset)),
|
||||
.ldrsb => try emit.writeInstruction(Instruction.ldrsb(cond, rr_extra_offset.rt, rr_extra_offset.rn, rr_extra_offset.offset)),
|
||||
.ldrsh => try emit.writeInstruction(Instruction.ldrsh(cond, rr_extra_offset.rt, rr_extra_offset.rn, rr_extra_offset.offset)),
|
||||
.strh => try emit.writeInstruction(Instruction.strh(cond, rr_extra_offset.rt, rr_extra_offset.rn, rr_extra_offset.offset)),
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn mirSpecialMove(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const cond = emit.mir.instructions.items(.cond)[inst];
|
||||
const r_imm16 = emit.mir.instructions.items(.data)[inst].r_imm16;
|
||||
|
||||
switch (tag) {
|
||||
.movw => try emit.writeInstruction(Instruction.movw(cond, r_imm16.rd, r_imm16.imm16)),
|
||||
.movt => try emit.writeInstruction(Instruction.movt(cond, r_imm16.rd, r_imm16.imm16)),
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn mirMultiply(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const cond = emit.mir.instructions.items(.cond)[inst];
|
||||
const rrr = emit.mir.instructions.items(.data)[inst].rrr;
|
||||
|
||||
switch (tag) {
|
||||
.mul => try emit.writeInstruction(Instruction.mul(cond, rrr.rd, rrr.rn, rrr.rm)),
|
||||
.smulbb => try emit.writeInstruction(Instruction.smulbb(cond, rrr.rd, rrr.rn, rrr.rm)),
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn mirMultiplyLong(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const cond = emit.mir.instructions.items(.cond)[inst];
|
||||
const rrrr = emit.mir.instructions.items(.data)[inst].rrrr;
|
||||
|
||||
switch (tag) {
|
||||
.smull => try emit.writeInstruction(Instruction.smull(cond, rrrr.rdlo, rrrr.rdhi, rrrr.rn, rrrr.rm)),
|
||||
.umull => try emit.writeInstruction(Instruction.umull(cond, rrrr.rdlo, rrrr.rdhi, rrrr.rn, rrrr.rm)),
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn mirNop(emit: *Emit) !void {
|
||||
try emit.writeInstruction(Instruction.nop());
|
||||
}
|
||||
|
||||
fn mirBlockDataTransfer(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const cond = emit.mir.instructions.items(.cond)[inst];
|
||||
const register_list = emit.mir.instructions.items(.data)[inst].register_list;
|
||||
|
||||
switch (tag) {
|
||||
.pop => try emit.writeInstruction(Instruction.ldm(cond, .sp, true, register_list)),
|
||||
.push => try emit.writeInstruction(Instruction.stmdb(cond, .sp, true, register_list)),
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn mirSupervisorCall(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const cond = emit.mir.instructions.items(.cond)[inst];
|
||||
const imm24 = emit.mir.instructions.items(.data)[inst].imm24;
|
||||
|
||||
switch (tag) {
|
||||
.svc => try emit.writeInstruction(Instruction.svc(cond, imm24)),
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
||||
fn mirBitFieldExtract(emit: *Emit, inst: Mir.Inst.Index) !void {
|
||||
const tag = emit.mir.instructions.items(.tag)[inst];
|
||||
const cond = emit.mir.instructions.items(.cond)[inst];
|
||||
const rr_lsb_width = emit.mir.instructions.items(.data)[inst].rr_lsb_width;
|
||||
const rd = rr_lsb_width.rd;
|
||||
const rn = rr_lsb_width.rn;
|
||||
const lsb = rr_lsb_width.lsb;
|
||||
const width = rr_lsb_width.width;
|
||||
|
||||
switch (tag) {
|
||||
.sbfx => try emit.writeInstruction(Instruction.sbfx(cond, rd, rn, lsb, width)),
|
||||
.ubfx => try emit.writeInstruction(Instruction.ubfx(cond, rd, rn, lsb, width)),
|
||||
else => unreachable,
|
||||
}
|
||||
}
|
||||
|
|
@ -1,340 +0,0 @@
|
|||
//! Machine Intermediate Representation.
|
||||
//! This data is produced by ARM Codegen or ARM assembly parsing
|
||||
//! These instructions have a 1:1 correspondence with machine code instructions
|
||||
//! for the target. MIR can be lowered to source-annotated textual assembly code
|
||||
//! instructions, or it can be lowered to machine code.
|
||||
//! The main purpose of MIR is to postpone the assignment of offsets until Isel,
|
||||
//! so that, for example, the smaller encodings of jump instructions can be used.
|
||||
|
||||
const Mir = @This();
|
||||
const std = @import("std");
|
||||
const builtin = @import("builtin");
|
||||
const assert = std.debug.assert;
|
||||
|
||||
const bits = @import("bits.zig");
|
||||
const Register = bits.Register;
|
||||
const InternPool = @import("../../InternPool.zig");
|
||||
const Emit = @import("Emit.zig");
|
||||
const codegen = @import("../../codegen.zig");
|
||||
const link = @import("../../link.zig");
|
||||
const Zcu = @import("../../Zcu.zig");
|
||||
|
||||
max_end_stack: u32,
|
||||
saved_regs_stack_space: u32,
|
||||
|
||||
instructions: std.MultiArrayList(Inst).Slice,
|
||||
/// The meaning of this data is determined by `Inst.Tag` value.
|
||||
extra: []const u32,
|
||||
|
||||
pub const Inst = struct {
|
||||
tag: Tag,
|
||||
cond: bits.Condition = .al,
|
||||
/// The meaning of this depends on `tag`.
|
||||
data: Data,
|
||||
|
||||
pub const Tag = enum(u16) {
|
||||
/// Add
|
||||
add,
|
||||
/// Add, update condition flags
|
||||
adds,
|
||||
/// Bitwise AND
|
||||
@"and",
|
||||
/// Arithmetic Shift Right
|
||||
asr,
|
||||
/// Branch
|
||||
b,
|
||||
/// Undefined instruction
|
||||
undefined_instruction,
|
||||
/// Breakpoint
|
||||
bkpt,
|
||||
/// Branch with Link and Exchange
|
||||
blx,
|
||||
/// Branch and Exchange
|
||||
bx,
|
||||
/// Compare
|
||||
cmp,
|
||||
/// Pseudo-instruction: End of prologue
|
||||
dbg_prologue_end,
|
||||
/// Pseudo-instruction: Beginning of epilogue
|
||||
dbg_epilogue_begin,
|
||||
/// Pseudo-instruction: Update debug line
|
||||
dbg_line,
|
||||
/// Bitwise Exclusive OR
|
||||
eor,
|
||||
/// Load Register
|
||||
ldr,
|
||||
/// Pseudo-instruction: Load pointer to stack argument offset
|
||||
ldr_ptr_stack_argument,
|
||||
/// Load Register
|
||||
ldr_stack_argument,
|
||||
/// Load Register Byte
|
||||
ldrb,
|
||||
/// Load Register Byte
|
||||
ldrb_stack_argument,
|
||||
/// Load Register Halfword
|
||||
ldrh,
|
||||
/// Load Register Halfword
|
||||
ldrh_stack_argument,
|
||||
/// Load Register Signed Byte
|
||||
ldrsb,
|
||||
/// Load Register Signed Byte
|
||||
ldrsb_stack_argument,
|
||||
/// Load Register Signed Halfword
|
||||
ldrsh,
|
||||
/// Load Register Signed Halfword
|
||||
ldrsh_stack_argument,
|
||||
/// Logical Shift Left
|
||||
lsl,
|
||||
/// Logical Shift Right
|
||||
lsr,
|
||||
/// Move
|
||||
mov,
|
||||
/// Move
|
||||
movw,
|
||||
/// Move Top
|
||||
movt,
|
||||
/// Multiply
|
||||
mul,
|
||||
/// Bitwise NOT
|
||||
mvn,
|
||||
/// No Operation
|
||||
nop,
|
||||
/// Bitwise OR
|
||||
orr,
|
||||
/// Pop multiple registers from Stack
|
||||
pop,
|
||||
/// Push multiple registers to Stack
|
||||
push,
|
||||
/// Reverse Subtract
|
||||
rsb,
|
||||
/// Signed Bit Field Extract
|
||||
sbfx,
|
||||
/// Signed Multiply (halfwords), bottom half, bottom half
|
||||
smulbb,
|
||||
/// Signed Multiply Long
|
||||
smull,
|
||||
/// Store Register
|
||||
str,
|
||||
/// Store Register Byte
|
||||
strb,
|
||||
/// Store Register Halfword
|
||||
strh,
|
||||
/// Subtract
|
||||
sub,
|
||||
/// Pseudo-instruction: Subtract 32-bit immediate from stack
|
||||
///
|
||||
/// r4 can be used by Emit as a scratch register for loading
|
||||
/// the immediate
|
||||
sub_sp_scratch_r4,
|
||||
/// Subtract, update condition flags
|
||||
subs,
|
||||
/// Supervisor Call
|
||||
svc,
|
||||
/// Unsigned Bit Field Extract
|
||||
ubfx,
|
||||
/// Unsigned Multiply Long
|
||||
umull,
|
||||
};
|
||||
|
||||
/// The position of an MIR instruction within the `Mir` instructions array.
|
||||
pub const Index = u32;
|
||||
|
||||
/// All instructions have a 8-byte payload, which is contained within
|
||||
/// this union. `Tag` determines which union field is active, as well as
|
||||
/// how to interpret the data within.
|
||||
pub const Data = union {
|
||||
/// No additional data
|
||||
///
|
||||
/// Used by e.g. nop
|
||||
nop: void,
|
||||
/// Another instruction
|
||||
///
|
||||
/// Used by e.g. b
|
||||
inst: Index,
|
||||
/// A 16-bit immediate value.
|
||||
///
|
||||
/// Used by e.g. bkpt
|
||||
imm16: u16,
|
||||
/// A 24-bit immediate value.
|
||||
///
|
||||
/// Used by e.g. svc
|
||||
imm24: u24,
|
||||
/// A 32-bit immediate value.
|
||||
///
|
||||
/// Used by e.g. sub_sp_scratch_r0
|
||||
imm32: u32,
|
||||
/// Index into `extra`. Meaning of what can be found there is context-dependent.
|
||||
///
|
||||
/// Used by e.g. load_memory
|
||||
payload: u32,
|
||||
/// A register
|
||||
///
|
||||
/// Used by e.g. blx
|
||||
reg: Register,
|
||||
/// A register and a stack offset
|
||||
///
|
||||
/// Used by e.g. ldr_stack_argument
|
||||
r_stack_offset: struct {
|
||||
rt: Register,
|
||||
stack_offset: u32,
|
||||
},
|
||||
/// A register and a 16-bit unsigned immediate
|
||||
///
|
||||
/// Used by e.g. movw
|
||||
r_imm16: struct {
|
||||
rd: Register,
|
||||
imm16: u16,
|
||||
},
|
||||
/// A register and an operand
|
||||
///
|
||||
/// Used by mov and mvn
|
||||
r_op_mov: struct {
|
||||
rd: Register,
|
||||
op: bits.Instruction.Operand,
|
||||
},
|
||||
/// A register and an operand
|
||||
///
|
||||
/// Used by cmp
|
||||
r_op_cmp: struct {
|
||||
rn: Register,
|
||||
op: bits.Instruction.Operand,
|
||||
},
|
||||
/// Two registers and a shift amount
|
||||
///
|
||||
/// Used by e.g. lsl
|
||||
rr_shift: struct {
|
||||
rd: Register,
|
||||
rm: Register,
|
||||
shift_amount: bits.Instruction.ShiftAmount,
|
||||
},
|
||||
/// Two registers and an operand
|
||||
///
|
||||
/// Used by e.g. sub
|
||||
rr_op: struct {
|
||||
rd: Register,
|
||||
rn: Register,
|
||||
op: bits.Instruction.Operand,
|
||||
},
|
||||
/// Two registers and an offset
|
||||
///
|
||||
/// Used by e.g. ldr
|
||||
rr_offset: struct {
|
||||
rt: Register,
|
||||
rn: Register,
|
||||
offset: bits.Instruction.OffsetArgs,
|
||||
},
|
||||
/// Two registers and an extra load/store offset
|
||||
///
|
||||
/// Used by e.g. ldrh
|
||||
rr_extra_offset: struct {
|
||||
rt: Register,
|
||||
rn: Register,
|
||||
offset: bits.Instruction.ExtraLoadStoreOffsetArgs,
|
||||
},
|
||||
/// Two registers and a lsb (range 0-31) and a width (range
|
||||
/// 1-32)
|
||||
///
|
||||
/// Used by e.g. sbfx
|
||||
rr_lsb_width: struct {
|
||||
rd: Register,
|
||||
rn: Register,
|
||||
lsb: u5,
|
||||
width: u6,
|
||||
},
|
||||
/// Three registers
|
||||
///
|
||||
/// Used by e.g. mul
|
||||
rrr: struct {
|
||||
rd: Register,
|
||||
rn: Register,
|
||||
rm: Register,
|
||||
},
|
||||
/// Four registers
|
||||
///
|
||||
/// Used by e.g. smull
|
||||
rrrr: struct {
|
||||
rdlo: Register,
|
||||
rdhi: Register,
|
||||
rn: Register,
|
||||
rm: Register,
|
||||
},
|
||||
/// An unordered list of registers
|
||||
///
|
||||
/// Used by e.g. push
|
||||
register_list: bits.Instruction.RegisterList,
|
||||
/// Debug info: line and column
|
||||
///
|
||||
/// Used by e.g. dbg_line
|
||||
dbg_line_column: struct {
|
||||
line: u32,
|
||||
column: u32,
|
||||
},
|
||||
};
|
||||
|
||||
// Make sure we don't accidentally make instructions bigger than expected.
|
||||
// Note that in safety builds, Zig is allowed to insert a secret field for safety checks.
|
||||
comptime {
|
||||
if (!std.debug.runtime_safety) {
|
||||
assert(@sizeOf(Data) == 8);
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
pub fn deinit(mir: *Mir, gpa: std.mem.Allocator) void {
|
||||
mir.instructions.deinit(gpa);
|
||||
gpa.free(mir.extra);
|
||||
mir.* = undefined;
|
||||
}
|
||||
|
||||
pub fn emit(
|
||||
mir: Mir,
|
||||
lf: *link.File,
|
||||
pt: Zcu.PerThread,
|
||||
src_loc: Zcu.LazySrcLoc,
|
||||
func_index: InternPool.Index,
|
||||
code: *std.ArrayListUnmanaged(u8),
|
||||
debug_output: link.File.DebugInfoOutput,
|
||||
) codegen.CodeGenError!void {
|
||||
const zcu = pt.zcu;
|
||||
const func = zcu.funcInfo(func_index);
|
||||
const nav = func.owner_nav;
|
||||
const mod = zcu.navFileScope(nav).mod.?;
|
||||
var e: Emit = .{
|
||||
.mir = mir,
|
||||
.bin_file = lf,
|
||||
.debug_output = debug_output,
|
||||
.target = &mod.resolved_target.result,
|
||||
.src_loc = src_loc,
|
||||
.code = code,
|
||||
.prev_di_pc = 0,
|
||||
.prev_di_line = func.lbrace_line,
|
||||
.prev_di_column = func.lbrace_column,
|
||||
.stack_size = mir.max_end_stack,
|
||||
.saved_regs_stack_space = mir.saved_regs_stack_space,
|
||||
};
|
||||
defer e.deinit();
|
||||
e.emitMir() catch |err| switch (err) {
|
||||
error.EmitFail => return zcu.codegenFailMsg(nav, e.err_msg.?),
|
||||
else => |e1| return e1,
|
||||
};
|
||||
}
|
||||
|
||||
/// Returns the requested data, as well as the new index which is at the start of the
|
||||
/// trailers for the object.
|
||||
pub fn extraData(mir: Mir, comptime T: type, index: usize) struct { data: T, end: usize } {
|
||||
const fields = std.meta.fields(T);
|
||||
var i: usize = index;
|
||||
var result: T = undefined;
|
||||
inline for (fields) |field| {
|
||||
@field(result, field.name) = switch (field.type) {
|
||||
u32 => mir.extra[i],
|
||||
i32 => @as(i32, @bitCast(mir.extra[i])),
|
||||
else => @compileError("bad field type"),
|
||||
};
|
||||
i += 1;
|
||||
}
|
||||
return .{
|
||||
.data = result,
|
||||
.end = i,
|
||||
};
|
||||
}
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -49,7 +49,7 @@ fn importBackend(comptime backend: std.builtin.CompilerBackend) type {
|
|||
return switch (backend) {
|
||||
.other, .stage1 => unreachable,
|
||||
.stage2_aarch64 => unreachable,
|
||||
.stage2_arm => @import("arch/arm/CodeGen.zig"),
|
||||
.stage2_arm => unreachable,
|
||||
.stage2_c => @import("codegen/c.zig"),
|
||||
.stage2_llvm => @import("codegen/llvm.zig"),
|
||||
.stage2_powerpc => unreachable,
|
||||
|
|
@ -70,7 +70,6 @@ pub fn legalizeFeatures(pt: Zcu.PerThread, nav_index: InternPool.Nav.Index) ?*co
|
|||
inline .stage2_llvm,
|
||||
.stage2_c,
|
||||
.stage2_wasm,
|
||||
.stage2_arm,
|
||||
.stage2_x86_64,
|
||||
.stage2_x86,
|
||||
.stage2_riscv64,
|
||||
|
|
@ -87,7 +86,6 @@ pub fn legalizeFeatures(pt: Zcu.PerThread, nav_index: InternPool.Nav.Index) ?*co
|
|||
/// MIR from codegen to the linker *regardless* of which backend is in use. So, we use this: a
|
||||
/// union of all MIR types. The active tag is known from the backend in use; see `AnyMir.tag`.
|
||||
pub const AnyMir = union {
|
||||
arm: @import("arch/arm/Mir.zig"),
|
||||
riscv64: @import("arch/riscv64/Mir.zig"),
|
||||
sparc64: @import("arch/sparc64/Mir.zig"),
|
||||
x86_64: @import("arch/x86_64/Mir.zig"),
|
||||
|
|
@ -112,8 +110,7 @@ pub const AnyMir = union {
|
|||
const backend = target_util.zigBackend(&zcu.root_mod.resolved_target.result, zcu.comp.config.use_llvm);
|
||||
switch (backend) {
|
||||
else => unreachable,
|
||||
inline .stage2_arm,
|
||||
.stage2_riscv64,
|
||||
inline .stage2_riscv64,
|
||||
.stage2_sparc64,
|
||||
.stage2_x86_64,
|
||||
.stage2_wasm,
|
||||
|
|
@ -141,8 +138,7 @@ pub fn generateFunction(
|
|||
const target = &zcu.navFileScope(func.owner_nav).mod.?.resolved_target.result;
|
||||
switch (target_util.zigBackend(target, false)) {
|
||||
else => unreachable,
|
||||
inline .stage2_arm,
|
||||
.stage2_riscv64,
|
||||
inline .stage2_riscv64,
|
||||
.stage2_sparc64,
|
||||
.stage2_x86_64,
|
||||
.stage2_wasm,
|
||||
|
|
@ -177,8 +173,7 @@ pub fn emitFunction(
|
|||
const target = &zcu.navFileScope(func.owner_nav).mod.?.resolved_target.result;
|
||||
switch (target_util.zigBackend(target, zcu.comp.config.use_llvm)) {
|
||||
else => unreachable,
|
||||
inline .stage2_arm,
|
||||
.stage2_riscv64,
|
||||
inline .stage2_riscv64,
|
||||
.stage2_sparc64,
|
||||
.stage2_x86_64,
|
||||
=> |backend| {
|
||||
|
|
|
|||
|
|
@ -1,7 +1,5 @@
|
|||
const std = @import("std");
|
||||
const assert = std.debug.assert;
|
||||
const bits = @import("bits.zig");
|
||||
const Register = bits.Register;
|
||||
const RegisterManagerFn = @import("../../register_manager.zig").RegisterManager;
|
||||
const Type = @import("../../Type.zig");
|
||||
const Zcu = @import("../../Zcu.zig");
|
||||
|
|
@ -163,25 +161,3 @@ fn countFloats(ty: Type, zcu: *Zcu, maybe_float_bits: *?u16) u32 {
|
|||
else => return invalid,
|
||||
}
|
||||
}
|
||||
|
||||
pub const callee_preserved_regs = [_]Register{ .r4, .r5, .r6, .r7, .r8, .r10 };
|
||||
pub const caller_preserved_regs = [_]Register{ .r0, .r1, .r2, .r3 };
|
||||
|
||||
pub const c_abi_int_param_regs = [_]Register{ .r0, .r1, .r2, .r3 };
|
||||
pub const c_abi_int_return_regs = [_]Register{ .r0, .r1 };
|
||||
|
||||
const allocatable_registers = callee_preserved_regs ++ caller_preserved_regs;
|
||||
pub const RegisterManager = RegisterManagerFn(@import("CodeGen.zig"), Register, &allocatable_registers);
|
||||
|
||||
// Register classes
|
||||
const RegisterBitSet = RegisterManager.RegisterBitSet;
|
||||
pub const RegisterClass = struct {
|
||||
pub const gp: RegisterBitSet = blk: {
|
||||
var set = RegisterBitSet.initEmpty();
|
||||
set.setRangeValue(.{
|
||||
.start = 0,
|
||||
.end = caller_preserved_regs.len + callee_preserved_regs.len,
|
||||
}, true);
|
||||
break :blk set;
|
||||
};
|
||||
};
|
||||
|
|
@ -23,7 +23,7 @@ const Type = @import("../Type.zig");
|
|||
const x86_64_abi = @import("../arch/x86_64/abi.zig");
|
||||
const wasm_c_abi = @import("../arch/wasm/abi.zig");
|
||||
const aarch64_c_abi = @import("aarch64/abi.zig");
|
||||
const arm_c_abi = @import("../arch/arm/abi.zig");
|
||||
const arm_c_abi = @import("arm/abi.zig");
|
||||
const riscv_c_abi = @import("../arch/riscv64/abi.zig");
|
||||
const mips_c_abi = @import("../arch/mips/abi.zig");
|
||||
const dev = @import("../dev.zig");
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue