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Merge pull request #22529 from xtexx/x86-64/shl-sat-int
x86_64: Implement integer saturating left shifting codegen
This commit is contained in:
Jacob Young
GitHub
commit
a6525c1762
2 changed files with 184 additions and 6 deletions
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@ -85078,10 +85078,132 @@ fn airShlShrBinOp(self: *CodeGen, inst: Air.Inst.Index) !void {
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}
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fn airShlSat(self: *CodeGen, inst: Air.Inst.Index) !void {
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const zcu = self.pt.zcu;
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const bin_op = self.air.instructions.items(.data)[@intFromEnum(inst)].bin_op;
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_ = bin_op;
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return self.fail("TODO implement shl_sat for {}", .{self.target.cpu.arch});
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//return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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const lhs_ty = self.typeOf(bin_op.lhs);
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const rhs_ty = self.typeOf(bin_op.rhs);
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const result: MCValue = result: {
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switch (lhs_ty.zigTypeTag(zcu)) {
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.int => {
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const lhs_bits = lhs_ty.bitSize(zcu);
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const rhs_bits = rhs_ty.bitSize(zcu);
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if (!(lhs_bits <= 32 and rhs_bits <= 5) and !(lhs_bits > 32 and lhs_bits <= 64 and rhs_bits <= 6) and !(rhs_bits <= std.math.log2(lhs_bits))) {
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return self.fail("TODO implement shl_sat for {} with lhs bits {}, rhs bits {}", .{ self.target.cpu.arch, lhs_bits, rhs_bits });
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}
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// clobberred by genShiftBinOp
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try self.spillRegisters(&.{.rcx});
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const lhs_mcv = try self.resolveInst(bin_op.lhs);
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var lhs_temp1 = try self.tempInit(lhs_ty, lhs_mcv);
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const rhs_mcv = try self.resolveInst(bin_op.rhs);
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const lhs_lock = switch (lhs_mcv) {
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.register => |reg| self.register_manager.lockRegAssumeUnused(reg),
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else => null,
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};
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defer if (lhs_lock) |lock| self.register_manager.unlockReg(lock);
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// shift left
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const dst_mcv = try self.genShiftBinOp(.shl, null, lhs_mcv, rhs_mcv, lhs_ty, rhs_ty);
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switch (dst_mcv) {
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.register => |dst_reg| try self.truncateRegister(lhs_ty, dst_reg),
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.register_pair => |dst_regs| try self.truncateRegister(lhs_ty, dst_regs[1]),
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.load_frame => |frame_addr| {
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const tmp_reg =
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try self.register_manager.allocReg(null, abi.RegisterClass.gp);
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const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
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defer self.register_manager.unlockReg(tmp_lock);
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const lhs_bits_u31: u31 = @intCast(lhs_bits);
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const tmp_ty: Type = if (lhs_bits_u31 > 64) .usize else lhs_ty;
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const off = frame_addr.off + (lhs_bits_u31 - 1) / 64 * 8;
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try self.genSetReg(
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tmp_reg,
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tmp_ty,
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.{ .load_frame = .{ .index = frame_addr.index, .off = off } },
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.{},
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);
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try self.truncateRegister(lhs_ty, tmp_reg);
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try self.genSetMem(
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.{ .frame = frame_addr.index },
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off,
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tmp_ty,
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.{ .register = tmp_reg },
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.{},
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);
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},
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else => {},
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}
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const dst_lock = switch (dst_mcv) {
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.register => |reg| self.register_manager.lockRegAssumeUnused(reg),
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else => null,
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};
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defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
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// shift right
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const tmp_mcv = try self.genShiftBinOp(.shr, null, dst_mcv, rhs_mcv, lhs_ty, rhs_ty);
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var tmp_temp = try self.tempInit(lhs_ty, tmp_mcv);
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// check if overflow happens
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const cc_temp = lhs_temp1.cmpInts(.neq, &tmp_temp, self) catch |err| switch (err) {
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error.SelectFailed => unreachable,
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else => |e| return e,
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};
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try lhs_temp1.die(self);
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try tmp_temp.die(self);
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const overflow_reloc = try self.genCondBrMir(lhs_ty, cc_temp.tracking(self).short);
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try cc_temp.die(self);
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// if overflow,
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// for unsigned integers, the saturating result is just its max
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// for signed integers,
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// if lhs is positive, the result is its max
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// if lhs is negative, it is min
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switch (lhs_ty.intInfo(zcu).signedness) {
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.unsigned => {
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const bound_mcv = try self.genTypedValue(try lhs_ty.maxIntScalar(self.pt, lhs_ty));
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try self.genCopy(lhs_ty, dst_mcv, bound_mcv, .{});
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},
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.signed => {
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// check the sign of lhs
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// TODO: optimize this.
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// we only need the highest bit so shifting the highest part of lhs_mcv
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// is enough to check the signedness. other parts can be skipped here.
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var lhs_temp2 = try self.tempInit(lhs_ty, lhs_mcv);
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var zero_temp = try self.tempInit(lhs_ty, try self.genTypedValue(try self.pt.intValue(lhs_ty, 0)));
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const sign_cc_temp = lhs_temp2.cmpInts(.lt, &zero_temp, self) catch |err| switch (err) {
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error.SelectFailed => unreachable,
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else => |e| return e,
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};
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try lhs_temp2.die(self);
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try zero_temp.die(self);
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const sign_reloc_condbr = try self.genCondBrMir(lhs_ty, sign_cc_temp.tracking(self).short);
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try sign_cc_temp.die(self);
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// if it is negative
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const min_mcv = try self.genTypedValue(try lhs_ty.minIntScalar(self.pt, lhs_ty));
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try self.genCopy(lhs_ty, dst_mcv, min_mcv, .{});
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const sign_reloc_br = try self.asmJmpReloc(undefined);
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self.performReloc(sign_reloc_condbr);
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// if it is positive
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const max_mcv = try self.genTypedValue(try lhs_ty.maxIntScalar(self.pt, lhs_ty));
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try self.genCopy(lhs_ty, dst_mcv, max_mcv, .{});
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self.performReloc(sign_reloc_br);
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},
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}
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self.performReloc(overflow_reloc);
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break :result dst_mcv;
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},
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else => {
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return self.fail("TODO implement shl_sat for {} op type {}", .{ self.target.cpu.arch, lhs_ty.zigTypeTag(zcu) });
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},
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}
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};
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return self.finishAir(inst, result, .{ bin_op.lhs, bin_op.rhs, .none });
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}
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fn airOptionalPayload(self: *CodeGen, inst: Air.Inst.Index) !void {
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@ -88466,7 +88588,7 @@ fn genShiftBinOpMir(
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) !void {
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const pt = self.pt;
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const zcu = pt.zcu;
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const abi_size: u32 = @intCast(lhs_ty.abiSize(zcu));
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const abi_size: u31 = @intCast(lhs_ty.abiSize(zcu));
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const shift_abi_size: u32 = @intCast(rhs_ty.abiSize(zcu));
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try self.spillEflagsIfOccupied();
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@ -88650,7 +88772,17 @@ fn genShiftBinOpMir(
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.immediate => {},
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else => self.performReloc(skip),
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}
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}
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} else try self.asmRegisterMemory(.{ ._, .mov }, temp_regs[2].to64(), .{
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.base = .{ .frame = lhs_mcv.load_frame.index },
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.mod = .{ .rm = .{
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.size = .qword,
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.disp = switch (tag[0]) {
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._l => lhs_mcv.load_frame.off,
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._r => lhs_mcv.load_frame.off + abi_size - 8,
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else => unreachable,
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},
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} },
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});
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switch (rhs_mcv) {
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.immediate => |shift_imm| try self.asmRegisterImmediate(
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tag,
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@ -1,5 +1,6 @@
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const std = @import("std");
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const expect = std.testing.expect;
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const expectEqual = std.testing.expectEqual;
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const builtin = @import("builtin");
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fn ShardedTable(comptime Key: type, comptime mask_bit_count: comptime_int, comptime V: type) type {
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@ -111,7 +112,6 @@ test "comptime shift safety check" {
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}
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test "Saturating Shift Left where lhs is of a computed type" {
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if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
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if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
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@ -159,3 +159,49 @@ comptime {
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_ = ℑ
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_ = @shlExact(@as(u16, image[0]), 8);
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}
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test "Saturating Shift Left" {
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if (builtin.zig_backend == .stage2_c) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest;
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if (builtin.zig_backend == .stage2_x86_64 and builtin.target.ofmt != .elf and builtin.target.ofmt != .macho) return error.SkipZigTest;
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const S = struct {
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fn shlSat(x: anytype, y: std.math.Log2Int(@TypeOf(x))) @TypeOf(x) {
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// workaround https://github.com/ziglang/zig/issues/23033
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@setRuntimeSafety(false);
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return x <<| y;
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}
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fn testType(comptime T: type) !void {
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comptime var rhs: std.math.Log2Int(T) = 0;
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inline while (true) : (rhs += 1) {
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comptime var lhs: T = std.math.minInt(T);
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inline while (true) : (lhs += 1) {
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try expectEqual(lhs <<| rhs, shlSat(lhs, rhs));
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if (lhs == std.math.maxInt(T)) break;
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}
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if (rhs == @bitSizeOf(T) - 1) break;
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}
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}
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};
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try S.testType(u2);
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try S.testType(i2);
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try S.testType(u3);
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try S.testType(i3);
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try S.testType(u4);
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try S.testType(i4);
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try expectEqual(0xfffffffffffffff0fffffffffffffff0, S.shlSat(@as(u128, 0x0fffffffffffffff0fffffffffffffff), 4));
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try expectEqual(0xffffffffffffffffffffffffffffffff, S.shlSat(@as(u128, 0x0fffffffffffffff0fffffffffffffff), 5));
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try expectEqual(-0x80000000000000000000000000000000, S.shlSat(@as(i128, -0x0fffffffffffffff0fffffffffffffff), 5));
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// TODO
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// try expectEqual(51146728248377216718956089012931236753385031969422887335676427626502090568823039920051095192592252455482604439493126109519019633529459266458258243583, S.shlSat(@as(i495, 0x2fe6bc5448c55ce18252e2c9d44777505dfe63ff249a8027a6626c7d8dd9893fd5731e51474727be556f757facb586a4e04bbc0148c6c7ad692302f46fbd), 0x31));
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try expectEqual(-57896044618658097711785492504343953926634992332820282019728792003956564819968, S.shlSat(@as(i256, -0x53d4148cee74ea43477a65b3daa7b8fdadcbf4508e793f4af113b8d8da5a7eb6), 0x91));
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try expectEqual(170141183460469231731687303715884105727, S.shlSat(@as(i128, 0x2fe6bc5448c55ce18252e2c9d4477750), 0x31));
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try expectEqual(0, S.shlSat(@as(i128, 0), 127));
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}
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