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compiler_rt: add outlined lse atomics for aarch64
This commit is contained in:
Devin Singh
Andrew Kelley
parent
7c527c6dfe
commit
a8f2d00ec4
3 changed files with 11030 additions and 0 deletions
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@ -2,6 +2,7 @@ pub const panic = @import("compiler_rt/common.zig").panic;
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comptime {
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_ = @import("compiler_rt/atomics.zig");
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_ = @import("compiler_rt/lse_atomics.zig");
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_ = @import("compiler_rt/addf3.zig");
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_ = @import("compiler_rt/addhf3.zig");
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10435
lib/compiler_rt/lse_atomics.zig
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10435
lib/compiler_rt/lse_atomics.zig
Normal file
File diff suppressed because it is too large
Load diff
594
tools/gen_outline_atomics.zig
Normal file
594
tools/gen_outline_atomics.zig
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@ -0,0 +1,594 @@
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const std = @import("std");
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const Allocator = std.mem.Allocator;
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const AtomicOp = enum {
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cas,
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swp,
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ldadd,
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ldclr,
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ldeor,
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ldset,
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};
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pub fn main() !void {
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var gpa = std.heap.GeneralPurposeAllocator(.{}){};
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defer std.debug.assert(!gpa.deinit());
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var allocator = gpa.allocator();
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const args = try std.process.argsAlloc(allocator);
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defer std.process.argsFree(allocator, args);
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if (args.len != 2) {
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usageAndExit(std.io.getStdErr(), args[0], 1);
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}
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var file = try std.fs.cwd().createFile(args[1], .{ .truncate = true });
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try file.writeAll(
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\\const std = @import("std");
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\\const builtin = @import("builtin");
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\\const arch = builtin.cpu.arch;
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\\const is_test = builtin.is_test;
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\\const target = std.Target;
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\\const os_tag = builtin.os.tag;
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\\const is_darwin = target.Os.Tag.isDarwin(os_tag);
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\\const has_lse = target.aarch64.featureSetHas(builtin.target.cpu.features, .lse);
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\\const linkage = if (is_test)
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\\ std.builtin.GlobalLinkage.Internal
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\\else
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\\ std.builtin.GlobalLinkage.Strong;
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\\
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\\
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);
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for ([_]N{ .one, .two, .four, .eight, .sixteen }) |n| {
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for ([_]Ordering{ .relax, .acq, .rel, .acq_rel }) |order| {
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for ([_]AtomicOp{ .cas, .swp, .ldadd, .ldclr, .ldeor, .ldset }) |pat| {
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if (pat == .cas or n != .sixteen) {
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for ([_]bool{ true, false }) |darwin| {
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for ([_]bool{ true, false }) |lse| {
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const darwin_name = if (darwin) "Darwin" else "Nondarwin";
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const lse_name = if (lse) "Lse" else "Nolse";
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var buf: [100:0]u8 = undefined;
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const name = try std.fmt.bufPrintZ(&buf, "{s}{s}{s}{s}{s}", .{ @tagName(pat), n.toBytes(), order.capName(), darwin_name, lse_name });
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const body = switch (pat) {
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.cas => try generateCas(&allocator, n, order, lse),
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.swp => try generateSwp(&allocator, n, order, lse),
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.ldadd => try generateLd(&allocator, n, order, .ldadd, lse),
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.ldclr => try generateLd(&allocator, n, order, .ldclr, lse),
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.ldeor => try generateLd(&allocator, n, order, .ldeor, lse),
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.ldset => try generateLd(&allocator, n, order, .ldset, lse),
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};
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defer allocator.destroy(body.ptr);
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try writeFunction(&file, name, pat, n, body);
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}
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}
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try writeExport(&file, @tagName(pat), n.toBytes(), order);
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}
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}
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}
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}
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try file.writeAll(
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\\//TODO: Add linksection once implemented and remove init at writeFunction
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\\fn __init_aarch64_have_lse_atomics() callconv(.C) void {
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\\ const AT_HWCAP = 16;
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\\ const HWCAP_ATOMICS = 1 << 8;
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\\ const hwcap = std.os.linux.getauxval(AT_HWCAP);
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\\ __aarch64_have_lse_atomics = @boolToInt((hwcap & HWCAP_ATOMICS) != 0);
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\\}
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\\
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\\var __aarch64_have_lse_atomics: u8 = @boolToInt(has_lse);
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\\
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\\comptime {
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\\ if (arch.isAARCH64()) {
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\\ @export(__aarch64_cas1_relax, .{ .name = "__aarch64_cas1_relax", .linkage = linkage });
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\\ @export(__aarch64_cas1_acq, .{ .name = "__aarch64_cas1_acq", .linkage = linkage });
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\\ @export(__aarch64_cas1_rel, .{ .name = "__aarch64_cas1_rel", .linkage = linkage });
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\\ @export(__aarch64_cas1_acq_rel, .{ .name = "__aarch64_cas1_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_cas2_relax, .{ .name = "__aarch64_cas2_relax", .linkage = linkage });
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\\ @export(__aarch64_cas2_acq, .{ .name = "__aarch64_cas2_acq", .linkage = linkage });
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\\ @export(__aarch64_cas2_rel, .{ .name = "__aarch64_cas2_rel", .linkage = linkage });
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\\ @export(__aarch64_cas2_acq_rel, .{ .name = "__aarch64_cas2_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_cas4_relax, .{ .name = "__aarch64_cas4_relax", .linkage = linkage });
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\\ @export(__aarch64_cas4_acq, .{ .name = "__aarch64_cas4_acq", .linkage = linkage });
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\\ @export(__aarch64_cas4_rel, .{ .name = "__aarch64_cas4_rel", .linkage = linkage });
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\\ @export(__aarch64_cas4_acq_rel, .{ .name = "__aarch64_cas4_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_cas8_relax, .{ .name = "__aarch64_cas8_relax", .linkage = linkage });
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\\ @export(__aarch64_cas8_acq, .{ .name = "__aarch64_cas8_acq", .linkage = linkage });
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\\ @export(__aarch64_cas8_rel, .{ .name = "__aarch64_cas8_rel", .linkage = linkage });
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\\ @export(__aarch64_cas8_acq_rel, .{ .name = "__aarch64_cas8_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_cas16_relax, .{ .name = "__aarch64_cas16_relax", .linkage = linkage });
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\\ @export(__aarch64_cas16_acq, .{ .name = "__aarch64_cas16_acq", .linkage = linkage });
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\\ @export(__aarch64_cas16_rel, .{ .name = "__aarch64_cas16_rel", .linkage = linkage });
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\\ @export(__aarch64_cas16_acq_rel, .{ .name = "__aarch64_cas16_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_swp1_relax, .{ .name = "__aarch64_swp1_relax", .linkage = linkage });
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\\ @export(__aarch64_swp1_acq, .{ .name = "__aarch64_swp1_acq", .linkage = linkage });
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\\ @export(__aarch64_swp1_rel, .{ .name = "__aarch64_swp1_rel", .linkage = linkage });
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\\ @export(__aarch64_swp1_acq_rel, .{ .name = "__aarch64_swp1_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_swp2_relax, .{ .name = "__aarch64_swp2_relax", .linkage = linkage });
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\\ @export(__aarch64_swp2_acq, .{ .name = "__aarch64_swp2_acq", .linkage = linkage });
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\\ @export(__aarch64_swp2_rel, .{ .name = "__aarch64_swp2_rel", .linkage = linkage });
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\\ @export(__aarch64_swp2_acq_rel, .{ .name = "__aarch64_swp2_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_swp4_relax, .{ .name = "__aarch64_swp4_relax", .linkage = linkage });
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\\ @export(__aarch64_swp4_acq, .{ .name = "__aarch64_swp4_acq", .linkage = linkage });
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\\ @export(__aarch64_swp4_rel, .{ .name = "__aarch64_swp4_rel", .linkage = linkage });
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\\ @export(__aarch64_swp4_acq_rel, .{ .name = "__aarch64_swp4_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_swp8_relax, .{ .name = "__aarch64_swp8_relax", .linkage = linkage });
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\\ @export(__aarch64_swp8_acq, .{ .name = "__aarch64_swp8_acq", .linkage = linkage });
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\\ @export(__aarch64_swp8_rel, .{ .name = "__aarch64_swp8_rel", .linkage = linkage });
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\\ @export(__aarch64_swp8_acq_rel, .{ .name = "__aarch64_swp8_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_ldadd1_relax, .{ .name = "__aarch64_ldadd1_relax", .linkage = linkage });
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\\ @export(__aarch64_ldadd1_acq, .{ .name = "__aarch64_ldadd1_acq", .linkage = linkage });
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\\ @export(__aarch64_ldadd1_rel, .{ .name = "__aarch64_ldadd1_rel", .linkage = linkage });
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\\ @export(__aarch64_ldadd1_acq_rel, .{ .name = "__aarch64_ldadd1_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_ldadd2_relax, .{ .name = "__aarch64_ldadd2_relax", .linkage = linkage });
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\\ @export(__aarch64_ldadd2_acq, .{ .name = "__aarch64_ldadd2_acq", .linkage = linkage });
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\\ @export(__aarch64_ldadd2_rel, .{ .name = "__aarch64_ldadd2_rel", .linkage = linkage });
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\\ @export(__aarch64_ldadd2_acq_rel, .{ .name = "__aarch64_ldadd2_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_ldadd4_relax, .{ .name = "__aarch64_ldadd4_relax", .linkage = linkage });
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\\ @export(__aarch64_ldadd4_acq, .{ .name = "__aarch64_ldadd4_acq", .linkage = linkage });
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\\ @export(__aarch64_ldadd4_rel, .{ .name = "__aarch64_ldadd4_rel", .linkage = linkage });
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\\ @export(__aarch64_ldadd4_acq_rel, .{ .name = "__aarch64_ldadd4_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_ldadd8_relax, .{ .name = "__aarch64_ldadd8_relax", .linkage = linkage });
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\\ @export(__aarch64_ldadd8_acq, .{ .name = "__aarch64_ldadd8_acq", .linkage = linkage });
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\\ @export(__aarch64_ldadd8_rel, .{ .name = "__aarch64_ldadd8_rel", .linkage = linkage });
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\\ @export(__aarch64_ldadd8_acq_rel, .{ .name = "__aarch64_ldadd8_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_ldclr1_relax, .{ .name = "__aarch64_ldclr1_relax", .linkage = linkage });
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\\ @export(__aarch64_ldclr1_acq, .{ .name = "__aarch64_ldclr1_acq", .linkage = linkage });
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\\ @export(__aarch64_ldclr1_rel, .{ .name = "__aarch64_ldclr1_rel", .linkage = linkage });
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\\ @export(__aarch64_ldclr1_acq_rel, .{ .name = "__aarch64_ldclr1_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_ldclr2_relax, .{ .name = "__aarch64_ldclr2_relax", .linkage = linkage });
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\\ @export(__aarch64_ldclr2_acq, .{ .name = "__aarch64_ldclr2_acq", .linkage = linkage });
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\\ @export(__aarch64_ldclr2_rel, .{ .name = "__aarch64_ldclr2_rel", .linkage = linkage });
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\\ @export(__aarch64_ldclr2_acq_rel, .{ .name = "__aarch64_ldclr2_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_ldclr4_relax, .{ .name = "__aarch64_ldclr4_relax", .linkage = linkage });
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\\ @export(__aarch64_ldclr4_acq, .{ .name = "__aarch64_ldclr4_acq", .linkage = linkage });
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\\ @export(__aarch64_ldclr4_rel, .{ .name = "__aarch64_ldclr4_rel", .linkage = linkage });
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\\ @export(__aarch64_ldclr4_acq_rel, .{ .name = "__aarch64_ldclr4_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_ldclr8_relax, .{ .name = "__aarch64_ldclr8_relax", .linkage = linkage });
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\\ @export(__aarch64_ldclr8_acq, .{ .name = "__aarch64_ldclr8_acq", .linkage = linkage });
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\\ @export(__aarch64_ldclr8_rel, .{ .name = "__aarch64_ldclr8_rel", .linkage = linkage });
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\\ @export(__aarch64_ldclr8_acq_rel, .{ .name = "__aarch64_ldclr8_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_ldeor1_relax, .{ .name = "__aarch64_ldeor1_relax", .linkage = linkage });
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\\ @export(__aarch64_ldeor1_acq, .{ .name = "__aarch64_ldeor1_acq", .linkage = linkage });
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\\ @export(__aarch64_ldeor1_rel, .{ .name = "__aarch64_ldeor1_rel", .linkage = linkage });
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\\ @export(__aarch64_ldeor1_acq_rel, .{ .name = "__aarch64_ldeor1_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_ldeor2_relax, .{ .name = "__aarch64_ldeor2_relax", .linkage = linkage });
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\\ @export(__aarch64_ldeor2_acq, .{ .name = "__aarch64_ldeor2_acq", .linkage = linkage });
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\\ @export(__aarch64_ldeor2_rel, .{ .name = "__aarch64_ldeor2_rel", .linkage = linkage });
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\\ @export(__aarch64_ldeor2_acq_rel, .{ .name = "__aarch64_ldeor2_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_ldeor4_relax, .{ .name = "__aarch64_ldeor4_relax", .linkage = linkage });
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\\ @export(__aarch64_ldeor4_acq, .{ .name = "__aarch64_ldeor4_acq", .linkage = linkage });
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\\ @export(__aarch64_ldeor4_rel, .{ .name = "__aarch64_ldeor4_rel", .linkage = linkage });
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\\ @export(__aarch64_ldeor4_acq_rel, .{ .name = "__aarch64_ldeor4_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_ldeor8_relax, .{ .name = "__aarch64_ldeor8_relax", .linkage = linkage });
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\\ @export(__aarch64_ldeor8_acq, .{ .name = "__aarch64_ldeor8_acq", .linkage = linkage });
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\\ @export(__aarch64_ldeor8_rel, .{ .name = "__aarch64_ldeor8_rel", .linkage = linkage });
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\\ @export(__aarch64_ldeor8_acq_rel, .{ .name = "__aarch64_ldeor8_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_ldset1_relax, .{ .name = "__aarch64_ldset1_relax", .linkage = linkage });
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\\ @export(__aarch64_ldset1_acq, .{ .name = "__aarch64_ldset1_acq", .linkage = linkage });
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\\ @export(__aarch64_ldset1_rel, .{ .name = "__aarch64_ldset1_rel", .linkage = linkage });
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\\ @export(__aarch64_ldset1_acq_rel, .{ .name = "__aarch64_ldset1_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_ldset2_relax, .{ .name = "__aarch64_ldset2_relax", .linkage = linkage });
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\\ @export(__aarch64_ldset2_acq, .{ .name = "__aarch64_ldset2_acq", .linkage = linkage });
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\\ @export(__aarch64_ldset2_rel, .{ .name = "__aarch64_ldset2_rel", .linkage = linkage });
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\\ @export(__aarch64_ldset2_acq_rel, .{ .name = "__aarch64_ldset2_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_ldset4_relax, .{ .name = "__aarch64_ldset4_relax", .linkage = linkage });
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\\ @export(__aarch64_ldset4_acq, .{ .name = "__aarch64_ldset4_acq", .linkage = linkage });
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\\ @export(__aarch64_ldset4_rel, .{ .name = "__aarch64_ldset4_rel", .linkage = linkage });
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\\ @export(__aarch64_ldset4_acq_rel, .{ .name = "__aarch64_ldset4_acq_rel", .linkage = linkage });
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\\ @export(__aarch64_ldset8_relax, .{ .name = "__aarch64_ldset8_relax", .linkage = linkage });
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\\ @export(__aarch64_ldset8_acq, .{ .name = "__aarch64_ldset8_acq", .linkage = linkage });
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\\ @export(__aarch64_ldset8_rel, .{ .name = "__aarch64_ldset8_rel", .linkage = linkage });
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\\ @export(__aarch64_ldset8_acq_rel, .{ .name = "__aarch64_ldset8_acq_rel", .linkage = linkage });
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\\ }
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\\}
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\\
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);
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}
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fn usageAndExit(file: std.fs.File, arg0: []const u8, code: u8) noreturn {
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file.writer().print(
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\\Usage: {s} /path/to/lib/compiler_rt/lse_atomics.zig
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\\
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\\Generates outline atomics for compiler-rt.
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\\
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, .{arg0}) catch std.process.exit(1);
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std.process.exit(code);
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}
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fn writeFunction(file: *std.fs.File, name: [:0]const u8, op: AtomicOp, n: N, body: [:0]const u8) !void {
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var fn_buf: [100:0]u8 = undefined;
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const fn_sig = if (op != .cas)
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try std.fmt.bufPrintZ(&fn_buf, "fn {[name]s}(val: u{[n]s}, ptr: *u{[n]s}) callconv(.C) u{[n]s} {{", .{ .name = name, .n = n.toBits() })
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else
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try std.fmt.bufPrintZ(&fn_buf, "fn {[name]s}(expected: u{[n]s}, desired: u{[n]s}, ptr: *u{[n]s}) callconv(.C) u{[n]s} {{", .{ .name = name, .n = n.toBits() });
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try file.writeAll(fn_sig);
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try file.writeAll(
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\\
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\\ @setRuntimeSafety(false);
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\\ __init_aarch64_have_lse_atomics();
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\\
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\\ return asm volatile (
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\\
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);
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var iter = std.mem.split(u8, body, "\n");
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while (iter.next()) |line| {
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try file.writeAll(" \\\\");
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try file.writeAll(line);
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try file.writeAll("\n");
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}
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var constraint_buf: [500:0]u8 = undefined;
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const constraints = if (op != .cas)
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try std.fmt.bufPrintZ(&constraint_buf,
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\\ : [ret] "={{{[reg]s}0}}" (-> u{[ty]s}),
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\\ : [val] "{{{[reg]s}0}}" (val),
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\\ [ptr] "{{x1}}" (ptr),
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\\ [__aarch64_have_lse_atomics] "{{w16}}" (__aarch64_have_lse_atomics),
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\\ : "w15", "w16", "w17", "memory"
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\\
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, .{ .reg = n.register(), .ty = n.toBits() })
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else
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try std.fmt.bufPrintZ(&constraint_buf,
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\\ : [ret] "={{{[reg]s}0}}" (-> u{[ty]s}),
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\\ : [expected] "{{{[reg]s}0}}" (expected),
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\\ [desired] "{{{[reg]s}1}}" (desired),
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\\ [ptr] "{{x2}}" (ptr),
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\\ [__aarch64_have_lse_atomics] "{{w16}}" (__aarch64_have_lse_atomics),
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\\ : "w15", "w16", "w17", "memory"
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\\
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, .{ .reg = n.register(), .ty = n.toBits() });
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try file.writeAll(constraints);
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try file.writeAll(
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\\ );
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\\
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||||
);
|
||||
try file.writeAll("}\n");
|
||||
}
|
||||
|
||||
fn writeExport(file: *std.fs.File, pat: [:0]const u8, n: [:0]const u8, order: Ordering) !void {
|
||||
var darwin_lse_buf: [100:0]u8 = undefined;
|
||||
var darwin_nolse_buf: [100:0]u8 = undefined;
|
||||
var nodarwin_lse_buf: [100:0]u8 = undefined;
|
||||
var nodarwin_nolse_buf: [100:0]u8 = undefined;
|
||||
var name_buf: [100:0]u8 = undefined;
|
||||
const darwin_lse = try std.fmt.bufPrintZ(&darwin_lse_buf, "{s}{s}{s}DarwinLse", .{ pat, n, order.capName() });
|
||||
const darwin_nolse = try std.fmt.bufPrintZ(&darwin_nolse_buf, "{s}{s}{s}DarwinNolse", .{ pat, n, order.capName() });
|
||||
const nodarwin_lse = try std.fmt.bufPrintZ(&nodarwin_lse_buf, "{s}{s}{s}NondarwinLse", .{ pat, n, order.capName() });
|
||||
const nodarwin_nolse = try std.fmt.bufPrintZ(&nodarwin_nolse_buf, "{s}{s}{s}NondarwinNolse", .{ pat, n, order.capName() });
|
||||
const name = try std.fmt.bufPrintZ(&name_buf, "__aarch64_{s}{s}_{s}", .{ pat, n, @tagName(order) });
|
||||
try file.writeAll("const ");
|
||||
try file.writeAll(name);
|
||||
try file.writeAll(
|
||||
\\ = if (is_darwin)
|
||||
\\ if (has_lse)
|
||||
\\
|
||||
);
|
||||
try file.writeAll(darwin_lse);
|
||||
try file.writeAll(
|
||||
\\
|
||||
\\ else
|
||||
\\
|
||||
);
|
||||
try file.writeAll(darwin_nolse);
|
||||
try file.writeAll(
|
||||
\\
|
||||
\\else if (has_lse)
|
||||
\\
|
||||
);
|
||||
try file.writeAll(nodarwin_lse);
|
||||
try file.writeAll(
|
||||
\\
|
||||
\\else
|
||||
\\
|
||||
);
|
||||
try file.writeAll(nodarwin_nolse);
|
||||
try file.writeAll(
|
||||
\\;
|
||||
\\
|
||||
);
|
||||
}
|
||||
|
||||
const N = enum(u8) {
|
||||
one = 1,
|
||||
two = 2,
|
||||
four = 4,
|
||||
eight = 8,
|
||||
sixteen = 16,
|
||||
|
||||
const Defines = struct {
|
||||
s: [:0]const u8,
|
||||
uxt: [:0]const u8,
|
||||
b: [:0]const u8,
|
||||
};
|
||||
fn defines(self: @This()) Defines {
|
||||
const s = switch (self) {
|
||||
.one => "b",
|
||||
.two => "h",
|
||||
else => "",
|
||||
};
|
||||
const uxt = switch (self) {
|
||||
.one => "uxtb",
|
||||
.two => "uxth",
|
||||
.four, .eight, .sixteen => "mov",
|
||||
};
|
||||
const b = switch (self) {
|
||||
.one => "0x00000000",
|
||||
.two => "0x40000000",
|
||||
.four => "0x80000000",
|
||||
.eight => "0xc0000000",
|
||||
else => "0x00000000",
|
||||
};
|
||||
return Defines{
|
||||
.s = s,
|
||||
.uxt = uxt,
|
||||
.b = b,
|
||||
};
|
||||
}
|
||||
|
||||
fn register(self: @This()) [:0]const u8 {
|
||||
return if (@enumToInt(self) < 8) "w" else "x";
|
||||
}
|
||||
|
||||
fn toBytes(self: @This()) [:0]const u8 {
|
||||
return switch (self) {
|
||||
.one => "1",
|
||||
.two => "2",
|
||||
.four => "4",
|
||||
.eight => "8",
|
||||
.sixteen => "16",
|
||||
};
|
||||
}
|
||||
|
||||
fn toBits(self: @This()) [:0]const u8 {
|
||||
return switch (self) {
|
||||
.one => "8",
|
||||
.two => "16",
|
||||
.four => "32",
|
||||
.eight => "64",
|
||||
.sixteen => "128",
|
||||
};
|
||||
}
|
||||
};
|
||||
|
||||
const Ordering = enum {
|
||||
relax,
|
||||
acq,
|
||||
rel,
|
||||
acq_rel,
|
||||
|
||||
const Defines = struct {
|
||||
suff: [:0]const u8,
|
||||
a: [:0]const u8,
|
||||
l: [:0]const u8,
|
||||
m: [:0]const u8,
|
||||
n: [:0]const u8,
|
||||
};
|
||||
fn defines(self: @This()) Defines {
|
||||
const suff = switch (self) {
|
||||
.relax => "_relax",
|
||||
.acq => "_acq",
|
||||
.rel => "_rel",
|
||||
.acq_rel => "_acq_rel",
|
||||
};
|
||||
const a = switch (self) {
|
||||
.relax => "",
|
||||
.acq => "a",
|
||||
.rel => "",
|
||||
.acq_rel => "a",
|
||||
};
|
||||
const l = switch (self) {
|
||||
.relax => "",
|
||||
.acq => "",
|
||||
.rel => "l",
|
||||
.acq_rel => "l",
|
||||
};
|
||||
const m = switch (self) {
|
||||
.relax => "0x000000",
|
||||
.acq => "0x400000",
|
||||
.rel => "0x008000",
|
||||
.acq_rel => "0x408000",
|
||||
};
|
||||
const n = switch (self) {
|
||||
.relax => "0x000000",
|
||||
.acq => "0x800000",
|
||||
.rel => "0x400000",
|
||||
.acq_rel => "0xc00000",
|
||||
};
|
||||
return .{ .suff = suff, .a = a, .l = l, .m = m, .n = n };
|
||||
}
|
||||
|
||||
fn capName(self: @This()) [:0]const u8 {
|
||||
return switch (self) {
|
||||
.relax => "Relax",
|
||||
.acq => "Acq",
|
||||
.rel => "Rel",
|
||||
.acq_rel => "AcqRel",
|
||||
};
|
||||
}
|
||||
};
|
||||
|
||||
const LdName = enum { ldadd, ldclr, ldeor, ldset };
|
||||
|
||||
fn generateCas(alloc: *Allocator, n: N, order: Ordering, lse: bool) ![:0]const u8 {
|
||||
const s_def = n.defines();
|
||||
const o_def = order.defines();
|
||||
var cas_buf = try alloc.create([200:0]u8);
|
||||
var ldxr_buf = try alloc.create([200:0]u8);
|
||||
var stxr_buf = try alloc.create([200:0]u8);
|
||||
defer alloc.destroy(cas_buf);
|
||||
defer alloc.destroy(ldxr_buf);
|
||||
defer alloc.destroy(stxr_buf);
|
||||
var instr_buf = try alloc.create([1000:0]u8);
|
||||
errdefer alloc.destroy(instr_buf);
|
||||
|
||||
const reg = n.register();
|
||||
|
||||
if (@enumToInt(n) < 16) {
|
||||
const cas = if (lse) blk: {
|
||||
break :blk try std.fmt.bufPrintZ(cas_buf,
|
||||
\\cas{[a]s}{[l]s}{[s]s} {[reg]s}0, {[reg]s}1, [x2]
|
||||
\\
|
||||
, .{ .a = o_def.a, .l = o_def.l, .s = s_def.s, .reg = reg });
|
||||
} else try std.fmt.bufPrintZ(cas_buf, ".inst 0x08a07c41 + {s} + {s}\n", .{ s_def.b, o_def.m });
|
||||
const ldxr = try std.fmt.bufPrintZ(ldxr_buf, "ld{s}xr{s}", .{ o_def.a, s_def.s });
|
||||
const stxr = try std.fmt.bufPrintZ(stxr_buf, "st{s}xr{s}", .{ o_def.l, s_def.s });
|
||||
|
||||
return try std.fmt.bufPrintZ(instr_buf,
|
||||
\\ cbz w16, 8f
|
||||
\\ {[cas]s}
|
||||
\\ cbz wzr, 1f
|
||||
\\8:
|
||||
\\ {[uxt]s} {[reg]s}16, {[reg]s}0
|
||||
\\0:
|
||||
\\ {[ldxr]s} {[reg]s}0, [x2]
|
||||
\\ cmp {[reg]s}0, {[reg]s}16
|
||||
\\ bne 1f
|
||||
\\ {[stxr]s} w17, {[reg]s}1, [x2]
|
||||
\\ cbnz w17, 0b
|
||||
\\1:
|
||||
, .{
|
||||
.cas = cas,
|
||||
.uxt = s_def.uxt,
|
||||
.ldxr = ldxr,
|
||||
.stxr = stxr,
|
||||
.reg = reg,
|
||||
});
|
||||
} else {
|
||||
const casp = if (lse)
|
||||
try std.fmt.bufPrintZ(cas_buf, "casp{s}{s} x0, x1, x2, x3, [x4]\n", .{ o_def.a, o_def.l })
|
||||
else
|
||||
try std.fmt.bufPrintZ(cas_buf, ".inst 0x48207c82 + {s}\n", .{o_def.m});
|
||||
|
||||
const ldxp = try std.fmt.bufPrintZ(ldxr_buf, "ld{s}xp", .{o_def.a});
|
||||
const stxp = try std.fmt.bufPrintZ(stxr_buf, "st{s}xp", .{o_def.l});
|
||||
|
||||
return try std.fmt.bufPrintZ(instr_buf,
|
||||
\\ cbz w16, 8f
|
||||
\\ {[casp]s}
|
||||
\\ cbz wzr, 1f
|
||||
\\8:
|
||||
\\ mov x16, x0
|
||||
\\ mov x17, x1
|
||||
\\0:
|
||||
\\ {[ldxp]s} x0, x1, [x4]
|
||||
\\ cmp x0, x16
|
||||
\\ ccmp x1, x17, #0, eq
|
||||
\\ bne 1f
|
||||
\\ {[stxp]s} w15, x2, x3, [x4]
|
||||
\\ cbnz w15, 0b
|
||||
\\1:
|
||||
, .{
|
||||
.casp = casp,
|
||||
.ldxp = ldxp,
|
||||
.stxp = stxp,
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
fn generateSwp(alloc: *Allocator, n: N, order: Ordering, lse: bool) ![:0]const u8 {
|
||||
const s_def = n.defines();
|
||||
const o_def = order.defines();
|
||||
|
||||
var swp_buf = try alloc.create([200:0]u8);
|
||||
var ldxr_buf = try alloc.create([200:0]u8);
|
||||
var stxr_buf = try alloc.create([200:0]u8);
|
||||
defer alloc.destroy(swp_buf);
|
||||
defer alloc.destroy(ldxr_buf);
|
||||
defer alloc.destroy(stxr_buf);
|
||||
|
||||
const reg = n.register();
|
||||
|
||||
const swp = if (lse) blk: {
|
||||
break :blk try std.fmt.bufPrintZ(swp_buf,
|
||||
\\swp{[a]s}{[l]s}{[s]s} {[reg]s}0, {[reg]s}0, [x1]
|
||||
, .{ .a = o_def.a, .l = o_def.l, .s = s_def.s, .reg = reg });
|
||||
} else std.fmt.bufPrintZ(swp_buf, ".inst 0x38208020 + {s} + {s}", .{ .b = s_def.b, .n = o_def.n });
|
||||
|
||||
const ldxr = try std.fmt.bufPrintZ(ldxr_buf, "ld{s}xr{s}", .{ o_def.a, s_def.s });
|
||||
const stxr = try std.fmt.bufPrintZ(stxr_buf, "st{s}xr{s}", .{ o_def.l, s_def.s });
|
||||
|
||||
var instr_buf = try alloc.create([1000:0]u8);
|
||||
errdefer alloc.destroy(instr_buf);
|
||||
return try std.fmt.bufPrintZ(instr_buf,
|
||||
\\ cbz w16, 8f
|
||||
\\ {[swp]s}
|
||||
\\ cbz wzr, 1f
|
||||
\\8:
|
||||
\\ mov {[reg]s}16, {[reg]s}0
|
||||
\\0:
|
||||
\\ {[ldxr]s} {[reg]s}0, [x1]
|
||||
\\ {[stxr]s} w17, {[reg]s}16, [x1]
|
||||
\\ cbnz w17, 0b
|
||||
\\1:
|
||||
, .{
|
||||
.swp = swp,
|
||||
.ldxr = ldxr,
|
||||
.stxr = stxr,
|
||||
.reg = reg,
|
||||
});
|
||||
}
|
||||
|
||||
fn generateLd(alloc: *Allocator, n: N, order: Ordering, ld: LdName, lse: bool) ![:0]const u8 {
|
||||
const s_def = n.defines();
|
||||
const o_def = order.defines();
|
||||
const ldname = @tagName(ld);
|
||||
const op = switch (ld) {
|
||||
.ldadd => "add",
|
||||
.ldclr => "bic",
|
||||
.ldeor => "eor",
|
||||
.ldset => "orr",
|
||||
};
|
||||
const op_n = switch (ld) {
|
||||
.ldadd => "0x0000",
|
||||
.ldclr => "0x1000",
|
||||
.ldeor => "0x2000",
|
||||
.ldset => "0x3000",
|
||||
};
|
||||
|
||||
var swp_buf = try alloc.create([200:0]u8);
|
||||
var ldop_buf = try alloc.create([200:0]u8);
|
||||
var ldxr_buf = try alloc.create([200:0]u8);
|
||||
var stxr_buf = try alloc.create([200:0]u8);
|
||||
defer alloc.destroy(swp_buf);
|
||||
defer alloc.destroy(ldop_buf);
|
||||
defer alloc.destroy(ldxr_buf);
|
||||
defer alloc.destroy(stxr_buf);
|
||||
|
||||
const reg = n.register();
|
||||
|
||||
const ldop = if (lse)
|
||||
std.fmt.bufPrintZ(ldop_buf,
|
||||
\\{[ldnm]s}{[a]s}{[l]s}{[s]s} {[reg]s}0, {[reg]s}0, [x1]
|
||||
, .{ .ldnm = ldname, .a = o_def.a, .l = o_def.l, .s = s_def.s, .reg = reg })
|
||||
else
|
||||
std.fmt.bufPrintZ(ldop_buf,
|
||||
\\.inst 0x38200020 + {[op_n]s} + {[b]s} + {[n]s}
|
||||
, .{ .op_n = op_n, .b = s_def.b, .n = o_def.n });
|
||||
|
||||
const ldxr = try std.fmt.bufPrintZ(ldxr_buf, "ld{s}xr{s}", .{ o_def.a, s_def.s });
|
||||
const stxr = try std.fmt.bufPrintZ(stxr_buf, "st{s}xr{s}", .{ o_def.l, s_def.s });
|
||||
|
||||
var instr_buf = try alloc.create([1000:0]u8);
|
||||
errdefer alloc.destroy(instr_buf);
|
||||
return try std.fmt.bufPrintZ(instr_buf,
|
||||
\\ cbz w16, 8f
|
||||
\\ {[ldop]s}
|
||||
\\ cbz wzr, 1f
|
||||
\\8:
|
||||
\\ mov {[reg]s}16, {[reg]s}0
|
||||
\\0:
|
||||
\\ {[ldxr]s} {[reg]s}0, [x1]
|
||||
\\ {[op]s} {[reg]s}17, {[reg]s}0, {[reg]s}16
|
||||
\\ {[stxr]s} w15, {[reg]s}17, [x1]
|
||||
\\ cbnz w15, 0b
|
||||
\\1:
|
||||
, .{
|
||||
.ldop = ldop,
|
||||
.ldxr = ldxr,
|
||||
.stxr = stxr,
|
||||
.op = op,
|
||||
.reg = reg,
|
||||
});
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue