update RISC-V target CPU features

lib/std/target/riscv.zig

@@ -1,8 +1,5 @@
-// SPDX-License-Identifier: MIT
-// Copyright (c) 2015-2021 Zig Contributors
-// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
-// The MIT license requires this copyright notice to be included in all copies
-// and substantial portions of the software.
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
 const std = @import("../std.zig");
 const CpuFeature = std.Target.Cpu.Feature;
 const CpuModel = std.Target.Cpu.Model;
@@ -15,6 +12,7 @@ pub const Feature = enum {
     e,
     experimental_b,
     experimental_v,
+    experimental_zba,
     experimental_zbb,
     experimental_zbc,
     experimental_zbe,
@@ -103,6 +101,7 @@ pub const all_features = blk: {
         .llvm_name = "experimental-b",
         .description = "'B' (Bit Manipulation Instructions)",
         .dependencies = featureSet(&[_]Feature{
+            .experimental_zba,
             .experimental_zbb,
             .experimental_zbc,
             .experimental_zbe,
@@ -117,9 +116,12 @@ pub const all_features = blk: {
     result[@enumToInt(Feature.experimental_v)] = .{
         .llvm_name = "experimental-v",
         .description = "'V' (Vector Instructions)",
-        .dependencies = featureSet(&[_]Feature{
-            .f,
-        }),
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@enumToInt(Feature.experimental_zba)] = .{
+        .llvm_name = "experimental-zba",
+        .description = "'Zba' (Address calculation 'B' Instructions)",
+        .dependencies = featureSet(&[_]Feature{}),
     };
     result[@enumToInt(Feature.experimental_zbb)] = .{
         .llvm_name = "experimental-zbb",
@@ -467,7 +469,6 @@ pub const cpu = struct {
             .a,
             .c,
             .d,
-            .f,
             .m,
         }),
     };
@@ -479,7 +480,6 @@ pub const cpu = struct {
             .a,
             .c,
             .d,
-            .f,
             .m,
         }),
     };

tools/update_cpu_features.zig

@@ -11,11 +11,18 @@ const FeatureOverride = struct {
     desc: ?[]const u8 = null,
 };
 
+const ExtraCpu = struct {
+    llvm_name: ?[]const u8,
+    zig_name: []const u8,
+    features: []const []const u8,
+};
+
 const LlvmTarget = struct {
     zig_name: []const u8,
     llvm_name: []const u8,
     td_name: []const u8,
     feature_overrides: []const FeatureOverride = &.{},
+    extra_cpus: []const ExtraCpu = &.{},
     branch_quota: ?usize = null,
 };
 
@@ -98,6 +105,18 @@ const llvm_targets = [_]LlvmTarget{
         .zig_name = "riscv",
         .llvm_name = "RISCV",
         .td_name = "RISCV.td",
+        .extra_cpus = &.{
+            .{
+                .llvm_name = null,
+                .zig_name = "baseline_rv32",
+                .features = &.{ "a", "c", "d", "f", "m" },
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "baseline_rv64",
+                .features = &.{ "64bit", "a", "c", "d", "f", "m" },
+            },
+        },
     },
     .{
         .zig_name = "sparc",
@@ -433,7 +452,44 @@ fn processOneTarget(job: Job) anyerror!void {
         \\pub const cpu = struct {
         \\
     );
-
+    for (llvm_target.extra_cpus) |extra_cpu| {
+        try w.print(
+            \\    pub const {} = CpuModel{{
+            \\        .name = "{}",
+            \\
+        , .{
+            std.zig.fmtId(extra_cpu.zig_name),
+            std.zig.fmtEscapes(extra_cpu.zig_name),
+        });
+        if (extra_cpu.llvm_name) |llvm_name| {
+            try w.print(
+                \\        .llvm_name = "{}",
+                \\        .features = featureSet(&[_]Feature{{
+            , .{std.zig.fmtEscapes(llvm_name)});
+        } else {
+            try w.writeAll(
+                \\        .llvm_name = null,
+                \\        .features = featureSet(&[_]Feature{
+            );
+        }
+        if (extra_cpu.features.len == 0) {
+            try w.writeAll(
+                \\}),
+                \\    };
+                \\
+            );
+        } else {
+            try w.writeAll("\n");
+            for (extra_cpu.features) |feature_zig_name| {
+                try w.print("            .{},\n", .{std.zig.fmtId(feature_zig_name)});
+            }
+            try w.writeAll(
+                \\        }),
+                \\    };
+                \\
+            );
+        }
+    }
     for (all_cpus.items) |obj| {
         const llvm_name = obj.get("Name").?.String;
         var deps_set = std.StringHashMap(void).init(arena);
@@ -516,7 +572,7 @@ fn usageAndExit(file: fs.File, arg0: []const u8, code: u8) noreturn {
 fn objectLessThan(context: void, a: *json.ObjectMap, b: *json.ObjectMap) bool {
     const a_key = a.get("Name").?.String;
     const b_key = b.get("Name").?.String;
-    return std.mem.lessThan(u8, a_key, b_key);
+    return std.ascii.lessThanIgnoreCase(a_key, b_key);
 }
 
 fn llvmNameToZigName(