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https://codeberg.org/ziglang/zig.git
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update target CPU features for LLVM 15
This commit is contained in:
Andrew Kelley
parent
5043369e14
commit
c75226d033
11 changed files with 3825 additions and 85 deletions
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@ -19,6 +19,7 @@ pub const Feature = enum {
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amvs,
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arith_bcc_fusion,
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arith_cbz_fusion,
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ascend_store_address,
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balance_fp_ops,
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bf16,
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brbe,
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@ -61,6 +62,7 @@ pub const Feature = enum {
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fptoint,
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fullfp16,
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fuse_address,
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fuse_adrp_add,
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fuse_aes,
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fuse_arith_logic,
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fuse_crypto_eor,
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@ -73,6 +75,7 @@ pub const Feature = enum {
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hcx,
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i8mm,
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jsconv,
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ldapr,
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lor,
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ls64,
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lse,
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@ -139,7 +142,6 @@ pub const Feature = enum {
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spe_eef,
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specrestrict,
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ssbs,
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streaming_sve,
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strict_align,
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sve,
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sve2,
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@ -206,6 +208,7 @@ pub const all_features = blk: {
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.description = "Cortex-A65 ARM processors",
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.dependencies = featureSet(&[_]Feature{
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.fuse_address,
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.fuse_adrp_add,
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.fuse_aes,
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.fuse_literals,
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}),
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@ -288,6 +291,11 @@ pub const all_features = blk: {
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.description = "CPU fuses arithmetic + cbz/cbnz operations",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.ascend_store_address)] = .{
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.llvm_name = "ascend-store-address",
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.description = "Schedule vector stores by ascending address",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.balance_fp_ops)] = .{
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.llvm_name = "balance-fp-ops",
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.description = "balance mix of odd and even D-registers for fp multiply(-accumulate) ops",
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@ -517,6 +525,11 @@ pub const all_features = blk: {
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.description = "CPU fuses address generation and memory operations",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.fuse_adrp_add)] = .{
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.llvm_name = "fuse-adrp-add",
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.description = "CPU fuses adrp+add operations",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.fuse_aes)] = .{
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.llvm_name = "fuse-aes",
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.description = "CPU fuses AES crypto operations",
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@ -579,6 +592,11 @@ pub const all_features = blk: {
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.fp_armv8,
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}),
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};
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result[@enumToInt(Feature.ldapr)] = .{
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.llvm_name = "ldapr",
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.description = "Use LDAPR to lower atomic loads; experimental until we have more testing/a formal correctness proof",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.lor)] = .{
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.llvm_name = "lor",
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.description = "Enables ARM v8.1 Limited Ordering Regions extension",
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@ -891,7 +909,7 @@ pub const all_features = blk: {
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.description = "Enable Scalable Matrix Extension (SME)",
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.dependencies = featureSet(&[_]Feature{
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.bf16,
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.streaming_sve,
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.use_scalar_inc_vl,
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}),
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};
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result[@enumToInt(Feature.sme_f64)] = .{
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@ -928,11 +946,6 @@ pub const all_features = blk: {
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.description = "Enable Speculative Store Bypass Safe bit",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.streaming_sve)] = .{
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.llvm_name = "streaming-sve",
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.description = "Enable subset of SVE(2) instructions for Streaming SVE execution mode",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.strict_align)] = .{
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.llvm_name = "strict-align",
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.description = "Disallow all unaligned memory access",
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@ -1178,6 +1191,7 @@ pub const all_features = blk: {
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.rcpc_immo,
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.rdm,
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.sel2,
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.specrestrict,
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.tlb_rmi,
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.tracev8_4,
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.uaops,
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@ -1387,6 +1401,7 @@ pub const cpu = struct {
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.fp16fml,
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.fptoint,
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.fuse_address,
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.fuse_adrp_add,
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.fuse_aes,
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.fuse_arith_logic,
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.fuse_crypto_eor,
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@ -1472,6 +1487,7 @@ pub const cpu = struct {
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.fp16fml,
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.fptoint,
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.fuse_address,
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.fuse_adrp_add,
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.fuse_aes,
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.fuse_arith_logic,
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.fuse_crypto_eor,
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@ -1503,6 +1519,7 @@ pub const cpu = struct {
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.fp16fml,
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.fptoint,
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.fuse_address,
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.fuse_adrp_add,
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.fuse_aes,
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.fuse_arith_logic,
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.fuse_crypto_eor,
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@ -1636,6 +1653,7 @@ pub const cpu = struct {
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.crc,
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.crypto,
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.custom_cheap_as_move,
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.fuse_adrp_add,
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.fuse_aes,
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.fuse_literals,
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.perfmon,
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@ -1652,6 +1670,7 @@ pub const cpu = struct {
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.crypto,
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.dotprod,
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.fullfp16,
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.perfmon,
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.rcpc,
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.ssbs,
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.v8_2a,
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@ -1665,6 +1684,7 @@ pub const cpu = struct {
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.crypto,
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.dotprod,
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.fullfp16,
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.perfmon,
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.rcpc,
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.ssbs,
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.v8_2a,
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@ -1691,6 +1711,7 @@ pub const cpu = struct {
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.features = featureSet(&[_]Feature{
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.crc,
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.crypto,
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.fuse_adrp_add,
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.fuse_aes,
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.fuse_literals,
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.perfmon,
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@ -1729,6 +1750,7 @@ pub const cpu = struct {
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.crypto,
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.dotprod,
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.fullfp16,
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.perfmon,
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.rcpc,
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.ssbs,
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.v8_2a,
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@ -1742,6 +1764,7 @@ pub const cpu = struct {
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.crypto,
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.dotprod,
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.fullfp16,
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.perfmon,
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.rcpc,
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.ssbs,
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.v8_2a,
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@ -1756,6 +1779,7 @@ pub const cpu = struct {
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.dotprod,
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.fullfp16,
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.fuse_aes,
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.perfmon,
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.rcpc,
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.ssbs,
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.v8_2a,
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@ -1802,7 +1826,6 @@ pub const cpu = struct {
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.perfmon,
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.predres,
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.sb,
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.specrestrict,
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.ssbs,
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.v8r,
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}),
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@ -1924,22 +1947,20 @@ pub const cpu = struct {
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.name = "exynos_m3",
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.llvm_name = "exynos-m3",
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.features = featureSet(&[_]Feature{
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.arith_bcc_fusion,
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.arith_cbz_fusion,
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.crc,
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.crypto,
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.exynos_cheap_as_move,
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.force_32bit_jump_tables,
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.fuse_address,
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.fuse_adrp_add,
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.fuse_aes,
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.fuse_arith_logic,
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.fuse_csel,
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.fuse_literals,
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.lsl_fast,
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.perfmon,
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.predictable_select_expensive,
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.use_postra_scheduler,
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.v8a,
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.zcz,
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}),
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};
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pub const exynos_m4 = CpuModel{
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@ -1954,6 +1975,7 @@ pub const cpu = struct {
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.force_32bit_jump_tables,
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.fullfp16,
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.fuse_address,
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.fuse_adrp_add,
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.fuse_aes,
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.fuse_arith_logic,
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.fuse_csel,
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@ -1977,6 +1999,7 @@ pub const cpu = struct {
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.force_32bit_jump_tables,
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.fullfp16,
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.fuse_address,
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.fuse_adrp_add,
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.fuse_aes,
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.fuse_arith_logic,
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.fuse_csel,
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@ -2010,9 +2033,9 @@ pub const cpu = struct {
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.llvm_name = "generic",
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.features = featureSet(&[_]Feature{
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.ete,
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.fuse_adrp_add,
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.fuse_aes,
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.neon,
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.perfmon,
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.use_postra_scheduler,
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}),
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};
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@ -2058,6 +2081,7 @@ pub const cpu = struct {
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.dotprod,
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.fullfp16,
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.fuse_aes,
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.perfmon,
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.rcpc,
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.ssbs,
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.use_postra_scheduler,
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@ -2072,6 +2096,7 @@ pub const cpu = struct {
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.dotprod,
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.fullfp16,
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.fuse_aes,
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.perfmon,
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.rcpc,
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.spe,
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.ssbs,
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@ -2089,6 +2114,7 @@ pub const cpu = struct {
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.fuse_aes,
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.i8mm,
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.mte,
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.perfmon,
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.sve2_bitperm,
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.use_postra_scheduler,
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.v8_5a,
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@ -10,7 +10,9 @@ pub const Feature = enum {
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add_no_carry_insts,
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aperture_regs,
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architected_flat_scratch,
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atomic_fadd_insts,
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atomic_fadd_no_rtn_insts,
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atomic_fadd_rtn_insts,
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atomic_pk_fadd_no_rtn_insts,
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auto_waitcnt_before_barrier,
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ci_insts,
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cumode,
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@ -22,12 +24,12 @@ pub const Feature = enum {
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dot5_insts,
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dot6_insts,
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dot7_insts,
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dot8_insts,
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dpp,
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dpp8,
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dpp_64bit,
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ds128,
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ds_src2_insts,
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enable_ds128,
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enable_prt_strict_null,
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extended_image_insts,
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fast_denormal_f32,
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fast_fmaf,
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@ -35,11 +37,13 @@ pub const Feature = enum {
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flat_for_global,
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flat_global_insts,
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flat_inst_offsets,
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flat_scratch,
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flat_scratch_insts,
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flat_segment_offset_bug,
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fma_mix_insts,
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fmaf,
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fp64,
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fp8_insts,
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full_rate_64_ops,
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g16,
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gcn3_encoding,
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@ -49,13 +53,17 @@ pub const Feature = enum {
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gfx10_a_encoding,
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gfx10_b_encoding,
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gfx10_insts,
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gfx11,
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gfx11_insts,
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gfx7_gfx8_gfx9_insts,
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gfx8_insts,
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gfx9,
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gfx90a_insts,
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gfx940_insts,
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gfx9_insts,
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half_rate_64_ops,
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image_gather4_d16_bug,
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image_insts,
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image_store_d16_bug,
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inst_fwd_prefetch_bug,
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int_clamp_insts,
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@ -90,6 +98,7 @@ pub const Feature = enum {
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packed_tid,
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pk_fmac_f16_inst,
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promote_alloca,
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prt_strict_null,
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r128_a16,
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s_memrealtime,
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s_memtime_inst,
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@ -113,12 +122,14 @@ pub const Feature = enum {
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tgsplit,
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trap_handler,
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trig_reduced_range,
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true16,
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unaligned_access_mode,
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unaligned_buffer_access,
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unaligned_ds_access,
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unaligned_scratch_access,
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unpacked_d16_vmem,
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unsafe_ds_offset_folding,
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user_sgpr_init16_bug,
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vcmpx_exec_war_hazard,
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vcmpx_permlane_hazard,
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vgpr_index_mode,
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@ -126,6 +137,7 @@ pub const Feature = enum {
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volcanic_islands,
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vop3_literal,
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vop3p,
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vopd,
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vscnt,
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wavefrontsize16,
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wavefrontsize32,
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@ -168,9 +180,23 @@ pub const all_features = blk: {
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.description = "Flat Scratch register is a readonly SPI initialized architected register",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.atomic_fadd_insts)] = .{
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.llvm_name = "atomic-fadd-insts",
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.description = "Has buffer_atomic_add_f32, buffer_atomic_pk_add_f16, global_atomic_add_f32, global_atomic_pk_add_f16 instructions",
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result[@enumToInt(Feature.atomic_fadd_no_rtn_insts)] = .{
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.llvm_name = "atomic-fadd-no-rtn-insts",
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.description = "Has buffer_atomic_add_f32 and global_atomic_add_f32 instructions that don't return original value",
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.dependencies = featureSet(&[_]Feature{
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.flat_global_insts,
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}),
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};
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result[@enumToInt(Feature.atomic_fadd_rtn_insts)] = .{
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.llvm_name = "atomic-fadd-rtn-insts",
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.description = "Has buffer_atomic_add_f32 and global_atomic_add_f32 instructions that return original value",
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.dependencies = featureSet(&[_]Feature{
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.flat_global_insts,
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}),
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};
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result[@enumToInt(Feature.atomic_pk_fadd_no_rtn_insts)] = .{
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.llvm_name = "atomic-pk-fadd-no-rtn-insts",
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.description = "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that don't return original value",
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.dependencies = featureSet(&[_]Feature{
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.flat_global_insts,
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}),
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@ -230,6 +256,11 @@ pub const all_features = blk: {
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.description = "Has v_dot2_f32_f16, v_dot4_u32_u8, v_dot8_u32_u4 instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.dot8_insts)] = .{
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.llvm_name = "dot8-insts",
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.description = "Has v_dot2_f16_f16, v_dot2_bf16_bf16, v_dot2_f32_bf16, v_dot4_i32_iu8, v_dot8_i32_iu4 instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.dpp)] = .{
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.llvm_name = "dpp",
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.description = "Support DPP (Data Parallel Primitives) extension",
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@ -245,19 +276,14 @@ pub const all_features = blk: {
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.description = "Support DPP (Data Parallel Primitives) extension",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.ds_src2_insts)] = .{
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.llvm_name = "ds-src2-insts",
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.description = "Has ds_*_src2 instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.enable_ds128)] = .{
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result[@enumToInt(Feature.ds128)] = .{
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.llvm_name = "enable-ds128",
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.description = "Use ds_{read|write}_b128",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.enable_prt_strict_null)] = .{
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.llvm_name = "enable-prt-strict-null",
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.description = "Enable zeroing of result registers for sparse texture fetches",
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result[@enumToInt(Feature.ds_src2_insts)] = .{
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.llvm_name = "ds-src2-insts",
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.description = "Has ds_*_src2 instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.extended_image_insts)] = .{
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@ -295,6 +321,11 @@ pub const all_features = blk: {
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.description = "Flat instructions have immediate offset addressing mode",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.flat_scratch)] = .{
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.llvm_name = "enable-flat-scratch",
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.description = "Use scratch_* flat memory instructions to access scratch",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@enumToInt(Feature.flat_scratch_insts)] = .{
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.llvm_name = "flat-scratch-insts",
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.description = "Have scratch_* flat memory instructions",
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@ -320,6 +351,11 @@ pub const all_features = blk: {
|
|||
.description = "Enable double precision operations",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.fp8_insts)] = .{
|
||||
.llvm_name = "fp8-insts",
|
||||
.description = "Has fp8 and bf8 instructions",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.full_rate_64_ops)] = .{
|
||||
.llvm_name = "full-rate-64-ops",
|
||||
.description = "Most fp64 instructions are full rate",
|
||||
|
|
@ -364,6 +400,7 @@ pub const all_features = blk: {
|
|||
.gfx10_insts,
|
||||
.gfx8_insts,
|
||||
.gfx9_insts,
|
||||
.image_insts,
|
||||
.int_clamp_insts,
|
||||
.inv_2pi_inline_imm,
|
||||
.localmemorysize65536,
|
||||
|
|
@ -405,6 +442,56 @@ pub const all_features = blk: {
|
|||
.description = "Additional instructions for GFX10+",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.gfx11)] = .{
|
||||
.llvm_name = "gfx11",
|
||||
.description = "GFX11 GPU generation",
|
||||
.dependencies = featureSet(&[_]Feature{
|
||||
.@"16_bit_insts",
|
||||
.a16,
|
||||
.add_no_carry_insts,
|
||||
.aperture_regs,
|
||||
.ci_insts,
|
||||
.dpp,
|
||||
.dpp8,
|
||||
.extended_image_insts,
|
||||
.fast_denormal_f32,
|
||||
.fast_fmaf,
|
||||
.flat_address_space,
|
||||
.flat_global_insts,
|
||||
.flat_inst_offsets,
|
||||
.flat_scratch_insts,
|
||||
.fma_mix_insts,
|
||||
.fp64,
|
||||
.g16,
|
||||
.gfx10_3_insts,
|
||||
.gfx10_a_encoding,
|
||||
.gfx10_b_encoding,
|
||||
.gfx10_insts,
|
||||
.gfx11_insts,
|
||||
.gfx8_insts,
|
||||
.gfx9_insts,
|
||||
.int_clamp_insts,
|
||||
.inv_2pi_inline_imm,
|
||||
.localmemorysize65536,
|
||||
.mimg_r128,
|
||||
.movrel,
|
||||
.no_data_dep_hazard,
|
||||
.no_sdst_cmpx,
|
||||
.pk_fmac_f16_inst,
|
||||
.true16,
|
||||
.unaligned_buffer_access,
|
||||
.unaligned_ds_access,
|
||||
.vop3_literal,
|
||||
.vop3p,
|
||||
.vopd,
|
||||
.vscnt,
|
||||
}),
|
||||
};
|
||||
result[@enumToInt(Feature.gfx11_insts)] = .{
|
||||
.llvm_name = "gfx11-insts",
|
||||
.description = "Additional instructions for GFX11+",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.gfx7_gfx8_gfx9_insts)] = .{
|
||||
.llvm_name = "gfx7-gfx8-gfx9-insts",
|
||||
.description = "Instructions shared in GFX7, GFX8, GFX9",
|
||||
|
|
@ -462,6 +549,11 @@ pub const all_features = blk: {
|
|||
.description = "Additional instructions for GFX90A+",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.gfx940_insts)] = .{
|
||||
.llvm_name = "gfx940-insts",
|
||||
.description = "Additional instructions for GFX940+",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.gfx9_insts)] = .{
|
||||
.llvm_name = "gfx9-insts",
|
||||
.description = "Additional instructions for GFX9+",
|
||||
|
|
@ -477,6 +569,11 @@ pub const all_features = blk: {
|
|||
.description = "Image Gather4 D16 hardware bug",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.image_insts)] = .{
|
||||
.llvm_name = "image-insts",
|
||||
.description = "Support image instructions",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.image_store_d16_bug)] = .{
|
||||
.llvm_name = "image-store-d16-bug",
|
||||
.description = "Image Store D16 hardware bug",
|
||||
|
|
@ -647,6 +744,11 @@ pub const all_features = blk: {
|
|||
.description = "Enable promote alloca pass",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.prt_strict_null)] = .{
|
||||
.llvm_name = "enable-prt-strict-null",
|
||||
.description = "Enable zeroing of result registers for sparse texture fetches",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.r128_a16)] = .{
|
||||
.llvm_name = "r128-a16",
|
||||
.description = "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128",
|
||||
|
|
@ -717,6 +819,7 @@ pub const all_features = blk: {
|
|||
.flat_address_space,
|
||||
.fp64,
|
||||
.gfx7_gfx8_gfx9_insts,
|
||||
.image_insts,
|
||||
.localmemorysize65536,
|
||||
.mad_mac_f32_insts,
|
||||
.mimg_r128,
|
||||
|
|
@ -754,6 +857,7 @@ pub const all_features = blk: {
|
|||
.ds_src2_insts,
|
||||
.extended_image_insts,
|
||||
.fp64,
|
||||
.image_insts,
|
||||
.ldsbankcount32,
|
||||
.localmemorysize32768,
|
||||
.mad_mac_f32_insts,
|
||||
|
|
@ -789,6 +893,11 @@ pub const all_features = blk: {
|
|||
.description = "Requires use of fract on arguments to trig instructions",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.true16)] = .{
|
||||
.llvm_name = "true16",
|
||||
.description = "True 16-bit operand instructions",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.unaligned_access_mode)] = .{
|
||||
.llvm_name = "unaligned-access-mode",
|
||||
.description = "Enable unaligned global, local and region loads and stores if the hardware supports it",
|
||||
|
|
@ -819,6 +928,11 @@ pub const all_features = blk: {
|
|||
.description = "Force using DS instruction immediate offsets on SI",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.user_sgpr_init16_bug)] = .{
|
||||
.llvm_name = "user-sgpr-init16-bug",
|
||||
.description = "Bug requiring at least 16 user+system SGPRs to be enabled",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.vcmpx_exec_war_hazard)] = .{
|
||||
.llvm_name = "vcmpx-exec-war-hazard",
|
||||
.description = "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)",
|
||||
|
|
@ -854,6 +968,7 @@ pub const all_features = blk: {
|
|||
.gcn3_encoding,
|
||||
.gfx7_gfx8_gfx9_insts,
|
||||
.gfx8_insts,
|
||||
.image_insts,
|
||||
.int_clamp_insts,
|
||||
.inv_2pi_inline_imm,
|
||||
.localmemorysize65536,
|
||||
|
|
@ -882,6 +997,11 @@ pub const all_features = blk: {
|
|||
.description = "Has VOP3P packed instructions",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.vopd)] = .{
|
||||
.llvm_name = "vopd",
|
||||
.description = "Has VOPD dual issue wave32 instructions",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.vscnt)] = .{
|
||||
.llvm_name = "vscnt",
|
||||
.description = "Has separate store vscnt counter",
|
||||
|
|
@ -1226,6 +1346,118 @@ pub const cpu = struct {
|
|||
.wavefrontsize32,
|
||||
}),
|
||||
};
|
||||
pub const gfx1036 = CpuModel{
|
||||
.name = "gfx1036",
|
||||
.llvm_name = "gfx1036",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.dl_insts,
|
||||
.dot1_insts,
|
||||
.dot2_insts,
|
||||
.dot5_insts,
|
||||
.dot6_insts,
|
||||
.dot7_insts,
|
||||
.gfx10,
|
||||
.gfx10_3_insts,
|
||||
.gfx10_a_encoding,
|
||||
.gfx10_b_encoding,
|
||||
.ldsbankcount32,
|
||||
.nsa_encoding,
|
||||
.nsa_max_size_13,
|
||||
.shader_cycles_register,
|
||||
.wavefrontsize32,
|
||||
}),
|
||||
};
|
||||
pub const gfx1100 = CpuModel{
|
||||
.name = "gfx1100",
|
||||
.llvm_name = "gfx1100",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.architected_flat_scratch,
|
||||
.atomic_fadd_no_rtn_insts,
|
||||
.atomic_fadd_rtn_insts,
|
||||
.dl_insts,
|
||||
.dot5_insts,
|
||||
.dot7_insts,
|
||||
.dot8_insts,
|
||||
.gfx11,
|
||||
.image_insts,
|
||||
.ldsbankcount32,
|
||||
.nsa_encoding,
|
||||
.nsa_max_size_5,
|
||||
.packed_tid,
|
||||
.shader_cycles_register,
|
||||
.user_sgpr_init16_bug,
|
||||
.vcmpx_permlane_hazard,
|
||||
.wavefrontsize32,
|
||||
}),
|
||||
};
|
||||
pub const gfx1101 = CpuModel{
|
||||
.name = "gfx1101",
|
||||
.llvm_name = "gfx1101",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.architected_flat_scratch,
|
||||
.atomic_fadd_no_rtn_insts,
|
||||
.atomic_fadd_rtn_insts,
|
||||
.dl_insts,
|
||||
.dot5_insts,
|
||||
.dot7_insts,
|
||||
.dot8_insts,
|
||||
.gfx11,
|
||||
.image_insts,
|
||||
.ldsbankcount32,
|
||||
.nsa_encoding,
|
||||
.nsa_max_size_5,
|
||||
.packed_tid,
|
||||
.shader_cycles_register,
|
||||
.vcmpx_permlane_hazard,
|
||||
.wavefrontsize32,
|
||||
}),
|
||||
};
|
||||
pub const gfx1102 = CpuModel{
|
||||
.name = "gfx1102",
|
||||
.llvm_name = "gfx1102",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.architected_flat_scratch,
|
||||
.atomic_fadd_no_rtn_insts,
|
||||
.atomic_fadd_rtn_insts,
|
||||
.dl_insts,
|
||||
.dot5_insts,
|
||||
.dot7_insts,
|
||||
.dot8_insts,
|
||||
.gfx11,
|
||||
.image_insts,
|
||||
.ldsbankcount32,
|
||||
.nsa_encoding,
|
||||
.nsa_max_size_5,
|
||||
.packed_tid,
|
||||
.shader_cycles_register,
|
||||
.user_sgpr_init16_bug,
|
||||
.vcmpx_permlane_hazard,
|
||||
.wavefrontsize32,
|
||||
}),
|
||||
};
|
||||
pub const gfx1103 = CpuModel{
|
||||
.name = "gfx1103",
|
||||
.llvm_name = "gfx1103",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.architected_flat_scratch,
|
||||
.atomic_fadd_no_rtn_insts,
|
||||
.atomic_fadd_rtn_insts,
|
||||
.dl_insts,
|
||||
.dot5_insts,
|
||||
.dot7_insts,
|
||||
.dot8_insts,
|
||||
.gfx11,
|
||||
.image_insts,
|
||||
.ldsbankcount32,
|
||||
.nsa_encoding,
|
||||
.nsa_max_size_5,
|
||||
.packed_tid,
|
||||
.shader_cycles_register,
|
||||
.user_sgpr_init16_bug,
|
||||
.vcmpx_permlane_hazard,
|
||||
.wavefrontsize32,
|
||||
}),
|
||||
};
|
||||
pub const gfx600 = CpuModel{
|
||||
.name = "gfx600",
|
||||
.llvm_name = "gfx600",
|
||||
|
|
@ -1360,6 +1592,7 @@ pub const cpu = struct {
|
|||
.extended_image_insts,
|
||||
.gfx9,
|
||||
.image_gather4_d16_bug,
|
||||
.image_insts,
|
||||
.ldsbankcount32,
|
||||
.mad_mac_f32_insts,
|
||||
.mad_mix_insts,
|
||||
|
|
@ -1373,6 +1606,7 @@ pub const cpu = struct {
|
|||
.extended_image_insts,
|
||||
.gfx9,
|
||||
.image_gather4_d16_bug,
|
||||
.image_insts,
|
||||
.ldsbankcount32,
|
||||
.mad_mac_f32_insts,
|
||||
.mad_mix_insts,
|
||||
|
|
@ -1387,6 +1621,7 @@ pub const cpu = struct {
|
|||
.fma_mix_insts,
|
||||
.gfx9,
|
||||
.image_gather4_d16_bug,
|
||||
.image_insts,
|
||||
.ldsbankcount32,
|
||||
.mad_mac_f32_insts,
|
||||
}),
|
||||
|
|
@ -1405,6 +1640,7 @@ pub const cpu = struct {
|
|||
.gfx9,
|
||||
.half_rate_64_ops,
|
||||
.image_gather4_d16_bug,
|
||||
.image_insts,
|
||||
.ldsbankcount32,
|
||||
.mad_mac_f32_insts,
|
||||
.sramecc_support,
|
||||
|
|
@ -1414,7 +1650,8 @@ pub const cpu = struct {
|
|||
.name = "gfx908",
|
||||
.llvm_name = "gfx908",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.atomic_fadd_insts,
|
||||
.atomic_fadd_no_rtn_insts,
|
||||
.atomic_pk_fadd_no_rtn_insts,
|
||||
.dl_insts,
|
||||
.dot1_insts,
|
||||
.dot2_insts,
|
||||
|
|
@ -1429,6 +1666,7 @@ pub const cpu = struct {
|
|||
.gfx9,
|
||||
.half_rate_64_ops,
|
||||
.image_gather4_d16_bug,
|
||||
.image_insts,
|
||||
.ldsbankcount32,
|
||||
.mad_mac_f32_insts,
|
||||
.mai_insts,
|
||||
|
|
@ -1445,6 +1683,7 @@ pub const cpu = struct {
|
|||
.extended_image_insts,
|
||||
.gfx9,
|
||||
.image_gather4_d16_bug,
|
||||
.image_insts,
|
||||
.ldsbankcount32,
|
||||
.mad_mac_f32_insts,
|
||||
.mad_mix_insts,
|
||||
|
|
@ -1454,7 +1693,9 @@ pub const cpu = struct {
|
|||
.name = "gfx90a",
|
||||
.llvm_name = "gfx90a",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.atomic_fadd_insts,
|
||||
.atomic_fadd_no_rtn_insts,
|
||||
.atomic_fadd_rtn_insts,
|
||||
.atomic_pk_fadd_no_rtn_insts,
|
||||
.dl_insts,
|
||||
.dot1_insts,
|
||||
.dot2_insts,
|
||||
|
|
@ -1468,6 +1709,7 @@ pub const cpu = struct {
|
|||
.full_rate_64_ops,
|
||||
.gfx9,
|
||||
.gfx90a_insts,
|
||||
.image_insts,
|
||||
.ldsbankcount32,
|
||||
.mad_mac_f32_insts,
|
||||
.mai_insts,
|
||||
|
|
@ -1485,11 +1727,43 @@ pub const cpu = struct {
|
|||
.extended_image_insts,
|
||||
.gfx9,
|
||||
.image_gather4_d16_bug,
|
||||
.image_insts,
|
||||
.ldsbankcount32,
|
||||
.mad_mac_f32_insts,
|
||||
.mad_mix_insts,
|
||||
}),
|
||||
};
|
||||
pub const gfx940 = CpuModel{
|
||||
.name = "gfx940",
|
||||
.llvm_name = "gfx940",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.architected_flat_scratch,
|
||||
.atomic_fadd_no_rtn_insts,
|
||||
.atomic_fadd_rtn_insts,
|
||||
.atomic_pk_fadd_no_rtn_insts,
|
||||
.dl_insts,
|
||||
.dot1_insts,
|
||||
.dot2_insts,
|
||||
.dot3_insts,
|
||||
.dot4_insts,
|
||||
.dot5_insts,
|
||||
.dot6_insts,
|
||||
.dot7_insts,
|
||||
.dpp_64bit,
|
||||
.fma_mix_insts,
|
||||
.fp8_insts,
|
||||
.full_rate_64_ops,
|
||||
.gfx9,
|
||||
.gfx90a_insts,
|
||||
.gfx940_insts,
|
||||
.ldsbankcount32,
|
||||
.mai_insts,
|
||||
.packed_fp32_ops,
|
||||
.packed_tid,
|
||||
.pk_fmac_f16_inst,
|
||||
.sramecc_support,
|
||||
}),
|
||||
};
|
||||
pub const hainan = CpuModel{
|
||||
.name = "hainan",
|
||||
.llvm_name = "hainan",
|
||||
|
|
|
|||
|
|
@ -8,9 +8,12 @@ pub const Feature = enum {
|
|||
@"32bit",
|
||||
@"8msecext",
|
||||
a76,
|
||||
aapcs_frame_chain,
|
||||
aapcs_frame_chain_leaf,
|
||||
aclass,
|
||||
acquire_release,
|
||||
aes,
|
||||
atomics_32,
|
||||
avoid_movs_shop,
|
||||
avoid_partial_cpsr,
|
||||
bf16,
|
||||
|
|
@ -37,6 +40,7 @@ pub const Feature = enum {
|
|||
expand_fp_mlx,
|
||||
exynos,
|
||||
fix_cmse_cve_2021_35465,
|
||||
fix_cortex_a57_aes_1742098,
|
||||
fp16,
|
||||
fp16fml,
|
||||
fp64,
|
||||
|
|
@ -133,6 +137,7 @@ pub const Feature = enum {
|
|||
thumb2,
|
||||
thumb_mode,
|
||||
trustzone,
|
||||
use_mipipeliner,
|
||||
use_misched,
|
||||
v2,
|
||||
v2a,
|
||||
|
|
@ -218,6 +223,18 @@ pub const all_features = blk: {
|
|||
.description = "Cortex-A76 ARM processors",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.aapcs_frame_chain)] = .{
|
||||
.llvm_name = "aapcs-frame-chain",
|
||||
.description = "Create an AAPCS compliant frame chain",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.aapcs_frame_chain_leaf)] = .{
|
||||
.llvm_name = "aapcs-frame-chain-leaf",
|
||||
.description = "Create an AAPCS compliant frame chain for leaf functions",
|
||||
.dependencies = featureSet(&[_]Feature{
|
||||
.aapcs_frame_chain,
|
||||
}),
|
||||
};
|
||||
result[@enumToInt(Feature.aclass)] = .{
|
||||
.llvm_name = "aclass",
|
||||
.description = "Is application profile ('A' series)",
|
||||
|
|
@ -235,6 +252,11 @@ pub const all_features = blk: {
|
|||
.neon,
|
||||
}),
|
||||
};
|
||||
result[@enumToInt(Feature.atomics_32)] = .{
|
||||
.llvm_name = "atomics-32",
|
||||
.description = "Assume that lock-free 32-bit atomics are available",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.avoid_movs_shop)] = .{
|
||||
.llvm_name = "avoid-movs-shop",
|
||||
.description = "Avoid movs instructions with shifter operand",
|
||||
|
|
@ -408,6 +430,11 @@ pub const all_features = blk: {
|
|||
.description = "Mitigate against the cve-2021-35465 security vulnurability",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.fix_cortex_a57_aes_1742098)] = .{
|
||||
.llvm_name = "fix-cortex-a57-aes-1742098",
|
||||
.description = "Work around Cortex-A57 Erratum 1742098 / Cortex-A72 Erratum 1655431 (AES)",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.fp16)] = .{
|
||||
.llvm_name = "fp16",
|
||||
.description = "Enable half-precision floating point",
|
||||
|
|
@ -989,6 +1016,11 @@ pub const all_features = blk: {
|
|||
.description = "Enable support for TrustZone security extensions",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.use_mipipeliner)] = .{
|
||||
.llvm_name = "use-mipipeliner",
|
||||
.description = "Use the MachinePipeliner",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.use_misched)] = .{
|
||||
.llvm_name = "use-misched",
|
||||
.description = "Use the MachineScheduler",
|
||||
|
|
@ -1911,6 +1943,7 @@ pub const cpu = struct {
|
|||
.features = featureSet(&[_]Feature{
|
||||
.avoid_partial_cpsr,
|
||||
.cheap_predicable_cpsr,
|
||||
.fix_cortex_a57_aes_1742098,
|
||||
.fpao,
|
||||
.v8a,
|
||||
}),
|
||||
|
|
@ -1946,6 +1979,7 @@ pub const cpu = struct {
|
|||
.name = "cortex_a72",
|
||||
.llvm_name = "cortex-a72",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.fix_cortex_a57_aes_1742098,
|
||||
.v8a,
|
||||
}),
|
||||
};
|
||||
|
|
@ -2151,10 +2185,22 @@ pub const cpu = struct {
|
|||
.llvm_name = "cortex-m7",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.fp_armv8d16,
|
||||
.use_mipipeliner,
|
||||
.use_misched,
|
||||
.v7em,
|
||||
}),
|
||||
};
|
||||
pub const cortex_m85 = CpuModel{
|
||||
.name = "cortex_m85",
|
||||
.llvm_name = "cortex-m85",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.fp_armv8d16,
|
||||
.mve_fp,
|
||||
.pacbti,
|
||||
.use_misched,
|
||||
.v8_1m_main,
|
||||
}),
|
||||
};
|
||||
pub const cortex_r4 = CpuModel{
|
||||
.name = "cortex_r4",
|
||||
.llvm_name = "cortex-r4",
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@ pub const Feature = enum {
|
|||
sram,
|
||||
tinyencoding,
|
||||
xmega,
|
||||
xmega3,
|
||||
xmegau,
|
||||
};
|
||||
|
||||
|
|
@ -163,6 +164,7 @@ pub const all_features = blk: {
|
|||
.dependencies = featureSet(&[_]Feature{
|
||||
.avr0,
|
||||
.@"break",
|
||||
.smallstack,
|
||||
.sram,
|
||||
.tinyencoding,
|
||||
}),
|
||||
|
|
@ -302,6 +304,22 @@ pub const all_features = blk: {
|
|||
.sram,
|
||||
}),
|
||||
};
|
||||
result[@enumToInt(Feature.xmega3)] = .{
|
||||
.llvm_name = "xmega3",
|
||||
.description = "The device is a part of the xmega3 family",
|
||||
.dependencies = featureSet(&[_]Feature{
|
||||
.addsubiw,
|
||||
.avr0,
|
||||
.@"break",
|
||||
.ijmpcall,
|
||||
.jmpcall,
|
||||
.lpm,
|
||||
.lpmx,
|
||||
.movw,
|
||||
.mul,
|
||||
.sram,
|
||||
}),
|
||||
};
|
||||
result[@enumToInt(Feature.xmegau)] = .{
|
||||
.llvm_name = "xmegau",
|
||||
.description = "The device is a part of the xmegau family",
|
||||
|
|
@ -445,6 +463,7 @@ pub const cpu = struct {
|
|||
.llvm_name = "at90s1200",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr0,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const at90s2313 = CpuModel{
|
||||
|
|
@ -452,6 +471,7 @@ pub const cpu = struct {
|
|||
.llvm_name = "at90s2313",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr2,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const at90s2323 = CpuModel{
|
||||
|
|
@ -459,6 +479,7 @@ pub const cpu = struct {
|
|||
.llvm_name = "at90s2323",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr2,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const at90s2333 = CpuModel{
|
||||
|
|
@ -466,6 +487,7 @@ pub const cpu = struct {
|
|||
.llvm_name = "at90s2333",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr2,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const at90s2343 = CpuModel{
|
||||
|
|
@ -473,6 +495,7 @@ pub const cpu = struct {
|
|||
.llvm_name = "at90s2343",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr2,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const at90s4414 = CpuModel{
|
||||
|
|
@ -480,6 +503,7 @@ pub const cpu = struct {
|
|||
.llvm_name = "at90s4414",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr2,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const at90s4433 = CpuModel{
|
||||
|
|
@ -487,6 +511,7 @@ pub const cpu = struct {
|
|||
.llvm_name = "at90s4433",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr2,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const at90s4434 = CpuModel{
|
||||
|
|
@ -494,6 +519,7 @@ pub const cpu = struct {
|
|||
.llvm_name = "at90s4434",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr2,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const at90s8515 = CpuModel{
|
||||
|
|
@ -674,6 +700,13 @@ pub const cpu = struct {
|
|||
.avr5,
|
||||
}),
|
||||
};
|
||||
pub const ata6616c = CpuModel{
|
||||
.name = "ata6616c",
|
||||
.llvm_name = "ata6616c",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr25,
|
||||
}),
|
||||
};
|
||||
pub const ata6617c = CpuModel{
|
||||
.name = "ata6617c",
|
||||
.llvm_name = "ata6617c",
|
||||
|
|
@ -779,6 +812,20 @@ pub const cpu = struct {
|
|||
.avr5,
|
||||
}),
|
||||
};
|
||||
pub const atmega1608 = CpuModel{
|
||||
.name = "atmega1608",
|
||||
.llvm_name = "atmega1608",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const atmega1609 = CpuModel{
|
||||
.name = "atmega1609",
|
||||
.llvm_name = "atmega1609",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const atmega161 = CpuModel{
|
||||
.name = "atmega161",
|
||||
.llvm_name = "atmega161",
|
||||
|
|
@ -1011,6 +1058,20 @@ pub const cpu = struct {
|
|||
.avr5,
|
||||
}),
|
||||
};
|
||||
pub const atmega3208 = CpuModel{
|
||||
.name = "atmega3208",
|
||||
.llvm_name = "atmega3208",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const atmega3209 = CpuModel{
|
||||
.name = "atmega3209",
|
||||
.llvm_name = "atmega3209",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const atmega323 = CpuModel{
|
||||
.name = "atmega323",
|
||||
.llvm_name = "atmega323",
|
||||
|
|
@ -1249,6 +1310,20 @@ pub const cpu = struct {
|
|||
.avr4,
|
||||
}),
|
||||
};
|
||||
pub const atmega4808 = CpuModel{
|
||||
.name = "atmega4808",
|
||||
.llvm_name = "atmega4808",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const atmega4809 = CpuModel{
|
||||
.name = "atmega4809",
|
||||
.llvm_name = "atmega4809",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const atmega48a = CpuModel{
|
||||
.name = "atmega48a",
|
||||
.llvm_name = "atmega48a",
|
||||
|
|
@ -1463,6 +1538,20 @@ pub const cpu = struct {
|
|||
.spm,
|
||||
}),
|
||||
};
|
||||
pub const atmega808 = CpuModel{
|
||||
.name = "atmega808",
|
||||
.llvm_name = "atmega808",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const atmega809 = CpuModel{
|
||||
.name = "atmega809",
|
||||
.llvm_name = "atmega809",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const atmega8515 = CpuModel{
|
||||
.name = "atmega8515",
|
||||
.llvm_name = "atmega8515",
|
||||
|
|
@ -1571,6 +1660,7 @@ pub const cpu = struct {
|
|||
.llvm_name = "attiny11",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr1,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const attiny12 = CpuModel{
|
||||
|
|
@ -1578,6 +1668,7 @@ pub const cpu = struct {
|
|||
.llvm_name = "attiny12",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr1,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const attiny13 = CpuModel{
|
||||
|
|
@ -1585,6 +1676,7 @@ pub const cpu = struct {
|
|||
.llvm_name = "attiny13",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr25,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const attiny13a = CpuModel{
|
||||
|
|
@ -1592,6 +1684,7 @@ pub const cpu = struct {
|
|||
.llvm_name = "attiny13a",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr25,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const attiny15 = CpuModel{
|
||||
|
|
@ -1599,48 +1692,70 @@ pub const cpu = struct {
|
|||
.llvm_name = "attiny15",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr1,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const attiny1604 = CpuModel{
|
||||
.name = "attiny1604",
|
||||
.llvm_name = "attiny1604",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny1606 = CpuModel{
|
||||
.name = "attiny1606",
|
||||
.llvm_name = "attiny1606",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny1607 = CpuModel{
|
||||
.name = "attiny1607",
|
||||
.llvm_name = "attiny1607",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny1614 = CpuModel{
|
||||
.name = "attiny1614",
|
||||
.llvm_name = "attiny1614",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny1616 = CpuModel{
|
||||
.name = "attiny1616",
|
||||
.llvm_name = "attiny1616",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny1617 = CpuModel{
|
||||
.name = "attiny1617",
|
||||
.llvm_name = "attiny1617",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny1624 = CpuModel{
|
||||
.name = "attiny1624",
|
||||
.llvm_name = "attiny1624",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny1626 = CpuModel{
|
||||
.name = "attiny1626",
|
||||
.llvm_name = "attiny1626",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny1627 = CpuModel{
|
||||
.name = "attiny1627",
|
||||
.llvm_name = "attiny1627",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny1634 = CpuModel{
|
||||
|
|
@ -1668,28 +1783,28 @@ pub const cpu = struct {
|
|||
.name = "attiny202",
|
||||
.llvm_name = "attiny202",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny204 = CpuModel{
|
||||
.name = "attiny204",
|
||||
.llvm_name = "attiny204",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny212 = CpuModel{
|
||||
.name = "attiny212",
|
||||
.llvm_name = "attiny212",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny214 = CpuModel{
|
||||
.name = "attiny214",
|
||||
.llvm_name = "attiny214",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny22 = CpuModel{
|
||||
|
|
@ -1697,6 +1812,7 @@ pub const cpu = struct {
|
|||
.llvm_name = "attiny22",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr2,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const attiny2313 = CpuModel{
|
||||
|
|
@ -1704,6 +1820,7 @@ pub const cpu = struct {
|
|||
.llvm_name = "attiny2313",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr25,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const attiny2313a = CpuModel{
|
||||
|
|
@ -1711,6 +1828,7 @@ pub const cpu = struct {
|
|||
.llvm_name = "attiny2313a",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr25,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const attiny24 = CpuModel{
|
||||
|
|
@ -1718,6 +1836,7 @@ pub const cpu = struct {
|
|||
.llvm_name = "attiny24",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr25,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const attiny24a = CpuModel{
|
||||
|
|
@ -1725,6 +1844,7 @@ pub const cpu = struct {
|
|||
.llvm_name = "attiny24a",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr25,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const attiny25 = CpuModel{
|
||||
|
|
@ -1732,6 +1852,7 @@ pub const cpu = struct {
|
|||
.llvm_name = "attiny25",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr25,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const attiny26 = CpuModel{
|
||||
|
|
@ -1740,6 +1861,7 @@ pub const cpu = struct {
|
|||
.features = featureSet(&[_]Feature{
|
||||
.avr2,
|
||||
.lpmx,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const attiny261 = CpuModel{
|
||||
|
|
@ -1747,6 +1869,7 @@ pub const cpu = struct {
|
|||
.llvm_name = "attiny261",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr25,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const attiny261a = CpuModel{
|
||||
|
|
@ -1754,6 +1877,7 @@ pub const cpu = struct {
|
|||
.llvm_name = "attiny261a",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr25,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const attiny28 = CpuModel{
|
||||
|
|
@ -1761,20 +1885,21 @@ pub const cpu = struct {
|
|||
.llvm_name = "attiny28",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.avr1,
|
||||
.smallstack,
|
||||
}),
|
||||
};
|
||||
pub const attiny3216 = CpuModel{
|
||||
.name = "attiny3216",
|
||||
.llvm_name = "attiny3216",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny3217 = CpuModel{
|
||||
.name = "attiny3217",
|
||||
.llvm_name = "attiny3217",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny4 = CpuModel{
|
||||
|
|
@ -1795,49 +1920,49 @@ pub const cpu = struct {
|
|||
.name = "attiny402",
|
||||
.llvm_name = "attiny402",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny404 = CpuModel{
|
||||
.name = "attiny404",
|
||||
.llvm_name = "attiny404",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny406 = CpuModel{
|
||||
.name = "attiny406",
|
||||
.llvm_name = "attiny406",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny412 = CpuModel{
|
||||
.name = "attiny412",
|
||||
.llvm_name = "attiny412",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny414 = CpuModel{
|
||||
.name = "attiny414",
|
||||
.llvm_name = "attiny414",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny416 = CpuModel{
|
||||
.name = "attiny416",
|
||||
.llvm_name = "attiny416",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny417 = CpuModel{
|
||||
.name = "attiny417",
|
||||
.llvm_name = "attiny417",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny4313 = CpuModel{
|
||||
|
|
@ -1914,42 +2039,42 @@ pub const cpu = struct {
|
|||
.name = "attiny804",
|
||||
.llvm_name = "attiny804",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny806 = CpuModel{
|
||||
.name = "attiny806",
|
||||
.llvm_name = "attiny806",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny807 = CpuModel{
|
||||
.name = "attiny807",
|
||||
.llvm_name = "attiny807",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny814 = CpuModel{
|
||||
.name = "attiny814",
|
||||
.llvm_name = "attiny814",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny816 = CpuModel{
|
||||
.name = "attiny816",
|
||||
.llvm_name = "attiny816",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny817 = CpuModel{
|
||||
.name = "attiny817",
|
||||
.llvm_name = "attiny817",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const attiny828 = CpuModel{
|
||||
|
|
@ -2246,13 +2371,6 @@ pub const cpu = struct {
|
|||
.xmegau,
|
||||
}),
|
||||
};
|
||||
pub const atxmega32x1 = CpuModel{
|
||||
.name = "atxmega32x1",
|
||||
.llvm_name = "atxmega32x1",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
}),
|
||||
};
|
||||
pub const atxmega384c3 = CpuModel{
|
||||
.name = "atxmega384c3",
|
||||
.llvm_name = "atxmega384c3",
|
||||
|
|
@ -2439,7 +2557,7 @@ pub const cpu = struct {
|
|||
.name = "avrxmega3",
|
||||
.llvm_name = "avrxmega3",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.xmega,
|
||||
.xmega3,
|
||||
}),
|
||||
};
|
||||
pub const avrxmega4 = CpuModel{
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -46,6 +46,7 @@ pub const Feature = enum {
|
|||
htm,
|
||||
icbt,
|
||||
invariant_function_descriptors,
|
||||
isa_future_instructions,
|
||||
isa_v206_instructions,
|
||||
isa_v207_instructions,
|
||||
isa_v30_instructions,
|
||||
|
|
@ -354,6 +355,13 @@ pub const all_features = blk: {
|
|||
.description = "Assume function descriptors are invariant",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.isa_future_instructions)] = .{
|
||||
.llvm_name = "isa-future-instructions",
|
||||
.description = "Enable instructions for Future ISA.",
|
||||
.dependencies = featureSet(&[_]Feature{
|
||||
.isa_v31_instructions,
|
||||
}),
|
||||
};
|
||||
result[@enumToInt(Feature.isa_v206_instructions)] = .{
|
||||
.llvm_name = "isa-v206-instructions",
|
||||
.description = "Enable instructions in ISA 2.06.",
|
||||
|
|
@ -728,6 +736,7 @@ pub const cpu = struct {
|
|||
.frsqrte,
|
||||
.frsqrtes,
|
||||
.fsqrt,
|
||||
.isa_v206_instructions,
|
||||
.isel,
|
||||
.ldbrx,
|
||||
.lfiwax,
|
||||
|
|
@ -774,6 +783,7 @@ pub const cpu = struct {
|
|||
.allow_unaligned_fp_access,
|
||||
.bpermd,
|
||||
.cmpb,
|
||||
.crbits,
|
||||
.crypto,
|
||||
.direct_move,
|
||||
.extdiv,
|
||||
|
|
@ -793,6 +803,7 @@ pub const cpu = struct {
|
|||
.fuse_store,
|
||||
.htm,
|
||||
.icbt,
|
||||
.isa_future_instructions,
|
||||
.isa_v206_instructions,
|
||||
.isel,
|
||||
.ldbrx,
|
||||
|
|
@ -886,6 +897,7 @@ pub const cpu = struct {
|
|||
.allow_unaligned_fp_access,
|
||||
.bpermd,
|
||||
.cmpb,
|
||||
.crbits,
|
||||
.crypto,
|
||||
.direct_move,
|
||||
.extdiv,
|
||||
|
|
@ -925,6 +937,7 @@ pub const cpu = struct {
|
|||
.allow_unaligned_fp_access,
|
||||
.bpermd,
|
||||
.cmpb,
|
||||
.crbits,
|
||||
.crypto,
|
||||
.direct_move,
|
||||
.extdiv,
|
||||
|
|
@ -1096,6 +1109,7 @@ pub const cpu = struct {
|
|||
.allow_unaligned_fp_access,
|
||||
.bpermd,
|
||||
.cmpb,
|
||||
.crbits,
|
||||
.crypto,
|
||||
.direct_move,
|
||||
.extdiv,
|
||||
|
|
@ -1135,6 +1149,7 @@ pub const cpu = struct {
|
|||
.allow_unaligned_fp_access,
|
||||
.bpermd,
|
||||
.cmpb,
|
||||
.crbits,
|
||||
.crypto,
|
||||
.direct_move,
|
||||
.extdiv,
|
||||
|
|
|
|||
|
|
@ -16,8 +16,11 @@ pub const Feature = enum {
|
|||
experimental_zbp,
|
||||
experimental_zbr,
|
||||
experimental_zbt,
|
||||
experimental_zvfh,
|
||||
f,
|
||||
lui_addi_fusion,
|
||||
m,
|
||||
no_default_unroll,
|
||||
no_rvc_hints,
|
||||
relax,
|
||||
reserve_x1,
|
||||
|
|
@ -52,6 +55,7 @@ pub const Feature = enum {
|
|||
reserve_x8,
|
||||
reserve_x9,
|
||||
save_restore,
|
||||
unaligned_scalar_mem,
|
||||
v,
|
||||
zba,
|
||||
zbb,
|
||||
|
|
@ -66,6 +70,10 @@ pub const Feature = enum {
|
|||
zfinx,
|
||||
zhinx,
|
||||
zhinxmin,
|
||||
zicbom,
|
||||
zicbop,
|
||||
zicboz,
|
||||
zihintpause,
|
||||
zk,
|
||||
zkn,
|
||||
zknd,
|
||||
|
|
@ -76,6 +84,7 @@ pub const Feature = enum {
|
|||
zksed,
|
||||
zksh,
|
||||
zkt,
|
||||
zmmul,
|
||||
zve32f,
|
||||
zve32x,
|
||||
zve64d,
|
||||
|
|
@ -160,16 +169,33 @@ pub const all_features = blk: {
|
|||
.description = "'Zbt' (Ternary 'Zb' Instructions)",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.experimental_zvfh)] = .{
|
||||
.llvm_name = "experimental-zvfh",
|
||||
.description = "'Zvfh' (Vector Half-Precision Floating-Point)",
|
||||
.dependencies = featureSet(&[_]Feature{
|
||||
.zve32f,
|
||||
}),
|
||||
};
|
||||
result[@enumToInt(Feature.f)] = .{
|
||||
.llvm_name = "f",
|
||||
.description = "'F' (Single-Precision Floating-Point)",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.lui_addi_fusion)] = .{
|
||||
.llvm_name = "lui-addi-fusion",
|
||||
.description = "Enable LUI+ADDI macrofusion",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.m)] = .{
|
||||
.llvm_name = "m",
|
||||
.description = "'M' (Integer Multiplication and Division)",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.no_default_unroll)] = .{
|
||||
.llvm_name = "no-default-unroll",
|
||||
.description = "Disable default unroll preference.",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.no_rvc_hints)] = .{
|
||||
.llvm_name = "no-rvc-hints",
|
||||
.description = "Disable RVC Hint Instructions.",
|
||||
|
|
@ -340,11 +366,17 @@ pub const all_features = blk: {
|
|||
.description = "Enable save/restore.",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.unaligned_scalar_mem)] = .{
|
||||
.llvm_name = "unaligned-scalar-mem",
|
||||
.description = "Has reasonably performant unaligned scalar loads and stores",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.v)] = .{
|
||||
.llvm_name = "v",
|
||||
.description = "'V' (Vector Extension for Application Processors)",
|
||||
.dependencies = featureSet(&[_]Feature{
|
||||
.d,
|
||||
.zve64d,
|
||||
.zvl128b,
|
||||
}),
|
||||
};
|
||||
|
|
@ -423,6 +455,26 @@ pub const all_features = blk: {
|
|||
.zfinx,
|
||||
}),
|
||||
};
|
||||
result[@enumToInt(Feature.zicbom)] = .{
|
||||
.llvm_name = "zicbom",
|
||||
.description = "'Zicbom' (Cache-Block Management Instructions)",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.zicbop)] = .{
|
||||
.llvm_name = "zicbop",
|
||||
.description = "'Zicbop' (Cache-Block Prefetch Instructions)",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.zicboz)] = .{
|
||||
.llvm_name = "zicboz",
|
||||
.description = "'Zicboz' (Cache-Block Zero Instructions)",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.zihintpause)] = .{
|
||||
.llvm_name = "zihintpause",
|
||||
.description = "'zihintpause' (Pause Hint)",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.zk)] = .{
|
||||
.llvm_name = "zk",
|
||||
.description = "'Zk' (Standard scalar cryptography extension)",
|
||||
|
|
@ -490,6 +542,11 @@ pub const all_features = blk: {
|
|||
.description = "'Zkt' (Data Independent Execution Latency)",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.zmmul)] = .{
|
||||
.llvm_name = "zmmul",
|
||||
.description = "'Zmmul' (Integer Multiplication)",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.zve32f)] = .{
|
||||
.llvm_name = "zve32f",
|
||||
.description = "'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension)",
|
||||
|
|
@ -632,6 +689,11 @@ pub const cpu = struct {
|
|||
.m,
|
||||
}),
|
||||
};
|
||||
pub const generic = CpuModel{
|
||||
.name = "generic",
|
||||
.llvm_name = "generic",
|
||||
.features = featureSet(&[_]Feature{}),
|
||||
};
|
||||
pub const generic_rv32 = CpuModel{
|
||||
.name = "generic_rv32",
|
||||
.llvm_name = "generic-rv32",
|
||||
|
|
@ -659,13 +721,16 @@ pub const cpu = struct {
|
|||
pub const sifive_7_rv32 = CpuModel{
|
||||
.name = "sifive_7_rv32",
|
||||
.llvm_name = "sifive-7-rv32",
|
||||
.features = featureSet(&[_]Feature{}),
|
||||
.features = featureSet(&[_]Feature{
|
||||
.no_default_unroll,
|
||||
}),
|
||||
};
|
||||
pub const sifive_7_rv64 = CpuModel{
|
||||
.name = "sifive_7_rv64",
|
||||
.llvm_name = "sifive-7-rv64",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.@"64bit",
|
||||
.no_default_unroll,
|
||||
}),
|
||||
};
|
||||
pub const sifive_e20 = CpuModel{
|
||||
|
|
@ -722,6 +787,7 @@ pub const cpu = struct {
|
|||
.c,
|
||||
.f,
|
||||
.m,
|
||||
.no_default_unroll,
|
||||
}),
|
||||
};
|
||||
pub const sifive_s21 = CpuModel{
|
||||
|
|
@ -764,6 +830,7 @@ pub const cpu = struct {
|
|||
.c,
|
||||
.d,
|
||||
.m,
|
||||
.no_default_unroll,
|
||||
}),
|
||||
};
|
||||
pub const sifive_u54 = CpuModel{
|
||||
|
|
@ -786,6 +853,7 @@ pub const cpu = struct {
|
|||
.c,
|
||||
.d,
|
||||
.m,
|
||||
.no_default_unroll,
|
||||
}),
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -579,6 +579,52 @@ pub const cpu = struct {
|
|||
.vector_packed_decimal_enhancement,
|
||||
}),
|
||||
};
|
||||
pub const z16 = CpuModel{
|
||||
.name = "z16",
|
||||
.llvm_name = "z16",
|
||||
.features = featureSet(&[_]Feature{
|
||||
.bear_enhancement,
|
||||
.deflate_conversion,
|
||||
.dfp_packed_conversion,
|
||||
.dfp_zoned_conversion,
|
||||
.distinct_ops,
|
||||
.enhanced_dat_2,
|
||||
.enhanced_sort,
|
||||
.execution_hint,
|
||||
.fast_serialization,
|
||||
.fp_extension,
|
||||
.guarded_storage,
|
||||
.high_word,
|
||||
.insert_reference_bits_multiple,
|
||||
.interlocked_access1,
|
||||
.load_and_trap,
|
||||
.load_and_zero_rightmost_byte,
|
||||
.load_store_on_cond,
|
||||
.load_store_on_cond_2,
|
||||
.message_security_assist_extension3,
|
||||
.message_security_assist_extension4,
|
||||
.message_security_assist_extension5,
|
||||
.message_security_assist_extension7,
|
||||
.message_security_assist_extension8,
|
||||
.message_security_assist_extension9,
|
||||
.miscellaneous_extensions,
|
||||
.miscellaneous_extensions_2,
|
||||
.miscellaneous_extensions_3,
|
||||
.nnp_assist,
|
||||
.population_count,
|
||||
.processor_activity_instrumentation,
|
||||
.processor_assist,
|
||||
.reset_dat_protection,
|
||||
.reset_reference_bits_multiple,
|
||||
.transactional_execution,
|
||||
.vector,
|
||||
.vector_enhancements_1,
|
||||
.vector_enhancements_2,
|
||||
.vector_packed_decimal,
|
||||
.vector_packed_decimal_enhancement,
|
||||
.vector_packed_decimal_enhancement_2,
|
||||
}),
|
||||
};
|
||||
pub const z196 = CpuModel{
|
||||
.name = "z196",
|
||||
.llvm_name = "z196",
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@ pub const Feature = enum {
|
|||
atomics,
|
||||
bulk_memory,
|
||||
exception_handling,
|
||||
extended_const,
|
||||
multivalue,
|
||||
mutable_globals,
|
||||
nontrapping_fptoint,
|
||||
|
|
@ -42,6 +43,11 @@ pub const all_features = blk: {
|
|||
.description = "Enable Wasm exception handling",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.extended_const)] = .{
|
||||
.llvm_name = "extended-const",
|
||||
.description = "Enable extended const expressions",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.multivalue)] = .{
|
||||
.llvm_name = "multivalue",
|
||||
.description = "Enable multivalue blocks, instructions, and functions",
|
||||
|
|
|
|||
|
|
@ -48,8 +48,13 @@ pub const Feature = enum {
|
|||
enqcmd,
|
||||
ermsb,
|
||||
f16c,
|
||||
false_deps_getmant,
|
||||
false_deps_lzcnt_tzcnt,
|
||||
false_deps_mulc,
|
||||
false_deps_mullq,
|
||||
false_deps_perm,
|
||||
false_deps_popcnt,
|
||||
false_deps_range,
|
||||
fast_11bytenop,
|
||||
fast_15bytenop,
|
||||
fast_7bytenop,
|
||||
|
|
@ -71,6 +76,8 @@ pub const Feature = enum {
|
|||
fsrm,
|
||||
fxsr,
|
||||
gfni,
|
||||
harden_sls_ijmp,
|
||||
harden_sls_ret,
|
||||
hreset,
|
||||
idivl_to_divb,
|
||||
idivq_to_divl,
|
||||
|
|
@ -101,6 +108,7 @@ pub const Feature = enum {
|
|||
prfchw,
|
||||
ptwrite,
|
||||
rdpid,
|
||||
rdpru,
|
||||
rdrnd,
|
||||
rdseed,
|
||||
retpoline,
|
||||
|
|
@ -109,6 +117,7 @@ pub const Feature = enum {
|
|||
retpoline_indirect_calls,
|
||||
rtm,
|
||||
sahf,
|
||||
sbb_dep_breaking,
|
||||
serialize,
|
||||
seses,
|
||||
sgx,
|
||||
|
|
@ -136,7 +145,6 @@ pub const Feature = enum {
|
|||
tbm,
|
||||
tsxldtrk,
|
||||
uintr,
|
||||
use_aa,
|
||||
use_glm_div_sqrt_costs,
|
||||
use_slm_arith_costs,
|
||||
vaes,
|
||||
|
|
@ -376,7 +384,7 @@ pub const all_features = blk: {
|
|||
};
|
||||
result[@enumToInt(Feature.cldemote)] = .{
|
||||
.llvm_name = "cldemote",
|
||||
.description = "Enable Cache Demote",
|
||||
.description = "Enable Cache Line Demote",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.clflushopt)] = .{
|
||||
|
|
@ -401,12 +409,12 @@ pub const all_features = blk: {
|
|||
};
|
||||
result[@enumToInt(Feature.crc32)] = .{
|
||||
.llvm_name = "crc32",
|
||||
.description = "Enable SSE 4.2 CRC32 instruction",
|
||||
.description = "Enable SSE 4.2 CRC32 instruction (used when SSE4.2 is supported but function is GPR only)",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.cx16)] = .{
|
||||
.llvm_name = "cx16",
|
||||
.description = "64-bit with cmpxchg16b",
|
||||
.description = "64-bit with cmpxchg16b (this is true for most x86-64 chips, but not the first AMD chips)",
|
||||
.dependencies = featureSet(&[_]Feature{
|
||||
.cx8,
|
||||
}),
|
||||
|
|
@ -433,16 +441,41 @@ pub const all_features = blk: {
|
|||
.avx,
|
||||
}),
|
||||
};
|
||||
result[@enumToInt(Feature.false_deps_getmant)] = .{
|
||||
.llvm_name = "false-deps-getmant",
|
||||
.description = "VGETMANTSS/SD/SH and VGETMANDPS/PD(memory version) has a false dependency on dest register",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.false_deps_lzcnt_tzcnt)] = .{
|
||||
.llvm_name = "false-deps-lzcnt-tzcnt",
|
||||
.description = "LZCNT/TZCNT have a false dependency on dest register",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.false_deps_mulc)] = .{
|
||||
.llvm_name = "false-deps-mulc",
|
||||
.description = "VF[C]MULCPH/SH has a false dependency on dest register",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.false_deps_mullq)] = .{
|
||||
.llvm_name = "false-deps-mullq",
|
||||
.description = "VPMULLQ has a false dependency on dest register",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.false_deps_perm)] = .{
|
||||
.llvm_name = "false-deps-perm",
|
||||
.description = "VPERMD/Q/PS/PD has a false dependency on dest register",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.false_deps_popcnt)] = .{
|
||||
.llvm_name = "false-deps-popcnt",
|
||||
.description = "POPCNT has a false dependency on dest register",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.false_deps_range)] = .{
|
||||
.llvm_name = "false-deps-range",
|
||||
.description = "VRANGEPD/PS/SD/SS has a false dependency on dest register",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.fast_11bytenop)] = .{
|
||||
.llvm_name = "fast-11bytenop",
|
||||
.description = "Target can quickly decode up to 11 byte NOPs",
|
||||
|
|
@ -465,7 +498,7 @@ pub const all_features = blk: {
|
|||
};
|
||||
result[@enumToInt(Feature.fast_gather)] = .{
|
||||
.llvm_name = "fast-gather",
|
||||
.description = "Indicates if gather is reasonably fast",
|
||||
.description = "Indicates if gather is reasonably fast (this is true for Skylake client and all AVX-512 CPUs)",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.fast_hops)] = .{
|
||||
|
|
@ -555,6 +588,16 @@ pub const all_features = blk: {
|
|||
.sse2,
|
||||
}),
|
||||
};
|
||||
result[@enumToInt(Feature.harden_sls_ijmp)] = .{
|
||||
.llvm_name = "harden-sls-ijmp",
|
||||
.description = "Harden against straight line speculation across indirect JMP instructions.",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.harden_sls_ret)] = .{
|
||||
.llvm_name = "harden-sls-ret",
|
||||
.description = "Harden against straight line speculation across RET instructions.",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.hreset)] = .{
|
||||
.llvm_name = "hreset",
|
||||
.description = "Has hreset instruction",
|
||||
|
|
@ -584,7 +627,7 @@ pub const all_features = blk: {
|
|||
};
|
||||
result[@enumToInt(Feature.lea_sp)] = .{
|
||||
.llvm_name = "lea-sp",
|
||||
.description = "Use LEA for adjusting the stack pointer",
|
||||
.description = "Use LEA for adjusting the stack pointer (this is an optimization for Intel Atom processors)",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.lea_uses_ag)] = .{
|
||||
|
|
@ -629,12 +672,12 @@ pub const all_features = blk: {
|
|||
};
|
||||
result[@enumToInt(Feature.movdir64b)] = .{
|
||||
.llvm_name = "movdir64b",
|
||||
.description = "Support movdir64b instruction",
|
||||
.description = "Support movdir64b instruction (direct store 64 bytes)",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.movdiri)] = .{
|
||||
.llvm_name = "movdiri",
|
||||
.description = "Support movdiri instruction",
|
||||
.description = "Support movdiri instruction (direct store integer)",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.mwaitx)] = .{
|
||||
|
|
@ -644,12 +687,12 @@ pub const all_features = blk: {
|
|||
};
|
||||
result[@enumToInt(Feature.nopl)] = .{
|
||||
.llvm_name = "nopl",
|
||||
.description = "Enable NOPL instruction",
|
||||
.description = "Enable NOPL instruction (generally pentium pro+)",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.pad_short_functions)] = .{
|
||||
.llvm_name = "pad-short-functions",
|
||||
.description = "Pad short functions",
|
||||
.description = "Pad short functions (to prevent a stall when returning too early)",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.pclmul)] = .{
|
||||
|
|
@ -709,6 +752,11 @@ pub const all_features = blk: {
|
|||
.description = "Support RDPID instructions",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.rdpru)] = .{
|
||||
.llvm_name = "rdpru",
|
||||
.description = "Support RDPRU instructions",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.rdrnd)] = .{
|
||||
.llvm_name = "rdrnd",
|
||||
.description = "Support RDRAND instruction",
|
||||
|
|
@ -754,6 +802,11 @@ pub const all_features = blk: {
|
|||
.description = "Support LAHF and SAHF instructions in 64-bit mode",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.sbb_dep_breaking)] = .{
|
||||
.llvm_name = "sbb-dep-breaking",
|
||||
.description = "SBB with same register has no source dependency",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.serialize)] = .{
|
||||
.llvm_name = "serialize",
|
||||
.description = "Has serialize instruction",
|
||||
|
|
@ -805,7 +858,7 @@ pub const all_features = blk: {
|
|||
};
|
||||
result[@enumToInt(Feature.slow_pmulld)] = .{
|
||||
.llvm_name = "slow-pmulld",
|
||||
.description = "PMULLD instruction is slow",
|
||||
.description = "PMULLD instruction is slow (compared to PMULLW/PMULHW and PMULUDQ)",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.slow_shld)] = .{
|
||||
|
|
@ -875,7 +928,7 @@ pub const all_features = blk: {
|
|||
};
|
||||
result[@enumToInt(Feature.sse_unaligned_mem)] = .{
|
||||
.llvm_name = "sse-unaligned-mem",
|
||||
.description = "Allow unaligned memory operands with SSE instructions",
|
||||
.description = "Allow unaligned memory operands with SSE instructions (this may require setting a configuration bit in the processor)",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.ssse3)] = .{
|
||||
|
|
@ -905,11 +958,6 @@ pub const all_features = blk: {
|
|||
.description = "Has UINTR Instructions",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.use_aa)] = .{
|
||||
.llvm_name = "use-aa",
|
||||
.description = "Use alias analysis during codegen",
|
||||
.dependencies = featureSet(&[_]Feature{}),
|
||||
};
|
||||
result[@enumToInt(Feature.use_glm_div_sqrt_costs)] = .{
|
||||
.llvm_name = "use-glm-div-sqrt-costs",
|
||||
.description = "Use Goldmont specific floating point div/sqrt costs",
|
||||
|
|
@ -1021,6 +1069,7 @@ pub const cpu = struct {
|
|||
.crc32,
|
||||
.cx16,
|
||||
.f16c,
|
||||
.false_deps_perm,
|
||||
.false_deps_popcnt,
|
||||
.fast_15bytenop,
|
||||
.fast_gather,
|
||||
|
|
@ -1082,6 +1131,7 @@ pub const cpu = struct {
|
|||
.popcnt,
|
||||
.prfchw,
|
||||
.sahf,
|
||||
.sbb_dep_breaking,
|
||||
.slow_shld,
|
||||
.sse4a,
|
||||
.vzeroupper,
|
||||
|
|
@ -1113,6 +1163,7 @@ pub const cpu = struct {
|
|||
.fast_scalar_shift_masks,
|
||||
.fxsr,
|
||||
.nopl,
|
||||
.sbb_dep_breaking,
|
||||
.slow_shld,
|
||||
.slow_unaligned_mem_16,
|
||||
.sse2,
|
||||
|
|
@ -1131,6 +1182,7 @@ pub const cpu = struct {
|
|||
.fast_scalar_shift_masks,
|
||||
.fxsr,
|
||||
.nopl,
|
||||
.sbb_dep_breaking,
|
||||
.slow_shld,
|
||||
.slow_unaligned_mem_16,
|
||||
.sse3,
|
||||
|
|
@ -1165,6 +1217,7 @@ pub const cpu = struct {
|
|||
.fast_scalar_shift_masks,
|
||||
.fxsr,
|
||||
.nopl,
|
||||
.sbb_dep_breaking,
|
||||
.slow_shld,
|
||||
.slow_unaligned_mem_16,
|
||||
.sse2,
|
||||
|
|
@ -1257,6 +1310,7 @@ pub const cpu = struct {
|
|||
.popcnt,
|
||||
.prfchw,
|
||||
.sahf,
|
||||
.sbb_dep_breaking,
|
||||
.slow_shld,
|
||||
.sse4a,
|
||||
.vzeroupper,
|
||||
|
|
@ -1284,6 +1338,7 @@ pub const cpu = struct {
|
|||
.popcnt,
|
||||
.prfchw,
|
||||
.sahf,
|
||||
.sbb_dep_breaking,
|
||||
.slow_shld,
|
||||
.vzeroupper,
|
||||
.x87,
|
||||
|
|
@ -1317,6 +1372,7 @@ pub const cpu = struct {
|
|||
.popcnt,
|
||||
.prfchw,
|
||||
.sahf,
|
||||
.sbb_dep_breaking,
|
||||
.slow_shld,
|
||||
.tbm,
|
||||
.vzeroupper,
|
||||
|
|
@ -1352,6 +1408,7 @@ pub const cpu = struct {
|
|||
.popcnt,
|
||||
.prfchw,
|
||||
.sahf,
|
||||
.sbb_dep_breaking,
|
||||
.slow_shld,
|
||||
.tbm,
|
||||
.vzeroupper,
|
||||
|
|
@ -1392,6 +1449,7 @@ pub const cpu = struct {
|
|||
.prfchw,
|
||||
.rdrnd,
|
||||
.sahf,
|
||||
.sbb_dep_breaking,
|
||||
.slow_shld,
|
||||
.tbm,
|
||||
.vzeroupper,
|
||||
|
|
@ -1484,6 +1542,7 @@ pub const cpu = struct {
|
|||
.popcnt,
|
||||
.prfchw,
|
||||
.sahf,
|
||||
.sbb_dep_breaking,
|
||||
.slow_shld,
|
||||
.sse4a,
|
||||
.ssse3,
|
||||
|
|
@ -1518,6 +1577,7 @@ pub const cpu = struct {
|
|||
.popcnt,
|
||||
.prfchw,
|
||||
.sahf,
|
||||
.sbb_dep_breaking,
|
||||
.slow_shld,
|
||||
.sse4a,
|
||||
.x87,
|
||||
|
|
@ -1847,10 +1907,11 @@ pub const cpu = struct {
|
|||
.features = featureSet(&[_]Feature{
|
||||
.@"64bit",
|
||||
.cx8,
|
||||
.fast_15bytenop,
|
||||
.fast_scalar_fsqrt,
|
||||
.idivq_to_divl,
|
||||
.macrofusion,
|
||||
.slow_3ops_lea,
|
||||
.slow_incdec,
|
||||
.vzeroupper,
|
||||
.x87,
|
||||
}),
|
||||
|
|
@ -2213,6 +2274,7 @@ pub const cpu = struct {
|
|||
.fast_scalar_shift_masks,
|
||||
.fxsr,
|
||||
.nopl,
|
||||
.sbb_dep_breaking,
|
||||
.slow_shld,
|
||||
.slow_unaligned_mem_16,
|
||||
.sse2,
|
||||
|
|
@ -2231,6 +2293,7 @@ pub const cpu = struct {
|
|||
.fast_scalar_shift_masks,
|
||||
.fxsr,
|
||||
.nopl,
|
||||
.sbb_dep_breaking,
|
||||
.slow_shld,
|
||||
.slow_unaligned_mem_16,
|
||||
.sse3,
|
||||
|
|
@ -2375,6 +2438,7 @@ pub const cpu = struct {
|
|||
.fast_scalar_shift_masks,
|
||||
.fxsr,
|
||||
.nopl,
|
||||
.sbb_dep_breaking,
|
||||
.slow_shld,
|
||||
.slow_unaligned_mem_16,
|
||||
.sse2,
|
||||
|
|
@ -2393,6 +2457,7 @@ pub const cpu = struct {
|
|||
.fast_scalar_shift_masks,
|
||||
.fxsr,
|
||||
.nopl,
|
||||
.sbb_dep_breaking,
|
||||
.slow_shld,
|
||||
.slow_unaligned_mem_16,
|
||||
.sse3,
|
||||
|
|
@ -2671,6 +2736,11 @@ pub const cpu = struct {
|
|||
.cx16,
|
||||
.enqcmd,
|
||||
.ermsb,
|
||||
.false_deps_getmant,
|
||||
.false_deps_mulc,
|
||||
.false_deps_mullq,
|
||||
.false_deps_perm,
|
||||
.false_deps_range,
|
||||
.fast_15bytenop,
|
||||
.fast_gather,
|
||||
.fast_scalar_fsqrt,
|
||||
|
|
@ -3231,6 +3301,7 @@ pub const cpu = struct {
|
|||
.fast_movbe,
|
||||
.fast_scalar_fsqrt,
|
||||
.fast_scalar_shift_masks,
|
||||
.fast_variable_perlane_shuffle,
|
||||
.fast_vector_fsqrt,
|
||||
.fma,
|
||||
.fsgsbase,
|
||||
|
|
@ -3246,6 +3317,7 @@ pub const cpu = struct {
|
|||
.rdrnd,
|
||||
.rdseed,
|
||||
.sahf,
|
||||
.sbb_dep_breaking,
|
||||
.sha,
|
||||
.slow_shld,
|
||||
.sse4a,
|
||||
|
|
@ -3280,6 +3352,7 @@ pub const cpu = struct {
|
|||
.fast_movbe,
|
||||
.fast_scalar_fsqrt,
|
||||
.fast_scalar_shift_masks,
|
||||
.fast_variable_perlane_shuffle,
|
||||
.fast_vector_fsqrt,
|
||||
.fma,
|
||||
.fsgsbase,
|
||||
|
|
@ -3293,9 +3366,11 @@ pub const cpu = struct {
|
|||
.popcnt,
|
||||
.prfchw,
|
||||
.rdpid,
|
||||
.rdpru,
|
||||
.rdrnd,
|
||||
.rdseed,
|
||||
.sahf,
|
||||
.sbb_dep_breaking,
|
||||
.sha,
|
||||
.slow_shld,
|
||||
.sse4a,
|
||||
|
|
@ -3347,9 +3422,11 @@ pub const cpu = struct {
|
|||
.popcnt,
|
||||
.prfchw,
|
||||
.rdpid,
|
||||
.rdpru,
|
||||
.rdrnd,
|
||||
.rdseed,
|
||||
.sahf,
|
||||
.sbb_dep_breaking,
|
||||
.sha,
|
||||
.slow_shld,
|
||||
.sse4a,
|
||||
|
|
|
|||
|
|
@ -50,6 +50,10 @@ const llvm_targets = [_]LlvmTarget{
|
|||
.td_name = "AArch64.td",
|
||||
.branch_quota = 2000,
|
||||
.feature_overrides = &.{
|
||||
.{
|
||||
.llvm_name = "all",
|
||||
.omit = true,
|
||||
},
|
||||
.{
|
||||
.llvm_name = "v8a",
|
||||
.extra_deps = &.{ "fp_armv8", "neon" },
|
||||
|
|
@ -81,13 +85,12 @@ const llvm_targets = [_]LlvmTarget{
|
|||
},
|
||||
.{
|
||||
.llvm_name = "exynosm3",
|
||||
.zig_name = "exynos_m3",
|
||||
.flatten = true,
|
||||
.extra_deps = &.{"v8a"},
|
||||
},
|
||||
.{
|
||||
.llvm_name = "exynosm4",
|
||||
.zig_name = "exynos_m4",
|
||||
.flatten = true,
|
||||
},
|
||||
.{
|
||||
.llvm_name = "v8.1a",
|
||||
|
|
@ -300,6 +303,18 @@ const llvm_targets = [_]LlvmTarget{
|
|||
.llvm_name = "dumpcode",
|
||||
.omit = true,
|
||||
},
|
||||
.{
|
||||
.llvm_name = "enable-ds128",
|
||||
.zig_name = "ds128",
|
||||
},
|
||||
.{
|
||||
.llvm_name = "enable-flat-scratch",
|
||||
.zig_name = "flat_scratch",
|
||||
},
|
||||
.{
|
||||
.llvm_name = "enable-prt-strict-null",
|
||||
.zig_name = "prt_strict_null",
|
||||
},
|
||||
},
|
||||
},
|
||||
.{
|
||||
|
|
@ -934,7 +949,7 @@ fn processOneTarget(job: Job) anyerror!void {
|
|||
const child_result = try std.ChildProcess.exec(.{
|
||||
.allocator = arena,
|
||||
.argv = &child_args,
|
||||
.max_output_bytes = 200 * 1024 * 1024,
|
||||
.max_output_bytes = 400 * 1024 * 1024,
|
||||
});
|
||||
tblgen_progress.end();
|
||||
if (child_result.stderr.len != 0) {
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue