diff --git a/lib/compiler/aro/aro/Compilation.zig b/lib/compiler/aro/aro/Compilation.zig
index d03f5dc997..21d6823253 100644
--- a/lib/compiler/aro/aro/Compilation.zig
+++ b/lib/compiler/aro/aro/Compilation.zig
@@ -363,7 +363,7 @@ fn generateSystemDefines(comp: *Compilation, w: anytype) !void {
             \\#define __sparc_v9__ 1
             \\
         ),
-        .sparc, .sparcel => try w.writeAll(
+        .sparc => try w.writeAll(
             \\#define __sparc__ 1
             \\#define __sparc 1
             \\
@@ -534,7 +534,7 @@ pub fn generateBuiltinMacros(comp: *Compilation, system_defines_mode: SystemDefi
 
     if (system_defines_mode == .include_system_defines) {
         try buf.appendSlice(
-            \\#define __VERSION__ "Aro 
+            \\#define __VERSION__ "Aro
         ++ @import("../backend.zig").version_str ++ "\"\n" ++
             \\#define __Aro__
             \\
diff --git a/lib/compiler/aro/aro/Driver/GCCDetector.zig b/lib/compiler/aro/aro/Driver/GCCDetector.zig
index d13a63985d..720254316e 100644
--- a/lib/compiler/aro/aro/Driver/GCCDetector.zig
+++ b/lib/compiler/aro/aro/Driver/GCCDetector.zig
@@ -376,7 +376,7 @@ fn collectLibDirsAndTriples(
             biarch_libdirs.appendSliceAssumeCapacity(&RISCV32LibDirs);
             biarch_triple_aliases.appendSliceAssumeCapacity(&RISCV32Triples);
         },
-        .sparc, .sparcel => {
+        .sparc => {
             lib_dirs.appendSliceAssumeCapacity(&SPARCv8LibDirs);
             triple_aliases.appendSliceAssumeCapacity(&SPARCv8Triples);
             biarch_libdirs.appendSliceAssumeCapacity(&SPARCv9LibDirs);
diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig
index 5822801036..1035bbaf7a 100644
--- a/lib/compiler/aro/aro/target.zig
+++ b/lib/compiler/aro/aro/target.zig
@@ -58,7 +58,7 @@ pub fn intPtrType(target: std.Target) Type {
         .avr,
         => return .{ .specifier = .int },
 
-        .sparc, .sparcel => switch (target.os.tag) {
+        .sparc => switch (target.os.tag) {
             .netbsd, .openbsd => {},
             else => return .{ .specifier = .int },
         },
@@ -132,7 +132,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u8 {
     return switch (target.cpu.arch) {
         .arm, .armeb => 4,
         .aarch64, .aarch64_be => 4,
-        .sparc, .sparcel, .sparc64 => 4,
+        .sparc, .sparc64 => 4,
         .riscv64 => 2,
         else => 1,
     };
@@ -426,7 +426,7 @@ pub fn ldEmulationOption(target: std.Target, arm_endianness: ?std.builtin.Endian
         .powerpc64le => "elf64lppc",
         .riscv32 => "elf32lriscv",
         .riscv64 => "elf64lriscv",
-        .sparc, .sparcel => "elf32_sparc",
+        .sparc => "elf32_sparc",
         .sparc64 => "elf64_sparc",
         .loongarch32 => "elf32loongarch",
         .loongarch64 => "elf64loongarch",
@@ -466,7 +466,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
         .powerpcle,
         .riscv32,
         .sparc,
-        .sparcel,
         .thumb,
         .thumbeb,
         .x86,
@@ -510,7 +509,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
         .lanai,
         .m68k,
         .msp430,
-        .sparcel,
         .spu_2,
         .xcore,
         .xtensa,
@@ -592,7 +590,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
         .riscv64 => "riscv64",
         .sparc => "sparc",
         .sparc64 => "sparc64",
-        .sparcel => "sparcel",
         .s390x => "s390x",
         .thumb => "thumb",
         .thumbeb => "thumbeb",
diff --git a/lib/compiler/aro/aro/toolchains/Linux.zig b/lib/compiler/aro/aro/toolchains/Linux.zig
index f166e9e683..36ab916b10 100644
--- a/lib/compiler/aro/aro/toolchains/Linux.zig
+++ b/lib/compiler/aro/aro/toolchains/Linux.zig
@@ -357,7 +357,6 @@ fn getOSLibDir(target: std.Target) []const u8 {
         .powerpc,
         .powerpcle,
         .sparc,
-        .sparcel,
         => return "lib32",
         else => {},
     }
diff --git a/lib/compiler_rt/atomics.zig b/lib/compiler_rt/atomics.zig
index 77519ee9a7..e82b6ab055 100644
--- a/lib/compiler_rt/atomics.zig
+++ b/lib/compiler_rt/atomics.zig
@@ -30,7 +30,7 @@ const largest_atomic_size = switch (arch) {
     // On SPARC systems that lacks CAS and/or swap instructions, the only
     // available atomic operation is a test-and-set (`ldstub`), so we force
     // every atomic memory access to go through the lock.
-    .sparc, .sparcel => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
+    .sparc => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
 
     // XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b
     // and set this parameter accordingly.
diff --git a/lib/compiler_rt/clear_cache.zig b/lib/compiler_rt/clear_cache.zig
index a5740c63fe..5e5f202928 100644
--- a/lib/compiler_rt/clear_cache.zig
+++ b/lib/compiler_rt/clear_cache.zig
@@ -41,7 +41,7 @@ fn clear_cache(start: usize, end: usize) callconv(.C) void {
         else => false,
     };
     const sparc = switch (arch) {
-        .sparc, .sparc64, .sparcel => true,
+        .sparc, .sparc64 => true,
         else => false,
     };
     const apple = switch (os) {
diff --git a/lib/std/Target.zig b/lib/std/Target.zig
index d76eb885c0..729b7ff2ce 100644
--- a/lib/std/Target.zig
+++ b/lib/std/Target.zig
@@ -201,7 +201,7 @@ pub const Os = struct {
                     .mips, .mipsel, .mips64, .mips64el => "mips",
                     .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
                     .riscv32, .riscv64 => "riscv",
-                    .sparc, .sparcel, .sparc64 => "sparc",
+                    .sparc, .sparc64 => "sparc",
                     .x86, .x86_64 => "x86",
                     else => @tagName(arch),
                 },
@@ -1017,7 +1017,6 @@ pub const Cpu = struct {
         riscv64,
         sparc,
         sparc64,
-        sparcel,
         s390x,
         thumb,
         thumbeb,
@@ -1040,6 +1039,7 @@ pub const Cpu = struct {
         // LLVM tags deliberately omitted:
         // - aarch64_32
         // - r600
+        // - sparcel
         // - le32
         // - le64
         // - amdil
@@ -1121,7 +1121,7 @@ pub const Cpu = struct {
 
         pub inline fn isSPARC(arch: Arch) bool {
             return switch (arch) {
-                .sparc, .sparcel, .sparc64 => true,
+                .sparc, .sparc64 => true,
                 else => false,
             };
         }
@@ -1171,7 +1171,6 @@ pub const Cpu = struct {
                 .powerpc, .powerpcle => .PPC,
                 .riscv32 => .RISCV,
                 .sparc => .SPARC,
-                .sparcel => .SPARC,
                 .thumb => .ARM,
                 .thumbeb => .ARM,
                 .x86 => .@"386",
@@ -1222,7 +1221,6 @@ pub const Cpu = struct {
                 .powerpc, .powerpcle => .POWERPC,
                 .riscv32 => .RISCV32,
                 .sparc => .Unknown,
-                .sparcel => .Unknown,
                 .thumb => .Thumb,
                 .thumbeb => .Thumb,
                 .x86 => .I386,
@@ -1274,7 +1272,6 @@ pub const Cpu = struct {
                 .msp430,
                 .nvptx,
                 .nvptx64,
-                .sparcel,
                 .powerpcle,
                 .powerpc64le,
                 .riscv32,
@@ -1341,7 +1338,7 @@ pub const Cpu = struct {
                 .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
                 .amdgcn => "amdgpu",
                 .riscv32, .riscv64 => "riscv",
-                .sparc, .sparc64, .sparcel => "sparc",
+                .sparc, .sparc64 => "sparc",
                 .s390x => "s390x",
                 .x86, .x86_64 => "x86",
                 .nvptx, .nvptx64 => "nvptx",
@@ -1368,7 +1365,7 @@ pub const Cpu = struct {
                 .powerpc, .powerpcle, .powerpc64, .powerpc64le => &powerpc.all_features,
                 .amdgcn => &amdgpu.all_features,
                 .riscv32, .riscv64 => &riscv.all_features,
-                .sparc, .sparc64, .sparcel => &sparc.all_features,
+                .sparc, .sparc64 => &sparc.all_features,
                 .spirv32, .spirv64 => &spirv.all_features,
                 .s390x => &s390x.all_features,
                 .x86, .x86_64 => &x86.all_features,
@@ -1398,7 +1395,7 @@ pub const Cpu = struct {
                 .powerpc, .powerpcle, .powerpc64, .powerpc64le => comptime allCpusFromDecls(powerpc.cpu),
                 .amdgcn => comptime allCpusFromDecls(amdgpu.cpu),
                 .riscv32, .riscv64 => comptime allCpusFromDecls(riscv.cpu),
-                .sparc, .sparc64, .sparcel => comptime allCpusFromDecls(sparc.cpu),
+                .sparc, .sparc64 => comptime allCpusFromDecls(sparc.cpu),
                 .spirv32, .spirv64 => comptime allCpusFromDecls(spirv.cpu),
                 .s390x => comptime allCpusFromDecls(s390x.cpu),
                 .x86, .x86_64 => comptime allCpusFromDecls(x86.cpu),
@@ -1490,7 +1487,7 @@ pub const Cpu = struct {
                 .riscv32 => &riscv.cpu.generic_rv32,
                 .riscv64 => &riscv.cpu.generic_rv64,
                 .spirv32, .spirv64 => &spirv.cpu.generic,
-                .sparc, .sparcel => &sparc.cpu.generic,
+                .sparc => &sparc.cpu.generic,
                 .sparc64 => &sparc.cpu.v9, // 64-bit SPARC needs v9 as the baseline
                 .s390x => &s390x.cpu.generic,
                 .x86 => &x86.cpu.i386,
@@ -1511,7 +1508,7 @@ pub const Cpu = struct {
                 .x86 => &x86.cpu.pentium4,
                 .nvptx, .nvptx64 => &nvptx.cpu.sm_20,
                 .s390x => &s390x.cpu.arch8,
-                .sparc, .sparcel => &sparc.cpu.v8,
+                .sparc => &sparc.cpu.v8,
                 .loongarch64 => &loongarch.cpu.loongarch64,
 
                 else => generic(arch),
@@ -1696,7 +1693,6 @@ pub const DynamicLinker = struct {
             .linux => switch (cpu.arch) {
                 .x86,
                 .sparc,
-                .sparcel,
                 => init("/lib/ld-linux.so.2"),
 
                 .aarch64 => init("/lib/ld-linux-aarch64.so.1"),
@@ -1854,7 +1850,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
         .powerpc,
         .powerpcle,
         .riscv32,
-        .sparcel,
         .thumb,
         .thumbeb,
         .x86,
@@ -1914,7 +1909,6 @@ pub fn stackAlignment(target: Target) u16 {
         .mips,
         .mipsel,
         .sparc,
-        .sparcel,
         => 8,
         .aarch64,
         .aarch64_be,
@@ -2075,7 +2069,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
                     .s390x,
                     .sparc,
                     .sparc64,
-                    .sparcel,
                     .wasm32,
                     .wasm64,
                     => return 128,
@@ -2180,7 +2173,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
                     .mips64el,
                     .sparc,
                     .sparc64,
-                    .sparcel,
                     .wasm32,
                     .wasm64,
                     => return 128,
@@ -2374,7 +2366,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
             .mips,
             .mipsel,
             .sparc,
-            .sparcel,
             .sparc64,
             .lanai,
             .nvptx,
@@ -2487,7 +2478,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
             .mips,
             .mipsel,
             .sparc,
-            .sparcel,
             .sparc64,
             .lanai,
             .nvptx,
diff --git a/lib/std/atomic.zig b/lib/std/atomic.zig
index be7203c0cf..6de6d5437b 100644
--- a/lib/std/atomic.zig
+++ b/lib/std/atomic.zig
@@ -486,7 +486,6 @@ pub const cache_line = switch (builtin.cpu.arch) {
     .riscv32,
     .riscv64,
     .sparc,
-    .sparcel,
     .sparc64,
     => 32,
 
diff --git a/lib/std/builtin.zig b/lib/std/builtin.zig
index 86f8da6cd4..176b17dd07 100644
--- a/lib/std/builtin.zig
+++ b/lib/std/builtin.zig
@@ -615,7 +615,7 @@ pub const VaList = switch (builtin.cpu.arch) {
         else => VaListPowerPc,
     },
     .powerpc64, .powerpc64le => *u8,
-    .sparc, .sparcel, .sparc64 => *anyopaque,
+    .sparc, .sparc64 => *anyopaque,
     .spirv32, .spirv64 => *anyopaque,
     .s390x => VaListS390x,
     .wasm32, .wasm64 => *anyopaque,
diff --git a/lib/std/c.zig b/lib/std/c.zig
index ff2c7dbd85..f6398720bf 100644
--- a/lib/std/c.zig
+++ b/lib/std/c.zig
@@ -5779,7 +5779,7 @@ pub const ucontext_t = switch (native_os) {
                 .x86 => 4,
                 .mips, .mipsel, .mips64, .mips64el => 14,
                 .arm, .armeb, .thumb, .thumbeb => 1,
-                .sparc, .sparcel, .sparc64 => if (@sizeOf(usize) == 4) 43 else 8,
+                .sparc, .sparc64 => if (@sizeOf(usize) == 4) 43 else 8,
                 else => 0,
             }
         ]u32,
@@ -6821,7 +6821,7 @@ pub const pthread_key_t = switch (native_os) {
 pub const padded_pthread_spin_t = switch (native_os) {
     .netbsd => switch (builtin.cpu.arch) {
         .x86, .x86_64 => u32,
-        .sparc, .sparcel, .sparc64 => u32,
+        .sparc, .sparc64 => u32,
         else => pthread_spin_t,
     },
     else => void,
@@ -6834,7 +6834,7 @@ pub const pthread_spin_t = switch (native_os) {
         .powerpc, .powerpc64, .powerpc64le => i32,
         .x86, .x86_64 => u8,
         .arm, .armeb, .thumb, .thumbeb => i32,
-        .sparc, .sparcel, .sparc64 => u8,
+        .sparc, .sparc64 => u8,
         .riscv32, .riscv64 => u32,
         else => @compileError("undefined pthread_spin_t for this arch"),
     },
diff --git a/lib/std/os/linux.zig b/lib/std/os/linux.zig
index 4f3db110b2..7bc8439370 100644
--- a/lib/std/os/linux.zig
+++ b/lib/std/os/linux.zig
@@ -2485,7 +2485,7 @@ pub const E = switch (native_arch) {
 
         pub const init = errnoFromSyscall;
     },
-    .sparc, .sparcel, .sparc64 => enum(u16) {
+    .sparc, .sparc64 => enum(u16) {
         /// No error occurred.
         SUCCESS = 0,
 
@@ -4832,7 +4832,6 @@ pub const MINSIGSTKSZ = switch (native_arch) {
     => 2048,
     .loongarch64,
     .sparc,
-    .sparcel,
     .sparc64,
     => 4096,
     .aarch64,
@@ -4869,7 +4868,6 @@ pub const SIGSTKSZ = switch (native_arch) {
     .aarch64_be,
     .loongarch64,
     .sparc,
-    .sparcel,
     .sparc64,
     => 16384,
     .powerpc64,
diff --git a/lib/std/os/linux/ioctl.zig b/lib/std/os/linux/ioctl.zig
index 7f5d36b72d..8b7cc80af9 100644
--- a/lib/std/os/linux/ioctl.zig
+++ b/lib/std/os/linux/ioctl.zig
@@ -11,7 +11,6 @@ const bits = switch (@import("builtin").cpu.arch) {
     .powerpc64le,
     .sparc,
     .sparc64,
-    .sparcel,
     => .{ .size = 13, .dir = 3, .none = 1, .read = 2, .write = 4 },
     else => .{ .size = 14, .dir = 2, .none = 0, .read = 2, .write = 1 },
 };
diff --git a/src/Type.zig b/src/Type.zig
index 22e2931019..52844f7ca5 100644
--- a/src/Type.zig
+++ b/src/Type.zig
@@ -1602,7 +1602,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
         .amdgcn,
         .riscv32,
         .sparc,
-        .sparcel,
         .s390x,
         .lanai,
         .wasm32,
diff --git a/src/Zcu.zig b/src/Zcu.zig
index bc7d2d2e49..54faf34bf4 100644
--- a/src/Zcu.zig
+++ b/src/Zcu.zig
@@ -3248,7 +3248,6 @@ pub fn atomicPtrAlignment(
         .powerpcle,
         .riscv32,
         .sparc,
-        .sparcel,
         .thumb,
         .thumbeb,
         .x86,
diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig
index fcbfa06bd2..4317c1b41f 100644
--- a/src/codegen/llvm.zig
+++ b/src/codegen/llvm.zig
@@ -69,7 +69,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
         .riscv64 => "riscv64",
         .sparc => "sparc",
         .sparc64 => "sparc64",
-        .sparcel => "sparcel",
         .s390x => "s390x",
         .thumb => "thumb",
         .thumbeb => "thumbeb",
@@ -280,7 +279,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
         .riscv64 => .riscv64,
         .sparc => .sparc,
         .sparc64 => .sparcv9, // In LLVM, sparc64 == sparcv9.
-        .sparcel => .sparcel,
         .s390x => .systemz,
         .thumb => .thumb,
         .thumbeb => .thumbeb,
@@ -469,7 +467,6 @@ const DataLayoutBuilder = struct {
             .powerpcle,
             .riscv32,
             .sparc,
-            .sparcel,
             .thumb,
             .thumbeb,
             .xtensa,
@@ -12004,7 +12001,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
             llvm.LLVMInitializeRISCVAsmPrinter();
             llvm.LLVMInitializeRISCVAsmParser();
         },
-        .sparc, .sparc64, .sparcel => {
+        .sparc, .sparc64 => {
             llvm.LLVMInitializeSparcTarget();
             llvm.LLVMInitializeSparcTargetInfo();
             llvm.LLVMInitializeSparcTargetMC();
diff --git a/src/glibc.zig b/src/glibc.zig
index 6474a23dce..5214d0a977 100644
--- a/src/glibc.zig
+++ b/src/glibc.zig
@@ -394,7 +394,7 @@ fn start_asm_path(comp: *Compilation, arena: Allocator, basename: []const u8) ![
     const arch = comp.getTarget().cpu.arch;
     const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le;
     const is_aarch64 = arch == .aarch64 or arch == .aarch64_be;
-    const is_sparc = arch == .sparc or arch == .sparcel or arch == .sparc64;
+    const is_sparc = arch == .sparc or arch == .sparc64;
     const is_64 = comp.getTarget().ptrBitWidth() == 64;
 
     const s = path.sep_str;
@@ -532,7 +532,7 @@ fn add_include_dirs_arch(
     const is_x86 = arch == .x86 or arch == .x86_64;
     const is_aarch64 = arch == .aarch64 or arch == .aarch64_be;
     const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le;
-    const is_sparc = arch == .sparc or arch == .sparcel or arch == .sparc64;
+    const is_sparc = arch == .sparc or arch == .sparc64;
     const is_64 = target.ptrBitWidth() == 64;
 
     const s = path.sep_str;
diff --git a/src/link/Elf.zig b/src/link/Elf.zig
index 5e5c05c1cd..70c28dfa35 100644
--- a/src/link/Elf.zig
+++ b/src/link/Elf.zig
@@ -5175,7 +5175,7 @@ fn getLDMOption(target: std.Target) ?[]const u8 {
         .powerpc => return "elf32ppclinux",
         .powerpc64 => return "elf64ppc",
         .powerpc64le => return "elf64lppc",
-        .sparc, .sparcel => return "elf32_sparc",
+        .sparc => return "elf32_sparc",
         .sparc64 => return "elf64_sparc",
         .mips => return "elf32btsmip",
         .mipsel => return "elf32ltsmip",
diff --git a/src/link/Plan9/aout.zig b/src/link/Plan9/aout.zig
index 12dfc45873..3d35bb9acb 100644
--- a/src/link/Plan9/aout.zig
+++ b/src/link/Plan9/aout.zig
@@ -110,7 +110,7 @@ pub const R_MAGIC = _MAGIC(HDR_MAGIC, 28); // arm64
 pub fn magicFromArch(arch: std.Target.Cpu.Arch) !u32 {
     return switch (arch) {
         .x86 => I_MAGIC,
-        .sparc => K_MAGIC, // TODO should sparc64 and sparcel go here?
+        .sparc => K_MAGIC, // TODO should sparc64 go here?
         .mips => V_MAGIC,
         .arm => E_MAGIC,
         .aarch64 => R_MAGIC,
diff --git a/src/target.zig b/src/target.zig
index e30743f65c..62f3e52cb8 100644
--- a/src/target.zig
+++ b/src/target.zig
@@ -138,7 +138,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
         .riscv64,
         .sparc,
         .sparc64,
-        .sparcel,
         .s390x,
         .thumb,
         .thumbeb,
@@ -408,7 +407,7 @@ pub fn defaultFunctionAlignment(target: std.Target) Alignment {
     return switch (target.cpu.arch) {
         .arm, .armeb => .@"4",
         .aarch64, .aarch64_be => .@"4",
-        .sparc, .sparcel, .sparc64 => .@"4",
+        .sparc, .sparc64 => .@"4",
         .riscv64 => .@"2",
         else => .@"1",
     };
@@ -423,7 +422,6 @@ pub fn minFunctionAlignment(target: std.Target) Alignment {
         .riscv32,
         .riscv64,
         .sparc,
-        .sparcel,
         .sparc64,
         => .@"2",
         else => .@"1",
diff --git a/test/behavior/align.zig b/test/behavior/align.zig
index 564e08bac1..2c3fd66412 100644
--- a/test/behavior/align.zig
+++ b/test/behavior/align.zig
@@ -95,7 +95,6 @@ test "alignment and size of structs with 128-bit fields" {
         .amdgcn,
         .riscv32,
         .sparc,
-        .sparcel,
         .s390x,
         .lanai,
         .wasm32,
diff --git a/test/llvm_targets.zig b/test/llvm_targets.zig
index 853ca15879..71dc9e30a3 100644
--- a/test/llvm_targets.zig
+++ b/test/llvm_targets.zig
@@ -87,8 +87,6 @@ const targets = [_]std.Target.Query{
     .{ .cpu_arch = .sparc, .os_tag = .freestanding, .abi = .none },
     .{ .cpu_arch = .sparc, .os_tag = .linux, .abi = .gnu },
     .{ .cpu_arch = .sparc, .os_tag = .linux, .abi = .none },
-    .{ .cpu_arch = .sparcel, .os_tag = .freestanding, .abi = .none },
-    .{ .cpu_arch = .sparcel, .os_tag = .linux, .abi = .gnu },
     .{ .cpu_arch = .sparc64, .os_tag = .freestanding, .abi = .none },
     .{ .cpu_arch = .sparc64, .os_tag = .linux, .abi = .gnu },
     //.{ .cpu_arch = .spirv32, .os_tag = .opencl, .abi = .none },