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compiler: Update max int alignments for some targets.

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Alex Rønne Petersen 2025-03-05 07:59:58 +01:00
parent 4c5c5bcd91
commit cf9c6f5298
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2 changed files with 38 additions and 86 deletions
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59
src/Type.zig
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@ -1641,69 +1641,60 @@ pub fn intAbiAlignment(bits: u16, target: Target) Alignment {
pub fn maxIntAlignment(target: std.Target) u16 { pub fn maxIntAlignment(target: std.Target) u16 {
return switch (target.cpu.arch) { return switch (target.cpu.arch) {
.avr => 1, .avr => 1,
.msp430 => 2,
.xcore => 4,
.propeller => 4,
.msp430 => 2,
.xcore,
.propeller,
=> 4,
.amdgcn,
.arm, .arm,
.armeb, .armeb,
.thumb, .thumb,
.thumbeb, .thumbeb,
.lanai,
.hexagon, .hexagon,
.mips, .mips,
.mipsel, .mipsel,
.powerpc, .powerpc,
.powerpcle, .powerpcle,
.amdgcn,
.riscv32, .riscv32,
.sparc,
.s390x, .s390x,
.lanai,
.wasm32,
.wasm64,
=> 8, => 8,
// For these, LLVMABIAlignmentOfType(i128) reports 8. Note that 16
// is a relevant number in three cases:
// 1. Different machine code instruction when loading into SIMD register.
// 2. The C ABI wants 16 for extern structs.
// 3. 16-byte cmpxchg needs 16-byte alignment.
// Same logic for powerpc64, mips64, sparc64.
.powerpc64,
.powerpc64le,
.mips64,
.mips64el,
.sparc64,
=> switch (target.ofmt) {
.c => 16,
else => 8,
},
.x86_64 => 16,
// Even LLVMABIAlignmentOfType(i128) agrees on these targets. // Even LLVMABIAlignmentOfType(i128) agrees on these targets.
.x86,
.aarch64, .aarch64,
.aarch64_be, .aarch64_be,
.riscv64,
.bpfel, .bpfel,
.bpfeb, .bpfeb,
.mips64,
.mips64el,
.nvptx, .nvptx,
.nvptx64, .nvptx64,
.powerpc64,
.powerpc64le,
.riscv64,
.sparc,
.sparc64,
.wasm32,
.wasm64,
.x86,
.x86_64,
=> 16, => 16,
// Below this comment are unverified but based on the fact that C requires // Below this comment are unverified but based on the fact that C requires
// int128_t to be 16 bytes aligned, it's a safe default. // int128_t to be 16 bytes aligned, it's a safe default.
.csky,
.arc, .arc,
.m68k, .csky,
.kalimba, .kalimba,
.spirv,
.spirv32,
.ve,
.spirv64,
.loongarch32, .loongarch32,
.loongarch64, .loongarch64,
.m68k,
.spirv,
.spirv32,
.spirv64,
.ve,
.xtensa, .xtensa,
=> 16, => 16,
}; };

65
test/behavior/align.zig
View file

@ -85,22 +85,19 @@ test "alignment and size of structs with 128-bit fields" {
y: u8, y: u8,
}; };
const expected = switch (builtin.cpu.arch) { const expected = switch (builtin.cpu.arch) {
.amdgcn,
.arm, .arm,
.armeb, .armeb,
.thumb, .thumb,
.thumbeb, .thumbeb,
.hexagon, .hexagon,
.lanai,
.mips, .mips,
.mipsel, .mipsel,
.powerpc, .powerpc,
.powerpcle, .powerpcle,
.amdgcn,
.riscv32, .riscv32,
.sparc,
.s390x, .s390x,
.lanai,
.wasm32,
.wasm64,
=> .{ => .{
.a_align = 8, .a_align = 8,
.a_size = 16, .a_size = 16,
@ -114,59 +111,23 @@ test "alignment and size of structs with 128-bit fields" {
.u129_size = 24, .u129_size = 24,
}, },
.mips64,
.mips64el,
.powerpc64,
.powerpc64le,
.sparc64,
=> switch (builtin.object_format) {
.c => .{
.a_align = 16,
.a_size = 16,
.b_align = 16,
.b_size = 32,
.u128_align = 16,
.u128_size = 16,
.u129_align = 16,
.u129_size = 32,
},
else => .{
.a_align = 8,
.a_size = 16,
.b_align = 16,
.b_size = 32,
.u128_align = 8,
.u128_size = 16,
.u129_align = 8,
.u129_size = 24,
},
},
.x86_64 => .{
.a_align = 16,
.a_size = 16,
.b_align = 16,
.b_size = 32,
.u128_align = 16,
.u128_size = 16,
.u129_align = 16,
.u129_size = 32,
},
.x86,
.aarch64, .aarch64,
.aarch64_be, .aarch64_be,
.riscv64,
.bpfel, .bpfel,
.bpfeb, .bpfeb,
.mips64,
.mips64el,
.nvptx, .nvptx,
.nvptx64, .nvptx64,
.powerpc64,
.powerpc64le,
.sparc,
.sparc64,
.riscv64,
.wasm32,
.wasm64,
.x86,
.x86_64,
=> .{ => .{
.a_align = 16, .a_align = 16,
.a_size = 16, .a_size = 16,