From fb0692334ed64a995690c21525fc3e729e63f424 Mon Sep 17 00:00:00 2001 From: Koakuma Date: Fri, 13 May 2022 22:59:06 +0700 Subject: [PATCH] target: Rename sparcv9 -> sparc64 Rename all references of sparcv9 to sparc64, to make Zig align more with other projects. Also, added new function to convert glibc arch name to Zig arch name, since it refers to the architecture as sparcv9. This is based on the suggestion by @kubkon in PR 11847. (https://github.com/ziglang/zig/pull/11487#pullrequestreview-963761757) --- CMakeLists.txt | 10 ++-- doc/langref.html.in | 4 +- lib/c.zig | 2 +- lib/compiler_rt/clear_cache.zig | 2 +- lib/std/Thread.zig | 2 +- lib/std/builtin.zig | 6 +- lib/std/c/linux.zig | 4 +- lib/std/c/minix.zig | 2 +- lib/std/c/netbsd.zig | 6 +- lib/std/c/openbsd.zig | 2 +- lib/std/debug.zig | 2 +- lib/std/elf.zig | 2 +- lib/std/mem.zig | 2 +- lib/std/os/linux.zig | 12 ++-- lib/std/os/linux/ioctl.zig | 2 +- lib/std/os/linux/tls.zig | 4 +- lib/std/start.zig | 6 +- lib/std/target.zig | 30 +++++----- lib/std/zig/system/NativeTargetInfo.zig | 2 +- lib/std/zig/system/linux.zig | 4 +- src/Compilation.zig | 2 +- src/arch/{sparcv9 => sparc64}/CodeGen.zig | 8 +-- src/arch/{sparcv9 => sparc64}/Emit.zig | 6 +- src/arch/{sparcv9 => sparc64}/Mir.zig | 0 src/arch/{sparcv9 => sparc64}/abi.zig | 0 src/arch/{sparcv9 => sparc64}/bits.zig | 0 src/codegen.zig | 2 +- src/codegen/llvm.zig | 4 +- src/glibc.zig | 55 +++++++++++++++++-- src/link/Elf.zig | 4 +- src/link/Plan9/aout.zig | 2 +- src/stage1/codegen.cpp | 9 ++- src/target.zig | 12 ++-- src/type.zig | 4 +- test/behavior/align.zig | 2 +- test/behavior/vector.zig | 2 +- .../hello_world.zig | 2 +- tools/process_headers.zig | 4 +- 38 files changed, 139 insertions(+), 85 deletions(-) rename src/arch/{sparcv9 => sparc64}/CodeGen.zig (99%) rename src/arch/{sparcv9 => sparc64}/Emit.zig (98%) rename src/arch/{sparcv9 => sparc64}/Mir.zig (100%) rename src/arch/{sparcv9 => sparc64}/abi.zig (100%) rename src/arch/{sparcv9 => sparc64}/bits.zig (100%) rename test/cases/{sparcv9-linux => sparc64-linux}/hello_world.zig (94%) diff --git a/CMakeLists.txt b/CMakeLists.txt index dd57918073..cc962fcff1 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -612,11 +612,11 @@ set(ZIG_STAGE2_SOURCES "${CMAKE_SOURCE_DIR}/src/arch/riscv64/Mir.zig" "${CMAKE_SOURCE_DIR}/src/arch/riscv64/bits.zig" "${CMAKE_SOURCE_DIR}/src/arch/riscv64/abi.zig" - "${CMAKE_SOURCE_DIR}/src/arch/sparcv9/CodeGen.zig" - "${CMAKE_SOURCE_DIR}/src/arch/sparcv9/Emit.zig" - "${CMAKE_SOURCE_DIR}/src/arch/sparcv9/Mir.zig" - "${CMAKE_SOURCE_DIR}/src/arch/sparcv9/bits.zig" - "${CMAKE_SOURCE_DIR}/src/arch/sparcv9/abi.zig" + "${CMAKE_SOURCE_DIR}/src/arch/sparc64/CodeGen.zig" + "${CMAKE_SOURCE_DIR}/src/arch/sparc64/Emit.zig" + "${CMAKE_SOURCE_DIR}/src/arch/sparc64/Mir.zig" + "${CMAKE_SOURCE_DIR}/src/arch/sparc64/bits.zig" + "${CMAKE_SOURCE_DIR}/src/arch/sparc64/abi.zig" "${CMAKE_SOURCE_DIR}/src/arch/wasm/CodeGen.zig" "${CMAKE_SOURCE_DIR}/src/arch/wasm/Emit.zig" "${CMAKE_SOURCE_DIR}/src/arch/wasm/Mir.zig" diff --git a/doc/langref.html.in b/doc/langref.html.in index f5d3c0b7c1..32320d5113 100644 --- a/doc/langref.html.in +++ b/doc/langref.html.in @@ -11392,7 +11392,7 @@ Architectures: riscv32 riscv64 sparc - sparcv9 + sparc64 sparcel s390x thumb @@ -11543,7 +11543,7 @@ Available libcs: s390x-linux-gnu s390x-linux-musl sparc-linux-gnu - sparcv9-linux-gnu + sparc64-linux-gnu wasm32-freestanding-musl wasm32-wasi-musl x86_64-linux-gnu diff --git a/lib/c.zig b/lib/c.zig index 525bdd267d..30c6e0cd76 100644 --- a/lib/c.zig +++ b/lib/c.zig @@ -625,7 +625,7 @@ fn clone() callconv(.Naked) void { \\ sc ); }, - .sparcv9 => { + .sparc64 => { // __clone(func, stack, flags, arg, ptid, tls, ctid) // i0, i1, i2, i3, i4, i5, sp // syscall(SYS_clone, flags, stack, ptid, tls, ctid) diff --git a/lib/compiler_rt/clear_cache.zig b/lib/compiler_rt/clear_cache.zig index d6ce02249e..0765a23811 100644 --- a/lib/compiler_rt/clear_cache.zig +++ b/lib/compiler_rt/clear_cache.zig @@ -36,7 +36,7 @@ pub fn clear_cache(start: usize, end: usize) callconv(.C) void { else => false, }; const sparc = switch (arch) { - .sparc, .sparcv9, .sparcel => true, + .sparc, .sparc64, .sparcel => true, else => false, }; const apple = switch (os) { diff --git a/lib/std/Thread.zig b/lib/std/Thread.zig index 45d2ac0040..9e29c82672 100644 --- a/lib/std/Thread.zig +++ b/lib/std/Thread.zig @@ -859,7 +859,7 @@ const LinuxThreadImpl = struct { [len] "r" (self.mapped.len), : "memory" ), - .sparcv9 => asm volatile ( + .sparc64 => asm volatile ( \\ # SPARCs really don't like it when active stack frames \\ # is unmapped (it will result in a segfault), so we \\ # force-deactivate it by running `restore` until diff --git a/lib/std/builtin.zig b/lib/std/builtin.zig index bf9a2d5682..53786c8661 100644 --- a/lib/std/builtin.zig +++ b/lib/std/builtin.zig @@ -727,8 +727,8 @@ pub const CompilerBackend = enum(u64) { /// riscv64 backend. stage2_riscv64 = 9, /// The reference implementation self-hosted compiler of Zig, using the - /// sparcv9 backend. - stage2_sparcv9 = 10, + /// sparc64 backend. + stage2_sparc64 = 10, _, }; @@ -775,7 +775,7 @@ pub fn default_panic(msg: []const u8, error_return_trace: ?*StackTrace) noreturn builtin.zig_backend == .stage2_x86_64 or builtin.zig_backend == .stage2_x86 or builtin.zig_backend == .stage2_riscv64 or - builtin.zig_backend == .stage2_sparcv9) + builtin.zig_backend == .stage2_sparc64) { while (true) { @breakpoint(); diff --git a/lib/std/c/linux.zig b/lib/std/c/linux.zig index 5f96fe3fe0..62a7d3e964 100644 --- a/lib/std/c/linux.zig +++ b/lib/std/c/linux.zig @@ -115,7 +115,7 @@ pub const _errno = switch (native_abi) { }; pub const Stat = switch (native_arch) { - .sparcv9 => extern struct { + .sparc64 => extern struct { dev: u64, __pad1: u16, ino: ino_t, @@ -345,7 +345,7 @@ const __SIZEOF_PTHREAD_MUTEX_T = switch (native_abi) { .gnu, .gnuabin32, .gnuabi64, .gnueabi, .gnueabihf, .gnux32 => switch (native_arch) { .aarch64 => 48, .x86_64 => if (native_abi == .gnux32) 40 else 32, - .mips64, .powerpc64, .powerpc64le, .sparcv9 => 40, + .mips64, .powerpc64, .powerpc64le, .sparc64 => 40, else => if (@sizeOf(usize) == 8) 40 else 24, }, .android => if (@sizeOf(usize) == 8) 40 else 4, diff --git a/lib/std/c/minix.zig b/lib/std/c/minix.zig index 9c644a7986..62cefc14fb 100644 --- a/lib/std/c/minix.zig +++ b/lib/std/c/minix.zig @@ -11,7 +11,7 @@ const __SIZEOF_PTHREAD_MUTEX_T = switch (builtin.abi) { .gnu, .gnuabin32, .gnuabi64, .gnueabi, .gnueabihf, .gnux32 => switch (builtin.cpu.arch) { .aarch64 => 48, .x86_64 => if (builtin.abi == .gnux32) 40 else 32, - .mips64, .powerpc64, .powerpc64le, .sparcv9 => 40, + .mips64, .powerpc64, .powerpc64le, .sparc64 => 40, else => if (@sizeOf(usize) == 8) 40 else 24, }, else => unreachable, diff --git a/lib/std/c/netbsd.zig b/lib/std/c/netbsd.zig index b1f8e8846e..e481de0996 100644 --- a/lib/std/c/netbsd.zig +++ b/lib/std/c/netbsd.zig @@ -99,14 +99,14 @@ const pthread_spin_t = switch (builtin.cpu.arch) { .powerpc, .powerpc64, .powerpc64le => i32, .i386, .x86_64 => u8, .arm, .armeb, .thumb, .thumbeb => i32, - .sparc, .sparcel, .sparcv9 => u8, + .sparc, .sparcel, .sparc64 => u8, .riscv32, .riscv64 => u32, else => @compileError("undefined pthread_spin_t for this arch"), }; const padded_pthread_spin_t = switch (builtin.cpu.arch) { .i386, .x86_64 => u32, - .sparc, .sparcel, .sparcv9 => u32, + .sparc, .sparcel, .sparc64 => u32, else => pthread_spin_t, }; @@ -1070,7 +1070,7 @@ pub const ucontext_t = extern struct { .i386 => 4, .mips, .mipsel, .mips64, .mips64el => 14, .arm, .armeb, .thumb, .thumbeb => 1, - .sparc, .sparcel, .sparcv9 => if (@sizeOf(usize) == 4) 43 else 8, + .sparc, .sparcel, .sparc64 => if (@sizeOf(usize) == 4) 43 else 8, else => 0, } ]u32, diff --git a/lib/std/c/openbsd.zig b/lib/std/c/openbsd.zig index 0aa90c741a..71c9d21ce3 100644 --- a/lib/std/c/openbsd.zig +++ b/lib/std/c/openbsd.zig @@ -1263,7 +1263,7 @@ pub const E = enum(u16) { const _MAX_PAGE_SHIFT = switch (builtin.cpu.arch) { .i386 => 12, - .sparcv9 => 13, + .sparc64 => 13, }; pub const MINSIGSTKSZ = 1 << _MAX_PAGE_SHIFT; pub const SIGSTKSZ = MINSIGSTKSZ + (1 << _MAX_PAGE_SHIFT) * 4; diff --git a/lib/std/debug.zig b/lib/std/debug.zig index 1a34d67f9d..83667c758b 100644 --- a/lib/std/debug.zig +++ b/lib/std/debug.zig @@ -401,7 +401,7 @@ pub const StackIterator = struct { fp: usize, pub fn init(first_address: ?usize, fp: ?usize) StackIterator { - if (native_arch == .sparcv9) { + if (native_arch == .sparc64) { // Flush all the register windows on stack. asm volatile ( \\ flushw diff --git a/lib/std/elf.zig b/lib/std/elf.zig index 2ea928f891..d80ae2f6a0 100644 --- a/lib/std/elf.zig +++ b/lib/std/elf.zig @@ -1511,7 +1511,7 @@ pub const EM = enum(u16) { .RISCV => .riscv64, .X86_64 => .x86_64, .BPF => .bpfel, - .SPARCV9 => .sparcv9, + .SPARCV9 => .sparc64, .S390 => .s390x, .SPU_2 => .spu_2, // there's many cases we don't (yet) handle, or will never have a diff --git a/lib/std/mem.zig b/lib/std/mem.zig index eec9d4d61f..73cc24c45c 100644 --- a/lib/std/mem.zig +++ b/lib/std/mem.zig @@ -18,7 +18,7 @@ pub const page_size = switch (builtin.cpu.arch) { .macos, .ios, .watchos, .tvos => 16 * 1024, else => 4 * 1024, }, - .sparcv9 => 8 * 1024, + .sparc64 => 8 * 1024, else => 4 * 1024, }; diff --git a/lib/std/os/linux.zig b/lib/std/os/linux.zig index 94e2dd47b9..fec9f55ad1 100644 --- a/lib/std/os/linux.zig +++ b/lib/std/os/linux.zig @@ -38,7 +38,7 @@ const arch_bits = switch (native_arch) { .aarch64 => @import("linux/arm64.zig"), .arm, .thumb => @import("linux/arm-eabi.zig"), .riscv64 => @import("linux/riscv64.zig"), - .sparcv9 => @import("linux/sparc64.zig"), + .sparc64 => @import("linux/sparc64.zig"), .mips, .mipsel => @import("linux/mips.zig"), .powerpc => @import("linux/powerpc.zig"), .powerpc64, .powerpc64le => @import("linux/powerpc64.zig"), @@ -1098,7 +1098,7 @@ pub fn sigaction(sig: u6, noalias act: ?*const Sigaction, noalias oact: ?*Sigact const result = switch (native_arch) { // The sparc version of rt_sigaction needs the restorer function to be passed as an argument too. - .sparc, .sparcv9 => syscall5(.rt_sigaction, sig, ksa_arg, oldksa_arg, @ptrToInt(ksa.restorer), mask_size), + .sparc, .sparc64 => syscall5(.rt_sigaction, sig, ksa_arg, oldksa_arg, @ptrToInt(ksa.restorer), mask_size), else => syscall4(.rt_sigaction, sig, ksa_arg, oldksa_arg, mask_size), }; if (getErrno(result) != .SUCCESS) return result; @@ -1698,7 +1698,7 @@ pub fn seccomp(operation: u32, flags: u32, args: ?*const anyopaque) usize { pub const E = switch (native_arch) { .mips, .mipsel => @import("linux/errno/mips.zig").E, - .sparc, .sparcel, .sparcv9 => @import("linux/errno/sparc.zig").E, + .sparc, .sparcel, .sparc64 => @import("linux/errno/sparc.zig").E, else => @import("linux/errno/generic.zig").E, }; @@ -4090,7 +4090,7 @@ pub const V = switch (native_arch) { pub const LNEXT = 15; pub const DISCARD = 16; }, - .sparc, .sparcv9 => struct { + .sparc, .sparc64 => struct { pub const INTR = 0; pub const QUIT = 1; pub const ERASE = 2; @@ -5427,7 +5427,7 @@ pub const AUDIT = struct { .aarch64 => .AARCH64, .arm, .thumb => .ARM, .riscv64 => .RISCV64, - .sparcv9 => .SPARC64, + .sparc64 => .SPARC64, .mips => .MIPS, .mipsel => .MIPSEL, .powerpc => .PPC, @@ -5454,7 +5454,7 @@ pub const AUDIT = struct { RISCV64 = toAudit(.riscv64), S390X = toAudit(.s390x), SPARC = toAudit(.sparc), - SPARC64 = toAudit(.sparcv9), + SPARC64 = toAudit(.sparc64), X86_64 = toAudit(.x86_64), fn toAudit(arch: std.Target.Cpu.Arch) u32 { diff --git a/lib/std/os/linux/ioctl.zig b/lib/std/os/linux/ioctl.zig index 35ff1bfc32..96ec96c306 100644 --- a/lib/std/os/linux/ioctl.zig +++ b/lib/std/os/linux/ioctl.zig @@ -10,7 +10,7 @@ const bits = switch (@import("builtin").cpu.arch) { .powerpc64, .powerpc64le, .sparc, - .sparcv9, + .sparc64, .sparcel, => .{ .size = 13, .dir = 3, .none = 1, .read = 2, .write = 4 }, else => .{ .size = 14, .dir = 2, .none = 0, .read = 2, .write = 1 }, diff --git a/lib/std/os/linux/tls.zig b/lib/std/os/linux/tls.zig index 770ab9b92c..d91f7d7a9e 100644 --- a/lib/std/os/linux/tls.zig +++ b/lib/std/os/linux/tls.zig @@ -49,7 +49,7 @@ const TLSVariant = enum { const tls_variant = switch (native_arch) { .arm, .armeb, .thumb, .aarch64, .aarch64_be, .riscv32, .riscv64, .mips, .mipsel, .powerpc, .powerpc64, .powerpc64le => TLSVariant.VariantI, - .x86_64, .i386, .sparcv9 => TLSVariant.VariantII, + .x86_64, .i386, .sparc64 => TLSVariant.VariantII, else => @compileError("undefined tls_variant for this architecture"), }; @@ -174,7 +174,7 @@ pub fn setThreadPointer(addr: usize) void { : [addr] "r" (addr), ); }, - .sparcv9 => { + .sparc64 => { asm volatile ( \\ mov %[addr], %%g7 : diff --git a/lib/std/start.zig b/lib/std/start.zig index 81c7942bc1..516d6363d7 100644 --- a/lib/std/start.zig +++ b/lib/std/start.zig @@ -29,7 +29,7 @@ comptime { builtin.zig_backend == .stage2_aarch64 or builtin.zig_backend == .stage2_arm or builtin.zig_backend == .stage2_riscv64 or - builtin.zig_backend == .stage2_sparcv9) + builtin.zig_backend == .stage2_sparc64) { if (builtin.output_mode == .Exe) { if ((builtin.link_libc or builtin.object_format == .c) and @hasDecl(root, "main")) { @@ -164,7 +164,7 @@ fn exit2(code: usize) noreturn { : "rcx", "r11", "memory" ); }, - .sparcv9 => { + .sparc64 => { asm volatile ("ta 0x6d" : : [number] "{g1}" (1), @@ -323,7 +323,7 @@ fn _start() callconv(.Naked) noreturn { : "r0" ); }, - .sparcv9 => { + .sparc64 => { // argc is stored after a register window (16 registers) plus stack bias argc_argv_ptr = asm ( \\ mov %%g0, %%i6 diff --git a/lib/std/target.zig b/lib/std/target.zig index 2db1415cd3..b11408cfce 100644 --- a/lib/std/target.zig +++ b/lib/std/target.zig @@ -785,7 +785,7 @@ pub const Target = struct { riscv32, riscv64, sparc, - sparcv9, + sparc64, sparcel, s390x, tce, @@ -884,7 +884,7 @@ pub const Target = struct { pub fn isSPARC(arch: Arch) bool { return switch (arch) { - .sparc, .sparcel, .sparcv9 => true, + .sparc, .sparcel, .sparc64 => true, else => false, }; } @@ -964,7 +964,7 @@ pub const Target = struct { .bpfel => .BPF, .bpfeb => .BPF, .csky => .CSKY, - .sparcv9 => .SPARCV9, + .sparc64 => .SPARCV9, .s390x => .S390, .ve => .NONE, .spu_2 => .SPU_2, @@ -1025,7 +1025,7 @@ pub const Target = struct { .bpfel => .Unknown, .bpfeb => .Unknown, .csky => .Unknown, - .sparcv9 => .Unknown, + .sparc64 => .Unknown, .s390x => .Unknown, .ve => .Unknown, .spu_2 => .Unknown, @@ -1092,7 +1092,7 @@ pub const Target = struct { .powerpc64, .thumbeb, .sparc, - .sparcv9, + .sparc64, .tce, .lanai, .s390x, @@ -1159,7 +1159,7 @@ pub const Target = struct { .amdgcn, .bpfel, .bpfeb, - .sparcv9, + .sparc64, .s390x, .ve, .spirv64, @@ -1177,7 +1177,7 @@ pub const Target = struct { .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc", .amdgcn => "amdgpu", .riscv32, .riscv64 => "riscv", - .sparc, .sparcv9, .sparcel => "sparc", + .sparc, .sparc64, .sparcel => "sparc", .s390x => "systemz", .i386, .x86_64 => "x86", .nvptx, .nvptx64 => "nvptx", @@ -1200,7 +1200,7 @@ pub const Target = struct { .powerpc, .powerpcle, .powerpc64, .powerpc64le => &powerpc.all_features, .amdgcn => &amdgpu.all_features, .riscv32, .riscv64 => &riscv.all_features, - .sparc, .sparcv9, .sparcel => &sparc.all_features, + .sparc, .sparc64, .sparcel => &sparc.all_features, .spirv32, .spirv64 => &spirv.all_features, .s390x => &systemz.all_features, .i386, .x86_64 => &x86.all_features, @@ -1225,7 +1225,7 @@ pub const Target = struct { .powerpc, .powerpcle, .powerpc64, .powerpc64le => comptime allCpusFromDecls(powerpc.cpu), .amdgcn => comptime allCpusFromDecls(amdgpu.cpu), .riscv32, .riscv64 => comptime allCpusFromDecls(riscv.cpu), - .sparc, .sparcv9, .sparcel => comptime allCpusFromDecls(sparc.cpu), + .sparc, .sparc64, .sparcel => comptime allCpusFromDecls(sparc.cpu), .s390x => comptime allCpusFromDecls(systemz.cpu), .i386, .x86_64 => comptime allCpusFromDecls(x86.cpu), .nvptx, .nvptx64 => comptime allCpusFromDecls(nvptx.cpu), @@ -1286,7 +1286,7 @@ pub const Target = struct { .riscv32 => &riscv.cpu.generic_rv32, .riscv64 => &riscv.cpu.generic_rv64, .sparc, .sparcel => &sparc.cpu.generic, - .sparcv9 => &sparc.cpu.v9, + .sparc64 => &sparc.cpu.v9, // 64-bit SPARC needs v9 as the baseline .s390x => &systemz.cpu.generic, .i386 => &x86.cpu._i386, .x86_64 => &x86.cpu.x86_64, @@ -1587,7 +1587,7 @@ pub const Target = struct { .powerpc, .powerpcle => return copy(&result, "/lib/ld.so.1"), .powerpc64, .powerpc64le => return copy(&result, "/lib64/ld64.so.2"), .s390x => return copy(&result, "/lib64/ld64.so.1"), - .sparcv9 => return copy(&result, "/lib64/ld-linux.so.2"), + .sparc64 => return copy(&result, "/lib64/ld-linux.so.2"), .x86_64 => return copy(&result, switch (self.abi) { .gnux32 => "/libx32/ld-linux-x32.so.2", else => "/lib64/ld-linux-x86-64.so.2", @@ -1735,7 +1735,7 @@ pub const Target = struct { .mips64, .mips64el, .sparc, - .sparcv9, + .sparc64, .sparcel, .powerpc, .powerpcle, @@ -1760,7 +1760,7 @@ pub const Target = struct { .mips64, .mips64el, .sparc, - .sparcv9, + .sparc64, .sparcel, .powerpc, .powerpcle, @@ -1810,14 +1810,14 @@ pub const Target = struct { // 1. Better machine code when loading into SIMD register. // 2. The C ABI wants 16 for extern structs. // 3. 16-byte cmpxchg needs 16-byte alignment. - // Same logic for riscv64, powerpc64, mips64, sparcv9. + // Same logic for riscv64, powerpc64, mips64, sparc64. .x86_64, .riscv64, .powerpc64, .powerpc64le, .mips64, .mips64el, - .sparcv9, + .sparc64, // Even LLVMABIAlignmentOfType(i128) agrees on these targets. .aarch64, diff --git a/lib/std/zig/system/NativeTargetInfo.zig b/lib/std/zig/system/NativeTargetInfo.zig index 9055d1c215..0956e469af 100644 --- a/lib/std/zig/system/NativeTargetInfo.zig +++ b/lib/std/zig/system/NativeTargetInfo.zig @@ -931,7 +931,7 @@ pub fn getExternalExecutor( .riscv64 => Executor{ .qemu = "qemu-riscv64" }, .s390x => Executor{ .qemu = "qemu-s390x" }, .sparc => Executor{ .qemu = "qemu-sparc" }, - .sparcv9 => Executor{ .qemu = "qemu-sparc64" }, + .sparc64 => Executor{ .qemu = "qemu-sparc64" }, .x86_64 => Executor{ .qemu = "qemu-x86_64" }, else => return bad_result, }; diff --git a/lib/std/zig/system/linux.zig b/lib/std/zig/system/linux.zig index 0594ff1e2f..ee1e987464 100644 --- a/lib/std/zig/system/linux.zig +++ b/lib/std/zig/system/linux.zig @@ -66,7 +66,7 @@ const SparcCpuinfoImpl = struct { const SparcCpuinfoParser = CpuinfoParser(SparcCpuinfoImpl); test "cpuinfo: SPARC" { - try testParser(SparcCpuinfoParser, .sparcv9, &Target.sparc.cpu.niagara2, + try testParser(SparcCpuinfoParser, .sparc64, &Target.sparc.cpu.niagara2, \\cpu : UltraSparc T2 (Niagara2) \\fpu : UltraSparc T2 integrated FPU \\pmu : niagara2 @@ -456,7 +456,7 @@ pub fn detectNativeCpuAndFeatures() ?Target.Cpu { .arm, .armeb, .thumb, .thumbeb, .aarch64, .aarch64_be, .aarch64_32 => { return ArmCpuinfoParser.parse(current_arch, f.reader()) catch null; }, - .sparcv9 => { + .sparc64 => { return SparcCpuinfoParser.parse(current_arch, f.reader()) catch null; }, .powerpc, .powerpcle, .powerpc64, .powerpc64le => { diff --git a/src/Compilation.zig b/src/Compilation.zig index 5e4ab0ec12..2091502da2 100644 --- a/src/Compilation.zig +++ b/src/Compilation.zig @@ -4566,7 +4566,7 @@ pub fn generateBuiltinZigSource(comp: *Compilation, allocator: Allocator) Alloca .i386 => .stage2_x86, .aarch64, .aarch64_be, .aarch64_32 => .stage2_aarch64, .riscv64 => .stage2_riscv64, - .sparcv9 => .stage2_sparcv9, + .sparc64 => .stage2_sparc64, else => .other, }; }; diff --git a/src/arch/sparcv9/CodeGen.zig b/src/arch/sparc64/CodeGen.zig similarity index 99% rename from src/arch/sparcv9/CodeGen.zig rename to src/arch/sparc64/CodeGen.zig index 35d9a78dcd..0745cd46c9 100644 --- a/src/arch/sparcv9/CodeGen.zig +++ b/src/arch/sparc64/CodeGen.zig @@ -338,7 +338,7 @@ pub fn generate( fn gen(self: *Self) !void { const cc = self.fn_type.fnCallingConvention(); if (cc != .Naked) { - // TODO Finish function prologue and epilogue for sparcv9. + // TODO Finish function prologue and epilogue for sparc64. // save %sp, stack_save_area, %sp const save_inst = try self.addInst(.{ @@ -378,7 +378,7 @@ fn gen(self: *Self) !void { for (self.exitlude_jump_relocs.items) |jmp_reloc| { _ = jmp_reloc; - return self.fail("TODO add branches in sparcv9", .{}); + return self.fail("TODO add branches in sparc64", .{}); } // Backpatch stack offset @@ -1668,11 +1668,11 @@ fn resolveCallingConventionValues(self: *Self, fn_ty: Type, role: RegisterView) .callee => .{ .register = abi.c_abi_int_return_regs_callee_view[0] }, }; } else { - return self.fail("TODO support more return values for sparcv9", .{}); + return self.fail("TODO support more return values for sparc64", .{}); } } }, - else => return self.fail("TODO implement function parameters for {} on sparcv9", .{cc}), + else => return self.fail("TODO implement function parameters for {} on sparc64", .{cc}), } return result; diff --git a/src/arch/sparcv9/Emit.zig b/src/arch/sparc64/Emit.zig similarity index 98% rename from src/arch/sparcv9/Emit.zig rename to src/arch/sparc64/Emit.zig index 4da2215c46..81ae062c61 100644 --- a/src/arch/sparcv9/Emit.zig +++ b/src/arch/sparc64/Emit.zig @@ -51,9 +51,9 @@ pub fn emitMir( .add => try emit.mirArithmetic3Op(inst), - .bpcc => @panic("TODO implement sparcv9 bpcc"), + .bpcc => @panic("TODO implement sparc64 bpcc"), - .call => @panic("TODO implement sparcv9 call"), + .call => @panic("TODO implement sparc64 call"), .jmpl => try emit.mirArithmetic3Op(inst), @@ -73,7 +73,7 @@ pub fn emitMir( .sethi => try emit.mirSethi(inst), - .sllx => @panic("TODO implement sparcv9 sllx"), + .sllx => @panic("TODO implement sparc64 sllx"), .stb => try emit.mirArithmetic3Op(inst), .sth => try emit.mirArithmetic3Op(inst), diff --git a/src/arch/sparcv9/Mir.zig b/src/arch/sparc64/Mir.zig similarity index 100% rename from src/arch/sparcv9/Mir.zig rename to src/arch/sparc64/Mir.zig diff --git a/src/arch/sparcv9/abi.zig b/src/arch/sparc64/abi.zig similarity index 100% rename from src/arch/sparcv9/abi.zig rename to src/arch/sparc64/abi.zig diff --git a/src/arch/sparcv9/bits.zig b/src/arch/sparc64/bits.zig similarity index 100% rename from src/arch/sparcv9/bits.zig rename to src/arch/sparc64/bits.zig diff --git a/src/codegen.zig b/src/codegen.zig index debd7b5e9d..def69d952f 100644 --- a/src/codegen.zig +++ b/src/codegen.zig @@ -103,7 +103,7 @@ pub fn generateFunction( //.riscv32 => return Function(.riscv32).generate(bin_file, src_loc, func, air, liveness, code, debug_output), .riscv64 => return @import("arch/riscv64/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output), //.sparc => return Function(.sparc).generate(bin_file, src_loc, func, air, liveness, code, debug_output), - .sparcv9 => return @import("arch/sparcv9/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output), + .sparc64 => return @import("arch/sparc64/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output), //.sparcel => return Function(.sparcel).generate(bin_file, src_loc, func, air, liveness, code, debug_output), //.s390x => return Function(.s390x).generate(bin_file, src_loc, func, air, liveness, code, debug_output), //.tce => return Function(.tce).generate(bin_file, src_loc, func, air, liveness, code, debug_output), diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index 5e70710046..5a8516b363 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -53,7 +53,7 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![:0]u8 { .riscv32 => "riscv32", .riscv64 => "riscv64", .sparc => "sparc", - .sparcv9 => "sparcv9", + .sparc64 => "sparc64", .sparcel => "sparcel", .s390x => "s390x", .tce => "tce", @@ -7797,7 +7797,7 @@ fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void { llvm.LLVMInitializeRISCVAsmPrinter(); llvm.LLVMInitializeRISCVAsmParser(); }, - .sparc, .sparcv9, .sparcel => { + .sparc, .sparc64, .sparcel => { llvm.LLVMInitializeSparcTarget(); llvm.LLVMInitializeSparcTargetInfo(); llvm.LLVMInitializeSparcTargetMC(); diff --git a/src/glibc.zig b/src/glibc.zig index dee4e50e37..4deac5275f 100644 --- a/src/glibc.zig +++ b/src/glibc.zig @@ -43,6 +43,29 @@ pub const libs = [_]Lib{ .{ .name = "util", .sover = 1 }, }; +// glibc's naming of Zig architectures +const Arch = enum(c_int) { + arm, + armeb, + aarch64, + aarch64_be, + mips, + mipsel, + mips64, + mips64el, + powerpc, + powerpc64, + powerpc64le, + riscv32, + riscv64, + sparc, + sparcv9, + sparcel, + s390x, + i386, + x86_64, +}; + pub const LoadMetaDataError = error{ /// The files that ship with the Zig compiler were unable to be read, or otherwise had malformed data. ZigInstallationCorrupt, @@ -134,7 +157,7 @@ pub fn loadMetaData(gpa: Allocator, zig_lib_dir: fs.Dir) LoadMetaDataError!*ABI log.err("abilists: expected ABI name", .{}); return error.ZigInstallationCorrupt; }; - const arch_tag = std.meta.stringToEnum(std.Target.Cpu.Arch, arch_name) orelse { + const arch_tag = std.meta.stringToEnum(Arch, arch_name) orelse { log.err("abilists: unrecognized arch: '{s}'", .{arch_name}); return error.ZigInstallationCorrupt; }; @@ -148,7 +171,7 @@ pub fn loadMetaData(gpa: Allocator, zig_lib_dir: fs.Dir) LoadMetaDataError!*ABI }; targets[i] = .{ - .arch = arch_tag, + .arch = glibcToZigArch(arch_tag), .os = .linux, .abi = abi_tag, }; @@ -381,7 +404,7 @@ fn start_asm_path(comp: *Compilation, arena: Allocator, basename: []const u8) ![ const arch = comp.getTarget().cpu.arch; const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le; const is_aarch64 = arch == .aarch64 or arch == .aarch64_be; - const is_sparc = arch == .sparc or arch == .sparcel or arch == .sparcv9; + const is_sparc = arch == .sparc or arch == .sparcel or arch == .sparc64; const is_64 = arch.ptrBitWidth() == 64; const s = path.sep_str; @@ -519,7 +542,7 @@ fn add_include_dirs_arch( const is_x86 = arch == .i386 or arch == .x86_64; const is_aarch64 = arch == .aarch64 or arch == .aarch64_be; const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le; - const is_sparc = arch == .sparc or arch == .sparcel or arch == .sparcv9; + const is_sparc = arch == .sparc or arch == .sparcel or arch == .sparc64; const is_64 = arch.ptrBitWidth() == 64; const s = path.sep_str; @@ -1115,6 +1138,30 @@ fn buildSharedLib( try sub_compilation.updateSubCompilation(); } +fn glibcToZigArch(arch_tag: Arch) std.Target.Cpu.Arch { + return switch (arch_tag) { + .arm => .arm, + .armeb => .armeb, + .aarch64 => .aarch64, + .aarch64_be => .aarch64_be, + .mips => .mips, + .mipsel => .mipsel, + .mips64 => .mips64, + .mips64el => .mips64el, + .powerpc => .powerpc, + .powerpc64 => .powerpc64, + .powerpc64le => .powerpc64le, + .riscv32 => .riscv32, + .riscv64 => .riscv64, + .sparc => .sparc, + .sparcv9 => .sparc64, // In glibc, sparc64 is called sparcv9. + .sparcel => .sparcel, + .s390x => .s390x, + .i386 => .i386, + .x86_64 => .x86_64, + }; +} + // Return true if glibc has crti/crtn sources for that architecture. pub fn needsCrtiCrtn(target: std.Target) bool { return switch (target.cpu.arch) { diff --git a/src/link/Elf.zig b/src/link/Elf.zig index 11a701fcf9..be366076b4 100644 --- a/src/link/Elf.zig +++ b/src/link/Elf.zig @@ -307,7 +307,7 @@ pub fn createEmpty(gpa: Allocator, options: link.Options) !*Elf { const page_size: u32 = switch (options.target.cpu.arch) { .powerpc64le => 0x10000, - .sparcv9 => 0x2000, + .sparc64 => 0x2000, else => 0x1000, }; @@ -2940,7 +2940,7 @@ fn getLDMOption(target: std.Target) ?[]const u8 { .powerpc64 => return "elf64ppc", .powerpc64le => return "elf64lppc", .sparc, .sparcel => return "elf32_sparc", - .sparcv9 => return "elf64_sparc", + .sparc64 => return "elf64_sparc", .mips => return "elf32btsmip", .mipsel => return "elf32ltsmip", .mips64 => { diff --git a/src/link/Plan9/aout.zig b/src/link/Plan9/aout.zig index 39994516fa..09f39d8990 100644 --- a/src/link/Plan9/aout.zig +++ b/src/link/Plan9/aout.zig @@ -110,7 +110,7 @@ pub const R_MAGIC = _MAGIC(HDR_MAGIC, 28); // arm64 pub fn magicFromArch(arch: std.Target.Cpu.Arch) !u32 { return switch (arch) { .i386 => I_MAGIC, - .sparc => K_MAGIC, // TODO should sparcv9 and sparcel go here? + .sparc => K_MAGIC, // TODO should sparc64 and sparcel go here? .mips => V_MAGIC, .arm => E_MAGIC, .aarch64 => R_MAGIC, diff --git a/src/stage1/codegen.cpp b/src/stage1/codegen.cpp index d101030c33..d6fb6d4753 100644 --- a/src/stage1/codegen.cpp +++ b/src/stage1/codegen.cpp @@ -21,6 +21,7 @@ #include "zigendian.h" #include +#include #include #include @@ -3596,7 +3597,7 @@ static LLVMValueRef gen_soft_float_bin_op(CodeGen *g, LLVMValueRef op1_value, LL result = LLVMBuildLoad(g->builder, result, ""); } - // Some operations are implemented as compound ops and require us to perform some + // Some operations are implemented as compound ops and require us to perform some // more operations before we obtain the final result switch (op_id) { case IrBinOpDivTrunc: @@ -9983,6 +9984,12 @@ Buf *codegen_generate_builtin_source(CodeGen *g) { cur_arch = arch_name; } } + + // Workaround to LLVM/Zig naming mismatch. + // LLVM calls it sparcv9, while Zig calls it sparc64. + if (!strcmp(cur_arch, "sparcv9")) { + cur_arch = "sparc64"; + } } assert(cur_arch != nullptr); diff --git a/src/target.zig b/src/target.zig index 9249ed1b60..c794ea52b0 100644 --- a/src/target.zig +++ b/src/target.zig @@ -63,7 +63,7 @@ pub const available_libcs = [_]ArchOsAbi{ .{ .arch = .s390x, .os = .linux, .abi = .gnu }, .{ .arch = .s390x, .os = .linux, .abi = .musl }, .{ .arch = .sparc, .os = .linux, .abi = .gnu }, - .{ .arch = .sparcv9, .os = .linux, .abi = .gnu }, + .{ .arch = .sparc64, .os = .linux, .abi = .gnu }, .{ .arch = .wasm32, .os = .freestanding, .abi = .musl }, .{ .arch = .wasm32, .os = .wasi, .abi = .musl }, .{ .arch = .x86_64, .os = .linux, .abi = .gnu }, @@ -118,7 +118,7 @@ pub fn osArchName(target: std.Target) [:0]const u8 { .mips, .mipsel, .mips64, .mips64el => "mips", .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc", .riscv32, .riscv64 => "riscv", - .sparc, .sparcel, .sparcv9 => "sparc", + .sparc, .sparcel, .sparc64 => "sparc", .i386, .x86_64 => "x86", else => @tagName(target.cpu.arch), }, @@ -232,7 +232,7 @@ pub fn hasLlvmSupport(target: std.Target) bool { .riscv32, .riscv64, .sparc, - .sparcv9, + .sparc64, .sparcel, .s390x, .tce, @@ -351,7 +351,7 @@ pub fn archToLLVM(arch_tag: std.Target.Cpu.Arch) llvm.ArchType { .riscv32 => .riscv32, .riscv64 => .riscv64, .sparc => .sparc, - .sparcv9 => .sparcv9, + .sparc64 => .sparcv9, // In LLVM, sparc64 == sparcv9. .sparcel => .sparcel, .s390x => .systemz, .tce => .tce, @@ -617,7 +617,7 @@ pub fn atomicPtrAlignment( .powerpc64, .powerpc64le, .riscv64, - .sparcv9, + .sparc64, .s390x, .amdil64, .hsail64, @@ -723,7 +723,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u32 { return switch (target.cpu.arch) { .arm, .armeb => 4, .aarch64, .aarch64_32, .aarch64_be => 4, - .sparc, .sparcel, .sparcv9 => 4, + .sparc, .sparcel, .sparc64 => 4, .riscv64 => 2, else => 1, }; diff --git a/src/type.zig b/src/type.zig index 8742d9b61c..2c3ce0d900 100644 --- a/src/type.zig +++ b/src/type.zig @@ -6229,7 +6229,7 @@ pub const CType = enum { .mips64, .mips64el, .sparc, - .sparcv9, + .sparc64, .sparcel, .powerpc, .powerpcle, @@ -6267,7 +6267,7 @@ pub const CType = enum { .mips64, .mips64el, .sparc, - .sparcv9, + .sparc64, .sparcel, .powerpc, .powerpcle, diff --git a/test/behavior/align.zig b/test/behavior/align.zig index 6c1122323a..b89cd5ee69 100644 --- a/test/behavior/align.zig +++ b/test/behavior/align.zig @@ -135,7 +135,7 @@ test "alignment and size of structs with 128-bit fields" { .powerpc64, .powerpc64le, .riscv64, - .sparcv9, + .sparc64, .x86_64, .aarch64, .aarch64_be, diff --git a/test/behavior/vector.zig b/test/behavior/vector.zig index aaf61745b0..9847054692 100644 --- a/test/behavior/vector.zig +++ b/test/behavior/vector.zig @@ -604,7 +604,7 @@ test "vector shift operators" { .mips64, .mips64el, .riscv64, - .sparcv9, + .sparc64, => { // LLVM miscompiles on this architecture // https://github.com/ziglang/zig/issues/4951 diff --git a/test/cases/sparcv9-linux/hello_world.zig b/test/cases/sparc64-linux/hello_world.zig similarity index 94% rename from test/cases/sparcv9-linux/hello_world.zig rename to test/cases/sparc64-linux/hello_world.zig index 1aea9da7a3..b5a2562c44 100644 --- a/test/cases/sparcv9-linux/hello_world.zig +++ b/test/cases/sparc64-linux/hello_world.zig @@ -16,7 +16,7 @@ pub fn main() void { } // run -// target=sparcv9-linux +// target=sparc64-linux // // Hello, World! // diff --git a/tools/process_headers.zig b/tools/process_headers.zig index 579667a5a6..39fbe08a4a 100644 --- a/tools/process_headers.zig +++ b/tools/process_headers.zig @@ -170,13 +170,13 @@ const glibc_targets = [_]LibCTarget{ .abi = MultiAbi{ .specific = Abi.gnu }, }, LibCTarget{ - .name = "sparc64-linux-gnu", + .name = "sparc-linux-gnu", .arch = MultiArch{ .specific = Arch.sparc }, .abi = MultiAbi{ .specific = Abi.gnu }, }, LibCTarget{ .name = "sparcv9-linux-gnu", - .arch = MultiArch{ .specific = Arch.sparcv9 }, + .arch = MultiArch{ .specific = Arch.sparc64 }, .abi = MultiAbi{ .specific = Abi.gnu }, }, LibCTarget{