Jakub Konka
6608fa1353
Merge pull request #11628 from ziglang/x64-shifts
2022-05-11 08:24:03 +02:00
Andrew Kelley
b33c8b0b06
Sema: comptime float negation supports negative zero
...
When handling the `negate` ZIR instruction, Zig now checks for a
comptime operand and handles it as a special case rather than lowering
it as `0 - x` so that the expression `-x` where `x` is a floating point
value known at compile-time, will get the negative zero bitwise
representation.
2022-05-10 21:50:55 -07:00
Jakub Konka
3c69810fe6
x64: fix binary not implementation
2022-05-10 21:30:39 +02:00
Jakub Konka
f6f98a621f
x64: enable additional math test
2022-05-10 21:21:09 +02:00
Jakub Konka
1d3b714125
x64: implement shl with overflow for non-pow-2
2022-05-10 21:19:05 +02:00
Jakub Konka
d31875f7ab
x64: implement shl_with_overflow for powers of two
2022-05-10 20:53:44 +02:00
Jakub Konka
2a738599a0
x64: implement missing bits in add_with_overflow and sub_with_overflow
2022-05-10 20:45:57 +02:00
Jakub Konka
f131e41db9
x64: implement shl_exact and shr_exact
2022-05-10 19:34:20 +02:00
Jakub Konka
9c3d24ea0b
x64: add naive impl of shr
2022-05-09 17:39:19 +02:00
Luuk de Gram
a110979582
stage2: Split @mulWithOverflow tests
2022-05-07 20:02:02 +02:00
Jakub Konka
c592f0ca21
test: pass extended mul_with_overflow tests on x64
2022-05-05 22:53:11 +02:00
Jakub Konka
eab5a1bd5a
test: test bitwidths between 1...8 and 8...16 for mul_with_overflow
2022-05-05 21:43:36 +02:00
Jakub Konka
3cef23129a
test: test more int sizes for @mulWithOverflow builtin
2022-05-05 21:43:36 +02:00
Jakub Konka
8715b01005
aarch64: implement mul_with_overflow for <= 32bit ints
...
Add emitters for `smull`, `umull` and `tst (immediate)` instructions.
2022-05-05 21:43:36 +02:00
joachimschmidt557
aaacda4df9
stage2 AArch64: implement shl_with_overflow
2022-05-05 21:43:35 +02:00
joachimschmidt557
c2d2307d09
stage2 AArch64: initial implementation of {add,sub}_with_overflow
2022-05-05 21:43:35 +02:00
Marc Tiehuis
5fbda2c579
temporary fix for stage2/stage1 f128 rounding discrepency
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This is only to get tests running again. The root issue should be fixed
in stage1 so rounding is consistent between stages.
2022-05-03 17:14:01 +12:00
Andrew Kelley
9d098657a0
stage1: fix i386-windows f80 sizeof/alignof
2022-04-27 22:57:12 -07:00
Andrew Kelley
7d8067878d
disable failing behavior test
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This is a new test added in this branch but it is not yet passing for
i386-windows with the stage1 compiler.
2022-04-27 18:41:53 -07:00
Andrew Kelley
758ec9bdd4
enable newly passing behavior tests
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closes #11030
2022-04-27 17:24:36 -07:00
Andrew Kelley
c4eaff6665
disable failing behavior tests
2022-04-27 14:29:59 -07:00
Andrew Kelley
41dd2beaac
compiler-rt: math functions reorg
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* unify the logic for exporting math functions from compiler-rt,
with the appropriate suffixes and prefixes.
- add all missing f128 and f80 exports. Functions with missing
implementations call other functions and have TODO comments.
- also add f16 functions
* move math functions from freestanding libc to compiler-rt (#7265 )
* enable all the f128 and f80 code in the stage2 compiler and behavior
tests (#11161 ).
* update std lib to use builtins rather than `std.math`.
2022-04-27 12:20:44 -07:00
joachimschmidt557
fa85a739d9
stage2 AArch64: fix shl, shr, shl_exact, shr_exact
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Introduces the necessary truncation after shift
2022-04-19 22:40:51 +02:00
joachimschmidt557
0a909a6712
stage2 AArch64: implement addwrap, subwrap, mulwrap
2022-04-19 22:40:50 +02:00
Cody Tapscott
1c1cfe1533
Skip @rem/@mod tests on stage2, due to missing fmodl implementation
2022-04-12 10:25:29 -07:00
Luuk de Gram
a0a587ff85
wasm: Enable passing behavior tests
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This shuffles some tests do ensure the new instructions are tested for the wasm backend,
by moving vectors into their own tests as well as move the f16 test cases as those require
special operating also.
2022-04-02 21:54:01 +02:00
joachimschmidt557
c4778fc029
stage2 ARM: implement mul_with_overflow for ints <= 16 bits
2022-04-01 22:02:56 +02:00
joachimschmidt557
77e70189f4
stage2 ARM: implement shl_with_overflow for ints <= 32 bits
2022-04-01 22:02:56 +02:00
joachimschmidt557
37a8c28802
stage2 ARM: implement add/sub_with_overflow for ints < 32 bits
2022-04-01 22:02:56 +02:00
Jakub Konka
fd29ddc06c
x64: implement add/sub with wrapping and xor op
2022-04-01 11:37:18 +02:00
Meghan
b73cf97c93
replace other uses of std.meta.Vector with @Vector ( #11346 )
2022-03-30 14:12:14 -04:00
Jakub Konka
ee6e3aef5d
x64: redo @mulWithOverflow using rax/rdx based multiplication
2022-03-30 00:37:42 +02:00
Jakub Konka
e6729036e4
x64: partially fix genImul, enable overflow tests
2022-03-28 17:45:50 +02:00
Luuk de Gram
e1bb09648f
wasm: Enable overflow behavior tests
2022-03-27 19:02:45 +02:00
William Sengir
b872539a13
stage2: enable some passing array & vector tests
2022-03-23 16:39:29 -04:00
Daniele Cocca
b6203b89d6
CBE: implement mod, divFloor, divTrunc
2022-03-19 21:01:36 -04:00
Daniele Cocca
00ed8d9c50
CBE: enable more tests that are currently passing
2022-03-17 11:39:56 -07:00
Joachim Schmidt
3c3826bf93
Merge pull request #11192 from joachimschmidt557/stage2-arm
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stage2 ARM: misc improvements
2022-03-17 09:40:41 +01:00
Mitchell Hashimoto
79d3780fbd
stage2: bit_not on u0 is always 0
2022-03-16 23:18:35 -07:00
joachimschmidt557
dcc1de12b0
stage2 ARM: implement addwrap, subwrap, mulwrap
2022-03-16 20:20:07 +01:00
joachimschmidt557
2412ac2c5f
stage2 ARM: fix shl for ints with bits < 32
2022-03-16 20:20:07 +01:00
joachimschmidt557
0eebdfcad3
stage2 ARM: fix bitwise negation of ints with bits < 32
2022-03-16 20:20:07 +01:00
Andrew Kelley
84f96779c3
Merge pull request #11143 from jmc-88/cbe
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CBE: Implement popCount, byteSwap, bitReverse for ints <= 128 bits
2022-03-14 18:23:00 -04:00
Daniele Cocca
8643591c9a
CBE: split {clz,ctz,mod,popCount,byteSwap,bitReverse} by type
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This also surfaces the fact that clz, ctz and popCount didn't actually
support 128 bit integers, despite what was claimed by
226fcd7c70
2022-03-14 19:43:31 +00:00
Andrew Kelley
b2a1b4c085
Sema: improve lowering of stores to bitcasted vector pointers
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Detect if we are storing an array operand to a bitcasted vector pointer.
If so, we instead reach through the bitcasted pointer to the vector pointer,
bitcast the array operand to a vector, and then lower this as a store of
a vector value to a vector pointer. This generally results in better code,
as well as working around an LLVM bug.
See #11154
2022-03-14 00:11:46 -07:00
joachimschmidt557
b74cd902c6
stage2 AArch64: enable mul for ints with <= 64 bits
2022-03-13 11:32:08 +01:00
joachimschmidt557
12207bbbd6
stage2 AArch64: Implement bit shifting with immediate operands
2022-03-13 11:32:07 +01:00
Daniele Cocca
226fcd7c70
CBE: implement clz, ctz for ints <= 128 bits
2022-03-11 23:12:15 +00:00
Luuk de Gram
90f08a69aa
wasm: Enable passing behavior tests
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This also adds some float-related instructions to MIR/Emit
2022-03-09 13:53:20 -07:00
joachimschmidt557
a06e9eca45
stage2 AArch64: add more slice support
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* airSlice
* airArrayToSlice
* and initial support for airSlicePtr and co
2022-03-05 11:31:51 +01:00
