Commit graph

196 commits

Author SHA1 Message Date
Andrew Kelley
34f64432b0 remove usingnamespace from the language
closes #20663
2025-07-07 13:39:48 -07:00
Jacob Young
1f98c98fff x86_64: increase passing test coverage on windows
Now that codegen has no references to linker state this is much easier.

Closes #24153
2025-06-19 18:41:12 -04:00
Ali Cheraghi
872f68c9cb
rename spirv backend name
`stage2_spirv64` -> `stage2_spirv`
2025-06-16 13:22:19 +03:30
Jacob Young
b483defc5a Legalize: implement scalarization of binary operations 2025-05-31 18:54:28 -04:00
Alex Rønne Petersen
b3f52ae339
test: Disable arrays and vectors with big integers on MIPS N32.
https://github.com/ziglang/zig/issues/23805
2025-05-08 21:32:22 +02:00
Ali Cheraghi
aec0f9b3e7
test: skip failing tests with spirv-vulkan 2025-02-24 19:39:42 +01:00
Jacob Young
c3d33440f0 x86_64: pass more behavior tests 2025-01-16 20:47:30 -05:00
Jacob Young
666d76d85c x86_64: implement load and store 2025-01-16 20:47:30 -05:00
kcbanner
2d888a8e63 tests: re-enable tests that now pass on aarch64-windows 2024-10-22 11:39:29 +02:00
Robin Voetter
86b88ea7da
spirv: skip range switch tests
This is not yet implemented
2024-10-13 01:58:11 +02:00
Meghan Denny
5e4da1ff30
std: add arch bits for s390x-linux (#21342)
see #21402
2024-09-24 13:35:12 -07:00
Alex Rønne Petersen
5cb9668632 test: Re-enable a bunch of behavior tests with LLVM.
Closes #10627.
Closes #12013.
Closes #18034.
2024-09-12 07:28:37 +02:00
mlugg
0fe3fd01dd
std: update std.builtin.Type fields to follow naming conventions
The compiler actually doesn't need any functional changes for this: Sema
does reification based on the tag indices of `std.builtin.Type` already!
So, no zig1.wasm update is necessary.

This change is necessary to disallow name clashes between fields and
decls on a type, which is a prerequisite of #9938.
2024-08-28 08:39:59 +01:00
mlugg
f47f6d766e
behavior,cases: add @branchHint test coverage 2024-08-27 00:44:35 +01:00
mlugg
6808ce27bd
compiler,lib,test,langref: migrate @setCold to @branchHint 2024-08-27 00:44:35 +01:00
mlugg
a3a737e9a6
lib,test,tools,doc: update usages of @export 2024-08-27 00:44:35 +01:00
David Rubin
2e8351cc9e elf: fix up riscv for .got.zig rewrite 2024-08-15 08:53:41 +02:00
David Rubin
8da212c11b
riscv: update tests and fix reuse bug 2024-07-26 04:19:58 -07:00
David Rubin
a1f6a8ef90
riscv: airAsm rewrite
with this rewrite we can call functions inside of
inline assembly, enabling us to use the default start.zig logic

all that's left is to implement lr/sc loops for atomically manipulating
1 and 2 byte values, after which we can use the segfault handler logic.
2024-07-26 04:19:55 -07:00
David Rubin
b533e848a2
riscv: enable passing tests 2024-07-26 04:19:17 -07:00
David Rubin
81ca3a1d59
riscv: fix logic bug in ptr_elem_ptr
I was doing duplicate work with `elemOffset` multiplying by the abi size and then the `ptr_add` `genBinOp` also multiplying.

This led to having writes happening in the wrong place.
2024-07-26 04:05:41 -07:00
David Rubin
8d30fc45c4
riscv: implement more operators
we can run `std.debug.print` now, with both run-time strings and integers!
2024-07-26 04:05:39 -07:00
Pavel Verigo
d1bd9518f9 stage2-wasm: fix big int comparison
Unexpected to be found only now
2024-07-18 17:18:17 +02:00
David Rubin
4fd8900337
riscv: rewrite "binOp"
Reorganize how the binOp and genBinOp functions work.

I've spent quite a while here reading exactly through the spec and so many
tests are enabled because of several critical issues the old design had.

There are some regressions that will take a long time to figure out individually
so I will ignore them for now, and pray they get fixed by themselves. When
we're closer to 100% passing is when I will start diving into them one-by-one.
2024-06-13 02:24:39 -07:00
David Rubin
a270c6f8c8
riscv: implement optional logic 2024-06-13 02:22:33 -07:00
David Rubin
b67995689d
riscv: add airAggregateInit for arrays 2024-06-13 02:22:04 -07:00
David Rubin
05de6c279b
riscv: std.fmt.format running
- implements `airSlice`, `airBitAnd`, `airBitOr`, `airShr`.

- got a basic design going for the `airErrorName` but for some reason it simply returns
empty bytes. will investigate further.

- only generating `.got.zig` entries when not compiling an object or shared library

- reduced the total amount of ops a mnemonic can have to 3, simplifying the logic
2024-06-13 02:20:47 -07:00
David Rubin
ffb63a05a3 riscv: finally fix bug + airAggregateInit
i just hadn't realized that I placed the `riscv_start` branch in the non-simplified
starts
2024-05-11 02:17:24 -07:00
David Rubin
2fd83d8c0a riscv: by-value structs + @min 2024-05-11 02:17:24 -07:00
David Rubin
a30af172e8 riscv: math progress 2024-05-11 02:17:24 -07:00
David Rubin
a615fbc1f8 riscv: mutable globals 2024-05-11 02:17:24 -07:00
David Rubin
d9e0cafe64 riscv: add stage2_riscv to test matrix and bypass failing tests 2024-05-11 02:17:24 -07:00
mlugg
152a2ceaf7
compiler: audit uses of ptr.addr in the frontend
This commit also performs some refactors to `TypedValue.print` in
preparation for improved comptime pointer access logic. Once that logic
exists, `TypedValue.print` can use Sema to access pointers for more
helpful printing.

This commit also implements proposal #19435, because the existing logic
there relied on some blatantly incorrect code in `Value.sliceLen`.

Resolves: #19435
2024-03-26 13:48:06 +00:00
Robin Voetter
9b18125562
spirv: make generic globals invocation-local 2024-03-18 19:13:50 +01:00
Ali Chraghi
37b0aa600a spirv: make rusticl the primary testing implementation 2024-02-09 09:27:08 +03:30
Jakub Konka
52066bf8e4 x86_64+macho: pass more behavior tests 2024-02-06 19:01:17 +01:00
Andrew Kelley
5cf138e512 delete bad behavior test
As pointed out in the issue this behavior test branches on an undefined
value. That's not valid Zig code.

Also behavior tests should not depend on the standard library in this
manner. They need to minimally isolate the specific language thing that
is being tested.

Closes #12681
2024-02-05 23:47:05 -07:00
Robin Voetter
9fbba0e01a
spirv: update tests 2024-02-04 19:09:33 +01:00
Veikka Tuominen
f93a36c091 llvm: revert bad array access optimization
Closes #18723
2024-01-29 08:43:27 -08:00
dweiller
8108c9f4d2 test/behavior: replace all 'comptime expect' with 'comptime assert' 2024-01-15 20:55:01 +11:00
Veikka Tuominen
804cee3b93 categorize behavior/bugs/<issueno>.zig tests 2024-01-06 16:49:41 -08:00
Robin Voetter
28e1d82857
spirv: disable failing tests 2023-11-24 01:11:12 +01:00
mlugg
9c16b2370d
test: update behavior to silence 'var is never mutated' errors 2023-11-19 09:57:03 +00:00
Jacob Young
27fe945a00 Revert "Revert "Merge pull request #17637 from jacobly0/x86_64-test-std""
This reverts commit 6f0198cadb.
2023-10-22 15:46:43 -04:00
Andrew Kelley
6f0198cadb Revert "Merge pull request #17637 from jacobly0/x86_64-test-std"
This reverts commit 0c99ba1eab, reversing
changes made to 5f92b070bf.

This caused a CI failure when it landed in master branch due to a
128-bit `@byteSwap` in std.mem.
2023-10-22 12:16:35 -07:00
Jacob Young
9358a7528f x86_64: fix crashes 2023-10-21 10:55:41 -04:00
Ali Chraghi
e5d5c1d423 spirv: switch on bool 2023-10-18 02:31:16 +03:30
Robin Voetter
faad97edff
spirv: update failing / passing tests
Some tests are now failing due to debug info changes, some tests
now pass due to improved compiler functionality.
2023-10-15 20:08:18 +02:00
Robin Voetter
3ca1f88898
std.testing: disable expectEqualSlices printing for spirv 2023-10-15 14:00:26 +02:00
Robin Voetter
89b1dafa78
spirv: aggregate_init for structs 2023-10-15 13:59:55 +02:00