David Rubin
05de6c279b
riscv: std.fmt.format running
...
- implements `airSlice`, `airBitAnd`, `airBitOr`, `airShr`.
- got a basic design going for the `airErrorName` but for some reason it simply returns
empty bytes. will investigate further.
- only generating `.got.zig` entries when not compiling an object or shared library
- reduced the total amount of ops a mnemonic can have to 3, simplifying the logic
2024-06-13 02:20:47 -07:00
David Rubin
d9e0cafe64
riscv: add stage2_riscv to test matrix and bypass failing tests
2024-05-11 02:17:24 -07:00
Robin Voetter
faad97edff
spirv: update failing / passing tests
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Some tests are now failing due to debug info changes, some tests
now pass due to improved compiler functionality.
2023-10-15 20:08:18 +02:00
Ali Chraghi
ccc490ef68
setup spirv backend in behavior tests
2023-05-11 20:31:52 +02:00
Jacob Young
f316cb29cc
x86_64: implement atomic and fence ops
2023-03-21 08:49:54 +01:00
joachimschmidt557
d6e6162081
stage2 AArch64: unify callee-preserved regs on all targets
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also enables many passing behavior tests
2022-12-27 21:17:52 +08:00
Koakuma
f9e9ba784f
stage2: sparc64: Skip unimplemented tests
2022-12-10 21:51:46 +07:00
joachimschmidt557
261fec8036
stage2 ARM: amend implementation of various AIR instructions
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- unwrap_errunion_err for registers
- unwrap_errunion_payload for registers
- ptr_slice_len_ptr for all MCValues
- ptr_slice_ptr_ptr for all MCValues
2022-09-09 19:17:17 +02:00
Daniele Cocca
00ed8d9c50
CBE: enable more tests that are currently passing
2022-03-17 11:39:56 -07:00
Luuk de Gram
90f08a69aa
wasm: Enable passing behavior tests
...
This also adds some float-related instructions to MIR/Emit
2022-03-09 13:53:20 -07:00
Andrew Kelley
4307436b99
move behavior tests from test/stage1/ to test/
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And fix test cases to make them pass. This is in preparation for
starting to pass behavior tests with self-hosted.
2021-04-29 15:54:04 -07:00
