Commit graph

185 commits

Author SHA1 Message Date
Alex Rønne Petersen
1f2e3b39ae
test: Disable vector division operators on RISC-V with vector support
https://github.com/ziglang/zig/issues/24301
2025-07-01 23:03:15 +02:00
Jacob Young
1f98c98fff x86_64: increase passing test coverage on windows
Now that codegen has no references to linker state this is much easier.

Closes #24153
2025-06-19 18:41:12 -04:00
Ali Cheraghi
872f68c9cb
rename spirv backend name
`stage2_spirv64` -> `stage2_spirv`
2025-06-16 13:22:19 +03:30
Daniel Kongsgaard
5e3c0b7af7
Allow more operators on bool vectors (#24131)
* Sema: allow binary operations and boolean not on vectors of bool

* langref: Clarify use of operators on vectors (`and` and `or` not allowed)

closes #24093
2025-06-12 15:16:23 -07:00
Danielkonge
f4c7290bc5 test: Enable some working vector tests
Closes #12827.
2025-06-11 22:29:51 +02:00
Alex Rønne Petersen
9d534790eb std.Target: Introduce Cpu convenience functions for feature tests.
Before:

* std.Target.arm.featureSetHas(target.cpu.features, .has_v7)
* std.Target.x86.featureSetHasAny(target.cpu.features, .{ .sse, .avx, .cmov })
* std.Target.wasm.featureSetHasAll(target.cpu.features, .{ .atomics, .bulk_memory })

After:

* target.cpu.has(.arm, .has_v7)
* target.cpu.hasAny(.x86, &.{ .sse, .avx, .cmov })
* target.cpu.hasAll(.wasm, &.{ .atomics, .bulk_memory })
2025-06-05 06:12:00 +02:00
Jacob Young
2543e2d97c x86_64: implement integer @divFloor and @mod
Closes #24039
2025-06-02 22:45:15 -04:00
Jacob Young
9edfccb9a7
Legalize: implement scalarization of overflow intrinsics 2025-06-01 08:24:01 +01:00
Jacob Young
ec579aa0f3
Legalize: implement scalarization of @shuffle 2025-06-01 08:24:01 +01:00
Jacob Young
b483defc5a Legalize: implement scalarization of binary operations 2025-05-31 18:54:28 -04:00
Jacob Young
9f9e7e398f x86_64: implement strict float @reduce(.Max) 2025-05-28 15:10:22 -04:00
Jacob Young
1f6f8b0ffe x86_64: implement integer @reduce(.Add) 2025-05-28 15:10:22 -04:00
Jacob Young
a4eabd3979 x86_64: implement vector_store_elem 2025-05-17 20:31:25 -04:00
Jacob Young
a3b0c242b0 x86_64: rewrite @splat 2025-05-17 18:00:17 -04:00
Jacob Young
96e35b3652 x86_64: rewrite vector -| 2025-05-17 02:08:41 -04:00
Jacob Young
6d68a494c8 x86_64: rewrite vector +| 2025-05-17 02:08:41 -04:00
Alex Rønne Petersen
12f56b8740
test: Disable vector reduce operation for sparc.
https://github.com/ziglang/zig/issues/23719
2025-04-28 12:05:19 +02:00
Alex Rønne Petersen
96fe4fb969
Revert "test: Partially disable vector float operators on mips."
This reverts commit 19a91084c2.

Closes #21051.
2025-04-04 06:08:10 +02:00
mlugg
2a4e06bcb3 Sema: rewrite comptime arithmetic
This commit reworks how Sema handles arithmetic on comptime-known
values, fixing many bugs in the process.

The general pattern is that arithmetic on comptime-known values is now
handled by the new namespace `Sema.arith`. Functions handling comptime
arithmetic no longer live on `Value`; this is because some of them can
emit compile errors, so some *can't* go on `Value`. Only semantic
analysis should really be doing arithmetic on `Value`s anyway, so it
makes sense for it to integrate more tightly with `Sema`.

This commit also implements more coherent rules surrounding how
`undefined` interacts with comptime and mixed-comptime-runtime
arithmetic. The rules are as follows.

* If an operation cannot trigger Illegal Behavior, and any operand is
  `undefined`, the result is `undefined`. This includes operations like
  `0 *| undef`, where the LHS logically *could* be used to determine a
  defined result. This is partly to simplify the language, but mostly to
  permit codegen backends to represent `undefined` values as completely
  invalid states.

* If an operation *can* trigger Illegal Behvaior, and any operand is
  `undefined`, then Illegal Behavior results. This occurs even if the
  operand in question isn't the one that "decides" illegal behavior; for
  instance, `undef / 1` is undefined. This is for the same reasons as
  described above.

* An operation which would trigger Illegal Behavior, when evaluated at
  comptime, instead triggers a compile error. Additionally, if one
  operand is comptime-known undef, such that the other (runtime-known)
  operand isn't needed to determine that Illegal Behavior would occur,
  the compile error is triggered.

* The only situation in which an operation with one comptime-known
  operand has a comptime-known result is if that operand is undefined,
  in which case the result is either undefined or a compile error per
  the above rules. This could potentially be loosened in future (for
  instance, `0 * rt` could be comptime-known 0 with a runtime assertion
  that `rt` is not undefined), but at least for now, defining it more
  conservatively simplifies the language and allows us to easily change
  this in future if desired.

This commit fixes many bugs regarding the handling of `undefined`,
particularly in vectors. Along with a collection of smaller tests, two
very large test cases are added to check arithmetic on `undefined`.

The operations which have been rewritten in this PR are:

* `+`, `+%`, `+|`, `@addWithOverflow`
* `-`, `-%`, `-|`, `@subWithOverflow`
* `*`, `*%`, `*|`, `@mulWithOverflow`
* `/`, `@divFloor`, `@divTrunc`, `@divExact`
* `%`, `@rem`, `@mod`

Other arithmetic operations are currently unchanged.

Resolves: #22743
Resolves: #22745
Resolves: #22748
Resolves: #22749
Resolves: #22914
2025-03-16 08:17:50 +00:00
Ali Cheraghi
aec0f9b3e7
test: skip failing tests with spirv-vulkan 2025-02-24 19:39:42 +01:00
Jacob Young
fa9b0fa6d3 x86_64: rewrite most of the remaining float ops 2025-02-06 16:14:53 -05:00
Jacob Young
c3d33440f0 x86_64: pass more behavior tests 2025-01-16 20:47:30 -05:00
Jacob Young
e5d5a8bc4e x86_64: implement switch jump tables 2025-01-16 20:42:08 -05:00
Jacob Young
ac1a975f9b x86_64: implement clz and not 2025-01-16 20:42:08 -05:00
Alex Rønne Petersen
52e9fd7c3c
test: Disable vector behavior tests affected by #22060 for thumbeb too. 2025-01-06 16:20:27 +01:00
Alex Rønne Petersen
1e61399537
test: Disable some vector behavior tests on armeb.
https://github.com/ziglang/zig/issues/22060
2024-12-13 03:13:14 +01:00
Alex Rønne Petersen
2958a90515
test: Disable some vector behavior tests on aarch64_be.
See: https://github.com/ziglang/zig/issues/21893
2024-11-04 08:29:42 +01:00
Alex Rønne Petersen
c9e67e71c1
std.Target: Replace isARM() with isArmOrThumb() and rename it to isArm().
The old isARM() function was a portability trap. With the name it had, it seemed
like the obviously correct function to use, but it didn't include Thumb. In the
vast majority of cases where someone wants to ask "is the target Arm?", Thumb
*should* be included.

There are exactly 3 cases in the codebase where we do actually need to exclude
Thumb, although one of those is in Aro and mirrors a check in Clang that is
itself likely a bug. These rare cases can just add an extra isThumb() check.
2024-11-03 09:29:30 +01:00
Alex Rønne Petersen
f8719c4197 test: Re-enable store vector with memset for LLVM.
Closes #16177.
2024-09-19 18:20:21 -07:00
Alex Rønne Petersen
5cb9668632 test: Re-enable a bunch of behavior tests with LLVM.
Closes #10627.
Closes #12013.
Closes #18034.
2024-09-12 07:28:37 +02:00
Andrew Kelley
4fba7336a9
Merge pull request #21269 from alexrp/soft-float
Fix soft float support, split musl triples by float ABI, and enable CI
2024-09-11 17:41:55 -07:00
Alex Rønne Petersen
5285f41267
test: Disable store vector with memset on soft float arm.
https://github.com/ziglang/zig/issues/16177
2024-09-10 08:53:30 +02:00
Alex Rønne Petersen
ccf852c31e
test: Re-enable vector reduce operation for most LLVM targets.
mips64 failure is tracked in #21091.

Closes #7138.
2024-09-07 02:47:57 +02:00
Alex Rønne Petersen
5c128a8990
test: Re-enable vector shift operators for all LLVM targets.
Closes #4951.
2024-09-07 02:47:57 +02:00
Alex Rønne Petersen
40ee682517
test: Disable store vector with memset on powerpc64.
This will be re-enabled with LLVM 19.
2024-09-05 01:15:33 +02:00
mlugg
0fe3fd01dd
std: update std.builtin.Type fields to follow naming conventions
The compiler actually doesn't need any functional changes for this: Sema
does reification based on the tag indices of `std.builtin.Type` already!
So, no zig1.wasm update is necessary.

This change is necessary to disallow name clashes between fields and
decls on a type, which is a prerequisite of #9938.
2024-08-28 08:39:59 +01:00
Alex Rønne Petersen
ecbc701376 test: Disable vector reduce operation on mips64.
https://github.com/ziglang/zig/issues/21091
2024-08-18 07:27:23 +02:00
Alex Rønne Petersen
19a91084c2
test: Partially disable vector float operators on mips.
https://github.com/ziglang/zig/issues/21051
2024-08-12 13:34:19 +02:00
Alex Rønne Petersen
d1d95294fd std.Target.Cpu.Arch: Remove the aarch64_32 tag.
This is a misfeature that we inherited from LLVM:

* https://reviews.llvm.org/D61259
* https://reviews.llvm.org/D61939

(`aarch64_32` and `arm64_32` are equivalent.)

I truly have no idea why this triple passed review in LLVM. It is, to date, the
*only* tag in the architecture component that is not, in fact, an architecture.
In reality, it is just an ILP32 ABI for AArch64 (*not* AArch32).

The triples that use `aarch64_32` look like `aarch64_32-apple-watchos`. Yes,
that triple is exactly what you think; it has no ABI component. They really,
seriously did this.

Since only Apple could come up with silliness like this, it should come as no
surprise that no one else uses `aarch64_32`. Later on, a GNU ILP32 ABI for
AArch64 was developed, and support was added to LLVM:

* https://reviews.llvm.org/D94143
* https://reviews.llvm.org/D104931

Here, sanity seems to have prevailed, and a triple using this ABI looks like
`aarch64-linux-gnu_ilp32` as you would expect.

As can be seen from the diffs in this commit, there was plenty of confusion
throughout the Zig codebase about what exactly `aarch64_32` was. So let's just
remove it. In its place, we'll use `aarch64-watchos-ilp32`,
`aarch64-linux-gnuilp32`, and so on. We'll then translate these appropriately
when talking to LLVM. Hence, this commit adds the `ilp32` ABI tag (we already
have `gnuilp32`).
2024-07-28 19:44:52 -07:00
David Rubin
81ca3a1d59
riscv: fix logic bug in ptr_elem_ptr
I was doing duplicate work with `elemOffset` multiplying by the abi size and then the `ptr_add` `genBinOp` also multiplying.

This led to having writes happening in the wrong place.
2024-07-26 04:05:41 -07:00
David Rubin
cde6956b21
riscv: remove redundant assert in genBinOp 2024-07-26 04:05:41 -07:00
David Rubin
9766b68c47
riscv: un-cache the avl and vtype when returning from a function call
the csrs `avl` and `vtype` are considered caller-saved so it could have changed while inside of the function.
the easiest way to handle this is to just set the cached `vtype` and `avl` to null, so that the next time something
needs to set it, it'll emit an instruction instead of relying on a potentially invalid setting.
2024-07-26 04:05:38 -07:00
Julian Vesper
3344ed8b8f aarch64: reenable tests that are no longer regressed
Closes #12012
2024-07-25 20:23:23 +03:00
Jacob Young
40bab4df69 behavior: disable test that triggers an llvm assertion
Tracked by #20680
2024-07-19 04:35:11 -04:00
David Rubin
5a4fe39fbb
riscv: disable failing tests 2024-07-14 23:04:06 -07:00
David Rubin
5a2c547fc1
riscv: vectors part 3 2024-07-14 23:02:35 -07:00
David Rubin
7a02878f4e
riscv: truncate airStructFieldVal result 2024-07-14 23:02:33 -07:00
David Rubin
4fd8900337
riscv: rewrite "binOp"
Reorganize how the binOp and genBinOp functions work.

I've spent quite a while here reading exactly through the spec and so many
tests are enabled because of several critical issues the old design had.

There are some regressions that will take a long time to figure out individually
so I will ignore them for now, and pray they get fixed by themselves. When
we're closer to 100% passing is when I will start diving into them one-by-one.
2024-06-13 02:24:39 -07:00
David Rubin
031d8248e0
riscv: first sign of floats! 2024-06-13 02:21:38 -07:00
Robin Voetter
a3b1ba82f5
spirv: new vectorization helper
The old vectorization helper (WipElementWise) was clunky and a bit
annoying to use, and it wasn't really flexible enough.

This introduces a new vectorization helper, which uses Temporary and
Operation types to deduce a Vectorization to perform the operation
in a reasonably efficient manner. It removes the outer loop
required by WipElementWise so that implementations of AIR instructions
are cleaner. This helps with sanity when we start to introduce support
for composite integers.

airShift, convertToDirect, convertToIndirect, and normalize are initially
implemented using this new method.
2024-06-10 20:32:49 +02:00