Commit graph

2131 commits

Author SHA1 Message Date
mlugg
4c0f021c2e
behavior: import unintentionally excluded file from behavior.zig
And remove the now-invalid test for the return value of `@branchHint`.
2024-08-27 00:44:35 +01:00
mlugg
f47f6d766e
behavior,cases: add @branchHint test coverage 2024-08-27 00:44:35 +01:00
mlugg
6808ce27bd
compiler,lib,test,langref: migrate @setCold to @branchHint 2024-08-27 00:44:35 +01:00
mlugg
a3a737e9a6
lib,test,tools,doc: update usages of @export 2024-08-27 00:44:35 +01:00
Alex Rønne Petersen
ecbc701376 test: Disable vector reduce operation on mips64.
https://github.com/ziglang/zig/issues/21091
2024-08-18 07:27:23 +02:00
Alex Rønne Petersen
d4d6b23d64 test: Disable @min/max for floats on mips64.
https://github.com/ziglang/zig/issues/21090
2024-08-18 07:27:23 +02:00
Jakub Konka
90989be0e3
Merge pull request #21065 from ziglang/elf-zig-got
elf: replace .got.zig with a zig jump table
2024-08-16 21:19:44 +02:00
David Rubin
2e8351cc9e elf: fix up riscv for .got.zig rewrite 2024-08-15 08:53:41 +02:00
Alex Rønne Petersen
19a91084c2
test: Partially disable vector float operators on mips.
https://github.com/ziglang/zig/issues/21051
2024-08-12 13:34:19 +02:00
Alex Rønne Petersen
abf6f35654
test: Disable reinterpret packed union on mips.
https://github.com/ziglang/zig/issues/21050
2024-08-12 13:34:19 +02:00
mlugg
548a087faf
compiler: split Decl into Nav and Cau
The type `Zcu.Decl` in the compiler is problematic: over time it has
gained many responsibilities. Every source declaration, container type,
generic instantiation, and `@extern` has a `Decl`. The functions of
these `Decl`s are in some cases entirely disjoint.

After careful analysis, I determined that the two main responsibilities
of `Decl` are as follows:
* A `Decl` acts as the "subject" of semantic analysis at comptime. A
  single unit of analysis is either a runtime function body, or a
  `Decl`. It registers incremental dependencies, tracks analysis errors,
  etc.
* A `Decl` acts as a "global variable": a pointer to it is consistent,
  and it may be lowered to a specific symbol by the codegen backend.

This commit eliminates `Decl` and introduces new types to model these
responsibilities: `Cau` (Comptime Analysis Unit) and `Nav` (Named
Addressable Value).

Every source declaration, and every container type requiring resolution
(so *not* including `opaque`), has a `Cau`. For a source declaration,
this `Cau` performs the resolution of its value. (When #131 is
implemented, it is unsolved whether type and value resolution will share
a `Cau` or have two distinct `Cau`s.) For a type, this `Cau` is the
context in which type resolution occurs.

Every non-`comptime` source declaration, every generic instantiation,
and every distinct `extern` has a `Nav`. These are sent to codegen/link:
the backends by definition do not care about `Cau`s.

This commit has some minor technically-breaking changes surrounding
`usingnamespace`. I don't think they'll impact anyone, since the changes
are fixes around semantics which were previously inconsistent (the
behavior changed depending on hashmap iteration order!).

Aside from that, this changeset has no significant user-facing changes.
Instead, it is an internal refactor which makes it easier to correctly
model the responsibilities of different objects, particularly regarding
incremental compilation. The performance impact should be negligible,
but I will take measurements before merging this work into `master`.

Co-authored-by: Jacob Young <jacobly0@users.noreply.github.com>
Co-authored-by: Jakub Konka <kubkon@jakubkonka.com>
2024-08-11 07:29:41 +01:00
Andrew Kelley
cf87a1a7cf language: add module name field to @src
closes #20963
2024-08-08 07:47:14 -07:00
Alex Rønne Petersen
e5c75479c2
std.Target: Rework isPPC()/isPPC64() functions.
* Rename isPPC() -> isPowerPC32().
* Rename isPPC64() -> isPowerPC64().
* Add new isPowerPC() function which covers both.

There was confusion even in the standard library about what isPPC() meant. This
change makes these functions work how I think most people actually expect them
to work, and makes them consistent with isMIPS(), isSPARC(), etc.

I chose to rename from PPC to PowerPC because 1) it's more consistent with the
other functions, and 2) it'll cause loud rather than silent breakage for anyone
who might have been depending on isPPC() while misunderstanding it.
2024-08-01 20:58:05 +02:00
Andrew Kelley
8f7cbaa4c0
Merge pull request #20870 from alexrp/target-cleanup-3
`std.Target`: Remove more dead OS/architecture tags
2024-08-01 01:32:32 -07:00
David Rubin
c08effc20a riscv: implement non-pow2 indirect loads 2024-07-31 16:57:30 -07:00
Alex Rønne Petersen
c8ca05e93a
std.Target: Remove sparcel architecture tag.
What is `sparcel`, you might ask? Good question!

If you take a peek in the SPARC v8 manual, §2.2, it is quite explicit that SPARC
v8 is a big-endian architecture. No little-endian or mixed-endian support to be
found here.

On the other hand, the SPARC v9 manual, in §3.2.1.2, states that it has support
for mixed-endian operation, with big-endian mode being the default.

Ok, so `sparcel` must just be referring to SPARC v9 running in little-endian
mode, surely?

Nope:

* 40b4fd7a3e/llvm/lib/Target/Sparc/SparcTargetMachine.cpp (L226)
* 40b4fd7a3e/llvm/lib/Target/Sparc/SparcTargetMachine.cpp (L104)

So, `sparcel` in LLVM is referring to some sort of fantastical little-endian
SPARC v8 architecture. I've scoured the internet and I can find absolutely no
evidence that such a thing exists or has ever existed. In fact, I can find no
evidence that a little-endian implementation of SPARC v9 ever existed, either.
Or any SPARC version, actually!

The support was added here: https://reviews.llvm.org/D8741

Notably, there is no mention whatsoever of what CPU this might be referring to,
and no justification given for the "but some are little" comment added in the
patch.

My best guess is that this might have been some private exercise in creating a
little-endian version of SPARC that never saw the light of day. Given that SPARC
v8 explicitly doesn't support little-endian operation (let alone little-endian
instruction encoding!), and no CPU is known to be implemented as such, I think
it's very reasonable for us to just remove this support.
2024-07-30 06:30:25 +02:00
Alex Rønne Petersen
d1d95294fd std.Target.Cpu.Arch: Remove the aarch64_32 tag.
This is a misfeature that we inherited from LLVM:

* https://reviews.llvm.org/D61259
* https://reviews.llvm.org/D61939

(`aarch64_32` and `arm64_32` are equivalent.)

I truly have no idea why this triple passed review in LLVM. It is, to date, the
*only* tag in the architecture component that is not, in fact, an architecture.
In reality, it is just an ILP32 ABI for AArch64 (*not* AArch32).

The triples that use `aarch64_32` look like `aarch64_32-apple-watchos`. Yes,
that triple is exactly what you think; it has no ABI component. They really,
seriously did this.

Since only Apple could come up with silliness like this, it should come as no
surprise that no one else uses `aarch64_32`. Later on, a GNU ILP32 ABI for
AArch64 was developed, and support was added to LLVM:

* https://reviews.llvm.org/D94143
* https://reviews.llvm.org/D104931

Here, sanity seems to have prevailed, and a triple using this ABI looks like
`aarch64-linux-gnu_ilp32` as you would expect.

As can be seen from the diffs in this commit, there was plenty of confusion
throughout the Zig codebase about what exactly `aarch64_32` was. So let's just
remove it. In its place, we'll use `aarch64-watchos-ilp32`,
`aarch64-linux-gnuilp32`, and so on. We'll then translate these appropriately
when talking to LLVM. Hence, this commit adds the `ilp32` ABI tag (we already
have `gnuilp32`).
2024-07-28 19:44:52 -07:00
David Rubin
8f84212855
riscv: make multi-threaded enabled compilation the default 2024-07-26 14:53:55 -07:00
David Rubin
846bd40361
riscv: implement @cmpxchg* and remove fixes 2024-07-26 12:43:47 -07:00
David Rubin
8da212c11b
riscv: update tests and fix reuse bug 2024-07-26 04:19:58 -07:00
David Rubin
a1f6a8ef90
riscv: airAsm rewrite
with this rewrite we can call functions inside of
inline assembly, enabling us to use the default start.zig logic

all that's left is to implement lr/sc loops for atomically manipulating
1 and 2 byte values, after which we can use the segfault handler logic.
2024-07-26 04:19:55 -07:00
David Rubin
b533e848a2
riscv: enable passing tests 2024-07-26 04:19:17 -07:00
David Rubin
c00a5ff792
riscv: implement @floatFromInt 2024-07-26 04:19:16 -07:00
David Rubin
1a7d89a84d
riscv: clean up and unify encoding logic 2024-07-26 04:19:13 -07:00
David Rubin
9bc7e8c852
riscv: update tests 2024-07-26 04:05:43 -07:00
David Rubin
1820f44104
riscv: implement sub-byte addition 2024-07-26 04:05:42 -07:00
David Rubin
81ca3a1d59
riscv: fix logic bug in ptr_elem_ptr
I was doing duplicate work with `elemOffset` multiplying by the abi size and then the `ptr_add` `genBinOp` also multiplying.

This led to having writes happening in the wrong place.
2024-07-26 04:05:41 -07:00
David Rubin
cde6956b21
riscv: remove redundant assert in genBinOp 2024-07-26 04:05:41 -07:00
David Rubin
93e9c7a963
riscv: implement @clz 2024-07-26 04:05:39 -07:00
David Rubin
8d30fc45c4
riscv: implement more operators
we can run `std.debug.print` now, with both run-time strings and integers!
2024-07-26 04:05:39 -07:00
David Rubin
9766b68c47
riscv: un-cache the avl and vtype when returning from a function call
the csrs `avl` and `vtype` are considered caller-saved so it could have changed while inside of the function.
the easiest way to handle this is to just set the cached `vtype` and `avl` to null, so that the next time something
needs to set it, it'll emit an instruction instead of relying on a potentially invalid setting.
2024-07-26 04:05:38 -07:00
Julian Vesper
3344ed8b8f aarch64: reenable tests that are no longer regressed
Closes #12012
2024-07-25 20:23:23 +03:00
Pavel Verigo
d71312d104 stage2-wasm: mul_sat 32 bits <=, i64, i128 2024-07-23 17:06:18 +02:00
David Rubin
1fc42ed3e7 riscv: disable failing test 2024-07-22 05:58:59 -04:00
Alex Rønne Petersen
c825b567b2
std.Target: Remove the r600 arch tag.
These are quite old GPUs, and it is unlikely that Zig will ever be able to
target them.

See: https://en.wikipedia.org/wiki/Radeon_HD_2000_series
2024-07-21 22:38:30 +02:00
David Rubin
7591df5172 ip: use getExternFunc in getCoerced
`ip.get` specifically doesn't allow `extern_func` keys to access it.
2024-07-21 01:00:49 -07:00
Andrew Kelley
93c546c8c9
Merge pull request #20692 from pavelverigo/stage2-wasm-overflow-ops
stage2-wasm: overflow ops improvement
2024-07-20 23:57:14 -07:00
Pavel Verigo
a0795f11df disable failing tests on stage2 backends 2024-07-20 14:58:41 +02:00
Pavel Verigo
f5dd6fb71a stage2-wasm: @mulWithOverflow fixes + 128 bit signed 2024-07-20 13:21:46 +02:00
Jacob Young
40bab4df69 behavior: disable test that triggers an llvm assertion
Tracked by #20680
2024-07-19 04:35:11 -04:00
Pavel Verigo
56d535dd24 stage2-wasm: improve @shlWithOverflow for <= 128 bits
Additionally fixed a bug for shr on signed big ints
2024-07-18 18:01:06 +02:00
Pavel Verigo
dc3176d628 stage2-wasm: enhance add/subWithOverflow
Added behavior tests to verify implementation
2024-07-18 17:54:44 +02:00
Pavel Verigo
d1bd9518f9 stage2-wasm: fix big int comparison
Unexpected to be found only now
2024-07-18 17:18:17 +02:00
Jakub Konka
9d9b5a11e8
Merge pull request #20474 from Rexicon226/riscv
more RISC-V backend progress
2024-07-17 08:39:44 +02:00
Wooster
888708ec8a
Sema: support pointer subtraction 2024-07-15 18:18:38 +00:00
David Rubin
5a4fe39fbb
riscv: disable failing tests 2024-07-14 23:04:06 -07:00
David Rubin
5a2c547fc1
riscv: vectors part 3 2024-07-14 23:02:35 -07:00
David Rubin
3e73f37d0a
riscv: implement @fence 2024-07-14 23:02:33 -07:00
David Rubin
7a02878f4e
riscv: truncate airStructFieldVal result 2024-07-14 23:02:33 -07:00
David Rubin
27ceb4ae37
riscv implement @sqrt for f32/f64 2024-07-14 23:02:32 -07:00