Commit graph

119 commits

Author SHA1 Message Date
Jacob Young
feb8f81cd9 cbe: canonicalize types that have the same C type when emitting typedefs 2022-10-25 05:11:29 -04:00
Jacob Young
6a4266d62a cbe: fix infinite recursion on recursive types 2022-10-25 05:11:28 -04:00
Jacob Young
525dcaecba behavior: enable stage2_c tests that are currently passing
Also fix C warnings triggered by these tests.
2022-10-25 05:11:28 -04:00
Cody Tapscott
83e2d3fb37 stage1: Skip new tests that never passed in stage1
This gets the behavior tests passing for stage1 again.
2022-10-13 12:53:20 -07:00
r00ster91
8e2aaf6aed fix(text): hyphenate "runtime" adjectives 2022-10-05 21:33:42 +02:00
Veikka Tuominen
540130650f Sema: pass calculated offset to elemPtrType in elemPtrSlice 2022-09-20 00:50:13 +03:00
Veikka Tuominen
e584558bd8 Sema: do not use coerceCompatiblePtr for alignCast
Closes  #12902
2022-09-19 18:34:52 +03:00
Andrew Kelley
cee82c7ce4 improved ABI alignment/size for >= 128-bit integers
* riscv64: adjust alignment and size of 128-bit integers.
 * take ofmt=c into account for ABI alignment of 128-bit integers and
   structs.
 * Type: make packed struct support intInfo
 * fix f80 alignment for i386-windows-msvc
2022-08-18 20:34:36 -07:00
Andrew Kelley
6e313eb110 stage2: agree with LLVM that @alignOf(u128) is 8
on x86_64 and similar targets.
2022-08-18 17:11:32 -07:00
Veikka Tuominen
baf516218e Sema: don't add union field access safety check for single field unions 2022-07-23 15:40:12 +03:00
Veikka Tuominen
794beafb9c Sema: validate extern struct field types earlier
`validateExternType` does not require the type to be resolved so we can
check it earlier. Only doing it in `resolveTypeFully` lead to worse or
missing compile errors.
2022-07-21 12:21:30 -07:00
Veikka Tuominen
d851b24180 Sema: validate function pointer alignment 2022-07-21 12:21:30 -07:00
joachimschmidt557
960c142060 stage2 ARM: implement basic intCast and error union wrapping 2022-06-25 21:16:51 +02:00
Koakuma
97d35a5147 behaviortest: Skip 'align(N) on functions' on sparc64 for now 2022-06-06 21:17:09 +07:00
Andrew Kelley
288e89b606 Sema: fix compiler crash with comptime arithmetic involving @ptrToInt 2022-06-01 16:45:28 -07:00
Andrew Kelley
b82cccc9e9 Sema: fix alignment of element ptr result type 2022-06-01 15:43:21 -07:00
Andrew Kelley
bd89a73d52 Sema: implement functions generic across callconv() or align() 2022-05-30 14:16:28 -07:00
joachimschmidt557
ddd5b57045 stage2 AArch64: complete genTypedValue 2022-05-27 16:43:11 -04:00
Andrew Kelley
83a2c41cd5 fix alignment behavior test case
As demonstrated by this new test case, stage1's functionality is
incorrect since it does not handle slicing from len..len correctly.

stage2 already has the correct behavior here.
2022-05-26 21:58:19 -07:00
Andrew Kelley
71e2a56e3e mark some more behavior tests as passing 2022-05-25 00:12:56 -07:00
Andrew Kelley
b6798c26ef stage2: fix pointer arithmetic result type
This makes it so the result of doing pointer arithmetic creates a new
pointer type that has adjusted alignment.
2022-05-17 23:50:38 -07:00
Luuk de Gram
e252f92b99 wasm: enable 128bit integer behavior tests 2022-05-18 07:43:33 +02:00
Koakuma
fb0692334e target: Rename sparcv9 -> sparc64
Rename all references of sparcv9 to sparc64, to make Zig align more with
other projects. Also, added new function to convert glibc arch name to Zig
arch name, since it refers to the architecture as sparcv9.

This is based on the suggestion by @kubkon in PR 11847.
(https://github.com/ziglang/zig/pull/11487#pullrequestreview-963761757)
2022-05-13 16:43:59 -04:00
Jakub Konka
6bf67eada4 arm: lock dest register in shl_overflow so that we do not spill it
Nerf two tests - they will require further investigation, but arm
now passes all tests with the safety PR.
2022-05-07 22:53:17 +02:00
Jakub Konka
ac954eb539 regalloc: ensure we only freeze/unfreeze at the outermost scope
This prevents a nasty type of bugs where we accidentally unfreeze
a register that was frozen purposely in the outer scope, risking
accidental realloc of a taken register.

Fix CF flags spilling on aarch64 backend.
2022-05-07 00:57:55 +02:00
Andrew Kelley
0bebb688fb stage2: change max int align from 8 to 16 for more ISAs
These targets now have a similar disagreement with LLVM about the
alignment of 128-bit integers as x86_64:
 * riscv64
 * powerpc64
 * powerpc64le
 * mips64
 * mips64el
 * sparcv9

See #2987
2022-05-04 19:11:02 -07:00
Andrew Kelley
af7e945a7d stage2: fix @sizeOf for structs with comptime fields 2022-05-04 18:45:59 -07:00
Andrew Kelley
f21c11a7f7 stage2: change x86_64 max int alignment from 8 to 16
For x86_64, LLVMABIAlignmentOfType(i128) reports 8. However I think 16
is a better number for two reasons:
1. Better machine code when loading into SIMD register.
2. The C ABI wants 16 for extern structs.
2022-05-04 17:34:17 -07:00
Andrew Kelley
259f784241 stage2: improve @sizeOf and @alignOf integers
Prior to this commit, the logic for ABI size and ABI alignment for
integers was naive and incorrect. This results in wasted hardware as
well as undefined behavior in the LLVM backend when we memset an
incorrect number of bytes to 0xaa due to disagreeing with LLVM about the
ABI size of integers.

This commit introduces a "max int align" value which is different per
Target. This value is used to derive the ABI size and alignment of all
integers.

This commit makes an interesting change from stage1, which treats
128-bit integers as 16-bytes aligned for x86_64-linux. stage1 is
incorrect. The maximum integer alignment on this system is only 8 bytes.
This change breaks the behavior test called "128-bit cmpxchg" because on
that target, 128-bit cmpxchg does require a 16-bytes aligned pointer to
a 128 bit integer. However, this alignment property does not belong on
*all* 128 bit integers - only on the pointer type in the `@cmpxchg`
builtin function prototype. The user can then use an alignment override
annotation on a 128-bit integer variable or struct field to obtain such
a pointer.
2022-05-04 17:34:16 -07:00
Cody Tapscott
19331b323d stage2: Correctly align decls for comptime allocs
This updates WipAnonDecl to require an alignment provided by the caller,
which is needed for explicitly aligned comptime allocs.
2022-03-19 19:41:23 -04:00
joachimschmidt557
3ecba7d7a2
stage2 ARM: implement slice_elem_ptr, ptr_elem_ptr 2022-03-18 12:12:14 +01:00
joachimschmidt557
b74cd902c6
stage2 AArch64: enable mul for ints with <= 64 bits 2022-03-13 11:32:08 +01:00
Andrew Kelley
0bc9635490 stage2: add debug info for locals in the LLVM backend
Adds 2 new AIR instructions:
 * dbg_var_ptr
 * dbg_var_val

Sema no longer emits dbg_stmt AIR instructions when strip=true.

LLVM backend: fixed lowerPtrToVoid when calling ptrAlignment on
the element type is problematic.

LLVM backend: fixed alloca instructions improperly getting debug
location annotated, causing chaotic debug info behavior.

zig_llvm.cpp: fixed incorrect bindings for a function that should use
unsigned integers for line and column.

A bunch of C test cases regressed because the new dbg_var AIR
instructions caused their operands to be alive, exposing latent bugs.
Mostly it's just a problem that the C backend lowers mutable
and const slices to the same C type, so we need to represent that in the
C backend instead of printing two duplicate typedefs.
2022-03-13 03:41:31 -04:00
Andrew Kelley
f736cde397 Sema: implement pointer to tuple to pointer to array coercion
This involved an LLVM backend fix for the aggregate_init instruction.
2022-03-09 18:49:37 -07:00
Andrew Kelley
f32a77b30d Sema: implement pointer-to-tuple coercion to slice and struct 2022-03-09 17:33:01 -07:00
Luuk de Gram
90f08a69aa wasm: Enable passing behavior tests
This also adds some float-related instructions to MIR/Emit
2022-03-09 13:53:20 -07:00
joachimschmidt557
3ea603c82a stage2 ARM: implement ptr_add, ptr_sub for all element sizes
Also reduces slice_elem_val to ptr_add, simplifying the implementation
2022-03-08 10:54:08 +01:00
Luuk de Gram
70fc6e3776
wasm: call into generateSymbol when lowering
This also unifies the wasm backend to use `generateSymbol` when lowering a constant
that cannot be lowered to an immediate value.
As both decls and constants are now refactored, the old `genTypedValue` is removed.
2022-03-06 19:38:53 +01:00
joachimschmidt557
a06e9eca45
stage2 AArch64: add more slice support
* airSlice
* airArrayToSlice
* and initial support for airSlicePtr and co
2022-03-05 11:31:51 +01:00
joachimschmidt557
d486a7b811 stage2 ARM: generate less no-op branches
The checks detecting such no-op branches (essentially instructions
that branch to the instruction immediately following the branch) were
tightened to catch more of these occurrences.
2022-03-04 23:28:14 +01:00
Jakub Konka
ec54ceee6d
Merge pull request #11016 from ziglang/x64-more-codegen 2022-03-01 09:14:23 +01:00
Andrew Kelley
157f66ec07 Sema: fix pointer type hash and equality functions
Several issues with pointer types are fixed:

Prior to this commit, Zig would not canonicalize a pointer type with
an explicit alignment to alignment=0 if it matched the pointee ABI
alignment. In order to fix this, `Type.ptr` now takes a Target
parameter. I also moved the host_size canonicalization to `Type.ptr`
since target is now available. Similarly, is_allowzero in the case of
C pointers is now treated as a canonicalization done by the function
rather than a precondition.

in-memory coercion for pointers now properly checks ABI alignment
of pointee types instead of incorrectly treating the 0 value as an
alignment.

Type equality is completely reworked based on the tag() rather than the
zigTypeTag(). It's still semantically based on zigTypeTag() but that
knowledge is implied rather than dictating the control flow of the
logic. Importantly, this fixes cases for opaques, structs, tuples,
enums, and unions, where type equality was incorrectly returning based
on whether the tag() values were equal.

Additionally, pointer type equality now takes into account alignment.
Because we canonicalize non-zero alignment which equals pointee type ABI
alignment to alignment=0, this now can be a simple integer comparison.

Type hashing is implemented for pointers and floats. Array types now
additionally hash their sentinels.

This regressed some behavior tests that were passing but only because
of bugs regarding type equality.

The C backend has a noticeable problem with lowering differently-aligned
pointers (particularly slices) as the same type, causing C compilation
errors due to duplicate declarations.
2022-02-28 19:22:16 -07:00
Jakub Konka
cfbc3537ef x64: pass more behavior tests 2022-02-28 23:20:05 +01:00
joachimschmidt557
91fbcf7093
stage2 ARM: enable more behavior tests 2022-02-27 21:38:56 +01:00
Jakub Konka
1b8ed7842c macho: redo selection of segment/section for decls and consts
* fix alignment issues for consts with natural ABI alignment not
  matching that of the `ldr` instruction in `aarch64` - solved by
  preceeding the `ldr` with an additional `add` instruction to form
  the full address before dereferencing the pointer.
* redo selection of segment/section for decls and consts based on
  combined type and value
2022-02-25 21:59:19 +01:00
joachimschmidt557
f91fe9afb9
stage2 AArch64: more support for MCValue.got_load and direct_load 2022-02-23 21:58:13 +01:00
Jakub Konka
25e4b16e25 Port more behavior tests 2022-02-22 21:57:42 +01:00
joachimschmidt557
25f73224f7
stage2 AArch64: pass a few more behavior tests 2022-02-21 23:05:16 +01:00
joachimschmidt557
2ba1ef165a
stage2 AArch64: implement genSetReg for ptr_stack_offset 2022-02-21 22:54:14 +01:00
Jakub Konka
3193cc1c1e x64: fix ptr_add and ptr_sub
Add standalone implementation of operand reuse for ptr related
arithmetic operations of add and sub.
2022-02-17 15:07:42 +01:00