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8 commits

Author SHA1 Message Date
Frank Denis
6c2e0c2046 Year++ 2020-12-31 15:45:24 -08:00
LemonBoy
518168edb2 compiler-rt: Avoid exposing atomic builtins when not supported 
Let's a void any kind of compilation/LLVM errors for niche targets such
as AVR/MSP430 or ARM v6m. By not exporting any atomic builtin anymore
the user is free to provide their own implementation (that disable the
IRQs) or to provide the --single-threaded switch and forget about this.
 2020-12-09 16:33:53 +01:00
Andrew Kelley
4a69b11e74 add license header to all std lib files 
add SPDX license identifier
copyright ownership is zig contributors
 2020-08-20 16:07:04 -04:00
LemonBoy
a0b73c9f02 compiler-rt: Separate max size allowed for load/store and CAS 
The v6m ISA has no way to express a CAS loop natively without turning
off the interrupts or using the kernel cmpxchg harness.

On such a platform the user has to provide a few __sync_* builtins to
satisfy the linker.
 2020-04-06 12:52:53 -04:00
daurnimator
e9e43ed0d3
compiler_rt/atomics: be consistent with const value 2020-04-05 14:08:25 +10:00
daurnimator
f947444362
Tidy up compiler_rt/atomics 2020-04-05 14:06:12 +10:00
Andrew Kelley
e03cbb117e
compiler-rt: don't forget to export these functions 2020-04-03 16:07:32 -04:00
LemonBoy
ed69821f5b
compiler-rt: Add the __atomic family of builtins 
The implementation was checked against a few files using std::atomic and
compiled using zig c++.

Closes #4887
 2020-04-03 16:04:44 -04:00