Commit graph

274 commits

Author SHA1 Message Date
Jay Petacat
464fcac802
Sema: Allow small integer types to coerce to floats
If the float can store all possible values of the integer without
rounding, coercion is allowed. The integer's precision must be less than
or equal to the float's significand precision.

Closes #18614
2025-11-29 13:18:19 -07:00
Ali Cheraghi
dec1163fbb
all: replace all @Type usages
Co-authored-by: Matthew Lugg <mlugg@mlugg.co.uk>
2025-11-22 22:42:38 +00:00
Jacob Young
e1f3fc6ce2 Coff2: create a new linker from scratch 2025-10-02 17:44:52 -04:00
Jacob Young
e313b387a0 x86_64: delete usages of avx2 vpack?s??
This instruction actually has fairly useless semantics, and even the
cases that were semantically correct could save 1 cycle of latency by
using a different sequnce involving the avx version instead.

Closes #25174
2025-09-10 22:40:26 -04:00
Andrew Kelley
5701617b27 wasm backend: disable failing behavior tests 2025-09-07 20:11:37 -07:00
mlugg
ba6abd71c2
llvm: unions which are equivalent to enums are not by-ref
The LLVM backend lowers unions where all fields are zero-bit as
equivalent to their backing enum, and expects them to have the same
by-ref-ness in at least one place in the backend, probably more.

Resolves: #23577
2025-08-13 11:36:16 +01:00
Ali Cheraghi
64563e2fff
test: skip tests that were not meant to pass for spirv 2025-08-09 13:27:45 +03:30
Jacob Young
869ef00602 aarch64: more progress
- factor out `loadReg`
 - support all general system control registers in inline asm
 - fix asserts after iterating field offsets
 - fix typo in `slice_elem_val`
 - fix translation of argument locations
2025-07-25 14:20:23 -04:00
Jacob Young
5060ab99c9 aarch64: add new from scratch self-hosted backend 2025-07-22 19:43:47 -07:00
Bingwu Zhang
e8d6ecb9ce
riscv64: skip failing tests 2025-06-28 06:47:09 +08:00
Jacob Young
1f98c98fff x86_64: increase passing test coverage on windows
Now that codegen has no references to linker state this is much easier.

Closes #24153
2025-06-19 18:41:12 -04:00
Matthew Lugg
561fdd0ed3
Merge pull request #24188 from mlugg/intfromfloat-safety
Absorb std.math.big.rational logic into std.math.big.int; fix `@intFromFloat` safety check
2025-06-17 11:02:03 +01:00
Ali Cheraghi
872f68c9cb
rename spirv backend name
`stage2_spirv64` -> `stage2_spirv`
2025-06-16 13:22:19 +03:30
mlugg
6ffa285fc3 compiler: fix @intFromFloat safety check
This safety check was completely broken; it triggered unchecked illegal
behavior *in order to implement the safety check*. You definitely can't
do that! Instead, we must explicitly check the boundaries. This is a
tiny bit fiddly, because we need to make sure we do floating-point
rounding in the correct direction, and also handle the fact that the
operation truncates so the boundary works differently for min vs max.

Instead of implementing this safety check in Sema, there are now
dedicated AIR instructions for safety-checked intfromfloat (two
instructions; which one is used depends on the float mode). Currently,
no backend directly implements them; instead, a `Legalize.Feature` is
added which expands the safety check, and this feature is enabled for
all backends we currently test, including the LLVM backend.

The `u0` case is still handled in Sema, because Sema needs to check for
that anyway due to the comptime-known result. The old safety check here
was also completely broken and has therefore been rewritten. In that
case, we just check for 'abs(input) < 1.0'.

I've added a bunch of test coverage for the boundary cases of
`@intFromFloat`, both for successes (in `test/behavior/cast.zig`) and
failures (in `test/cases/safety/`).

Resolves: #24161
2025-06-15 14:15:18 -04:00
Jacob Young
80170d017b Legalize: handle packed semantics
Closes #22915
2025-06-03 15:04:43 -04:00
Jacob Young
b483defc5a Legalize: implement scalarization of binary operations 2025-05-31 18:54:28 -04:00
Jacob Young
1f6f8b0ffe x86_64: implement integer @reduce(.Add) 2025-05-28 15:10:22 -04:00
Andrew Kelley
65bd8d52c8
Merge pull request #23061 from pavelverigo/stage2-wasm-misc
stage2-wasm: multiple fixes
2025-04-11 15:56:35 -04:00
Alex Rønne Petersen
382aa48f04
test: Disable a bunch of vector behavior tests for hexagon.
Most of the failures are:

* https://github.com/llvm/llvm-project/issues/118879
* https://github.com/llvm/llvm-project/issues/134659

But some are also miscompilations leading to wrong results. I'm not going to
investigate the latter further until all the backend crashes have been resolved.
2025-04-11 02:28:35 +02:00
Pavel Verigo
a429d04ba9 stage2-wasm: enable already working tests 2025-03-24 14:59:58 +01:00
Ali Cheraghi
aec0f9b3e7
test: skip failing tests with spirv-vulkan 2025-02-24 19:39:42 +01:00
Jacob Young
13ca87e204 x86_64: implement conversions between float and int vectors 2025-02-12 10:11:54 -05:00
mlugg
fbe0ae4fd4
Sema: fix PTR of slice of sentinel-terminated array
Resolves: #20901
2025-02-05 19:53:12 +00:00
Jacob Young
c3d33440f0 x86_64: pass more behavior tests 2025-01-16 20:47:30 -05:00
Jacob Young
e5d5a8bc4e x86_64: implement switch jump tables 2025-01-16 20:42:08 -05:00
mlugg
d00e05f186
all: update to std.builtin.Type.Pointer.Size field renames
This was done by regex substitution with `sed`. I then manually went
over the entire diff and fixed any incorrect changes.

This diff also changes a lot of `callconv(.C)` to `callconv(.c)`, since
my regex happened to also trigger here. I opted to leave these changes
in, since they *are* a correct migration, even if they're not the one I
was trying to do!
2025-01-16 12:46:29 +00:00
xdBronch
5f3a70ed5f Fix peer type resolution with allowzero pointers 2024-11-20 02:09:50 +02:00
Alex Rønne Petersen
c9e67e71c1
std.Target: Replace isARM() with isArmOrThumb() and rename it to isArm().
The old isARM() function was a portability trap. With the name it had, it seemed
like the obviously correct function to use, but it didn't include Thumb. In the
vast majority of cases where someone wants to ask "is the target Arm?", Thumb
*should* be included.

There are exactly 3 cases in the codebase where we do actually need to exclude
Thumb, although one of those is in Aro and mirrors a check in Clang that is
itself likely a bug. These rare cases can just add an extra isThumb() check.
2024-11-03 09:29:30 +01:00
mlugg
d11bbde5f9
compiler: remove anonymous struct types, unify all tuples
This commit reworks how anonymous struct literals and tuples work.

Previously, an untyped anonymous struct literal
(e.g. `const x = .{ .a = 123 }`) was given an "anonymous struct type",
which is a special kind of struct which coerces using structural
equivalence. This mechanism was a holdover from before we used
RLS / result types as the primary mechanism of type inference. This
commit changes the language so that the type assigned here is a "normal"
struct type. It uses a form of equivalence based on the AST node and the
type's structure, much like a reified (`@Type`) type.

Additionally, tuples have been simplified. The distinction between
"simple" and "complex" tuple types is eliminated. All tuples, even those
explicitly declared using `struct { ... }` syntax, use structural
equivalence, and do not undergo staged type resolution. Tuples are very
restricted: they cannot have non-`auto` layouts, cannot have aligned
fields, and cannot have default values with the exception of `comptime`
fields. Tuples currently do not have optimized layout, but this can be
changed in the future.

This change simplifies the language, and fixes some problematic
coercions through pointers which led to unintuitive behavior.

Resolves: #16865
2024-10-31 20:42:53 +00:00
kcbanner
2d888a8e63 tests: re-enable tests that now pass on aarch64-windows 2024-10-22 11:39:29 +02:00
David Rubin
bc161430b0 riscv: implement optional_payload_ptr_set 2024-09-12 20:29:10 -04:00
mlugg
0fe3fd01dd
std: update std.builtin.Type fields to follow naming conventions
The compiler actually doesn't need any functional changes for this: Sema
does reification based on the tag indices of `std.builtin.Type` already!
So, no zig1.wasm update is necessary.

This change is necessary to disallow name clashes between fields and
decls on a type, which is a prerequisite of #9938.
2024-08-28 08:39:59 +01:00
David Rubin
8da212c11b
riscv: update tests and fix reuse bug 2024-07-26 04:19:58 -07:00
David Rubin
a1f6a8ef90
riscv: airAsm rewrite
with this rewrite we can call functions inside of
inline assembly, enabling us to use the default start.zig logic

all that's left is to implement lr/sc loops for atomically manipulating
1 and 2 byte values, after which we can use the segfault handler logic.
2024-07-26 04:19:55 -07:00
David Rubin
b533e848a2
riscv: enable passing tests 2024-07-26 04:19:17 -07:00
David Rubin
c00a5ff792
riscv: implement @floatFromInt 2024-07-26 04:19:16 -07:00
David Rubin
cde6956b21
riscv: remove redundant assert in genBinOp 2024-07-26 04:05:41 -07:00
David Rubin
8d30fc45c4
riscv: implement more operators
we can run `std.debug.print` now, with both run-time strings and integers!
2024-07-26 04:05:39 -07:00
David Rubin
e60c581147
test: disable-enable riscv tests 2024-06-13 04:42:26 -07:00
David Rubin
3967e00047
riscv: disable failing test 2024-06-13 02:24:39 -07:00
David Rubin
4fd8900337
riscv: rewrite "binOp"
Reorganize how the binOp and genBinOp functions work.

I've spent quite a while here reading exactly through the spec and so many
tests are enabled because of several critical issues the old design had.

There are some regressions that will take a long time to figure out individually
so I will ignore them for now, and pray they get fixed by themselves. When
we're closer to 100% passing is when I will start diving into them one-by-one.
2024-06-13 02:24:39 -07:00
David Rubin
a270c6f8c8
riscv: implement optional logic 2024-06-13 02:22:33 -07:00
David Rubin
d69c48370a
riscv: integer + float @abs 2024-06-13 02:22:06 -07:00
David Rubin
c10d1c6a75
riscv: implement more arithmetic instructions 2024-06-13 02:22:05 -07:00
David Rubin
083b7b483e
riscv: zero registers when using register-wide operations
what was happening is that instructions like `lb` were only affecting the lower bytes of the register and leaving the top dirty. this would lead to situtations were `cmp_eq` for example was using `xor`, which was failing because of the left-over stuff in the top of the register.

with this commit, we now zero out or truncate depending on the context, to ensure instructions like xor will provide proper results.
2024-06-13 02:22:04 -07:00
David Rubin
7ed2f2156f
riscv: fix register clobber in certain edge cases 2024-06-13 02:21:38 -07:00
David Rubin
05de6c279b
riscv: std.fmt.format running
- implements `airSlice`, `airBitAnd`, `airBitOr`, `airShr`.

- got a basic design going for the `airErrorName` but for some reason it simply returns
empty bytes. will investigate further.

- only generating `.got.zig` entries when not compiling an object or shared library

- reduced the total amount of ops a mnemonic can have to 3, simplifying the logic
2024-06-13 02:20:47 -07:00
David Rubin
c457f35da5
riscv: arbitrary sized arrays 2024-06-13 02:19:40 -07:00
David Rubin
004d0c8978
riscv: switch progress + by-ref return progress 2024-06-13 02:19:38 -07:00
Robin Voetter
b9d738a5cf
spirv: disable tests that fail on pocl
Besides the Intel OpenCL CPU runtime, we can now run the
behavior tests using the Portable Computing Language. This
implementation is open-source, so it will be easier for us
to patch in updated versions of spirv-llvm-translator that
have bug fixes etc.
2024-06-10 20:32:34 +02:00