Commit graph

29474 commits

Author SHA1 Message Date
r00ster91
9ae43567a3 Sema: improve error set/union discard/ignore errors
Previously the error had a note suggesting to use `try`, `catch`, or
`if`, even for error sets where none of those work.
Instead, in case of an error set the way you can handle the error
depends very much on the specific case. For example you might be in a
`catch` where you are discarding or ignoring the error set capture
value, in which case one way to handle the error might be to `return`
the error.
So, in that case, we do not attach that error note.

Additionally, this makes the error tell you what kind of an error it is:
is it an error set or an error union? This distinction is very relevant
in how to handle the error.
2024-05-14 01:13:49 +09:00
r00ster91
8579904ddd Sema: add error note for !?Type types when optional type is expected 2024-05-14 01:13:49 +09:00
r00ster91
31689d0dd9 Sema: remove periods from the few error messages that have them
For consistency.
2024-05-14 01:13:49 +09:00
r00ster91
60830e36e3 Sema error: talk about discarding instead of suppressing
Maybe I'm just being pedantic here (most likely) but I don't like how we're
just telling the user here how to "suppress this error" by "assigning the value to '_'".
I think it's better if we use the word "discard" here which I think is
the official terminology and also tells the user what it actually means
to "assign the value to '_'".

Also, using the value would also be a way to "suppress the error".
It is just one of the two options: discard or use.
2024-05-14 01:13:48 +09:00
Jakub Konka
2d537da6bd Step.CheckObject: support dumping raw section contents for MachO 2024-05-13 09:14:35 +02:00
Jakub Konka
5d619da2de Step.CheckObject: put MachO object parsing logic in ObjectContext wrapper 2024-05-13 08:56:15 +02:00
Jakub Konka
6f117dbca4 test/standalone: fix iOS smoke test 2024-05-13 08:55:27 +02:00
Andrew Kelley
e2ec54bb38
Merge pull request #19926 from squeek502/windows-sdk-cachepath-registry
WindowsSdk: Fix finding the _Instances directory when it's not in the default location
2024-05-12 09:39:13 -04:00
Ronald Chen
c77afca957 [std] Fixed bug missing optional for lpName param on CreateEventExW. fixes #19946
https://learn.microsoft.com/en-us/windows/win32/api/synchapi/nf-synchapi-createeventexw
2024-05-12 07:45:40 +02:00
Georgijs
084c2cd90f
windows: use permissive file share flags everywhere (#19505)
* use permissive file share flags everywhere

* remove file_share_delete from createnamedpipefile
2024-05-11 23:34:40 +02:00
Christofer Nolander
8f6b1f2c38
zig fetch: resolve branch/tag names to commit SHA (#19941)
* Revert "Revert "Merge pull request #19349 from nolanderc/save-commit""

This reverts commit 6ca4ed5948.

* update to new URI changes, rework `--save` type

* initialize `latest_commit` to null everywhere
2024-05-11 14:19:35 -07:00
Jakub Konka
86d8688c7f
Merge pull request #19431 from Rexicon226/revive-riscv
revive STAGE2 RISCV64 backend
2024-05-11 21:35:18 +02:00
Andrew Kelley
661a9be66b std.Build.Step.Run: add missing call to writeManifest
fixes #19938
2024-05-11 06:28:45 -07:00
Jordan Yates
17c1fa64c3 Bump required LLVM version in README.md 2024-05-11 04:13:17 -07:00
David Rubin
75372f12ef riscv: update behaviour tests again 2024-05-11 02:17:24 -07:00
David Rubin
1dfdc21c31 riscv: intcast got_addr
the recent merge strings PR made `got_addr` `i64` and now requires an `@intCast`.
2024-05-11 02:17:24 -07:00
David Rubin
ffb63a05a3 riscv: finally fix bug + airAggregateInit
i just hadn't realized that I placed the `riscv_start` branch in the non-simplified
starts
2024-05-11 02:17:24 -07:00
David Rubin
2fd83d8c0a riscv: by-value structs + @min 2024-05-11 02:17:24 -07:00
David Rubin
a30af172e8 riscv: math progress 2024-05-11 02:17:24 -07:00
David Rubin
a615fbc1f8 riscv: mutable globals 2024-05-11 02:17:24 -07:00
David Rubin
d9e0cafe64 riscv: add stage2_riscv to test matrix and bypass failing tests 2024-05-11 02:17:24 -07:00
David Rubin
e622485df8 riscv: actually working test runner 2024-05-11 02:17:11 -07:00
David Rubin
d19b77d63f riscv: back to hello world panics 2024-05-11 02:17:11 -07:00
David Rubin
cc204e2365 riscv: spill args immediately to prevent clobbers 2024-05-11 02:17:11 -07:00
David Rubin
6740c1f084 riscv: big rewrite to use latest liveness
this one is even harder to document then the last large overhaul.

TLDR;
- split apart Emit.zig into an Emit.zig and a Lower.zig
- created seperate files for the encoding, and now adding a new instruction
is as simple as just adding it to a couple of switch statements and providing the encoding.
- relocs are handled in a more sane maner, and we have a clear defining boundary between
lea_symbol and load_symbol now.
- a lot of different abstractions for things like the stack, memory, registers, and others.
- we're using x86_64's FrameIndex now, which simplifies a lot of the tougher design process.
- a lot more that I don't have the energy to document. at this point, just read the commit itself :p
2024-05-11 02:17:11 -07:00
David Rubin
9d0bb6371d riscv: almost @errorName but not loading correctly 2024-05-11 02:17:11 -07:00
David Rubin
8ac239ebce riscv: add enough components to get a test runner working 2024-05-11 02:17:11 -07:00
David Rubin
c0629c3539 riscv: implement airNot 2024-05-11 02:17:11 -07:00
David Rubin
4ce85f930e riscv: implement structFieldPtr and retLoad 2024-05-11 02:17:11 -07:00
David Rubin
ece70e08a0 riscv: pass optionals by register_pair for resolveCallingConventionValues 2024-05-11 02:17:11 -07:00
David Rubin
26ce82d98e riscv: correctly derefence load_symbol in genSetReg 2024-05-11 02:17:11 -07:00
David Rubin
3bf008a3d0 riscv: implement slices 2024-05-11 02:17:11 -07:00
David Rubin
350ad90cee riscv: totally rewrite how we do loads and stores
this commit is a little too large to document fully, however the main gist of it this

- finish the `genInlineMemcpy` implement
- rename `setValue` to `genCopy` as I agree with jacob that it's a better name
- add in `genVarDbgInfo` for a better gdb experience
- follow the x86_64's method for genCall, as the procedure is very similar for us
- add `airSliceLen` as it's trivial
- change up the `airAddWithOverflow implementation a bit
- make sure to not spill of the elem_ty is 0 size
- correctly follow the RISC-V calling convention and spill the used calle saved registers in the prologue
and restore them in the epilogue
- add `address`, `deref`, and `offset` helper functions for MCValue. I must say I love these,
they make the code very readable and super verbose :)
- fix a `register_manager.zig` issue where when using the last register in the set, the value would overflow at comptime.
was happening because we were adding to `max_id` before subtracting from it.
2024-05-11 02:17:11 -07:00
David Rubin
cbf62bd6dc riscv: switch default_panic to use the message 2024-05-11 02:17:11 -07:00
David Rubin
3c0015c828 riscv: implement a basic @intCast
the truncation panic logic is generated in Sema, so I don't need to roll anything
of my own. I add all of the boilerplate for that detecting the truncation and it works
in basic test cases!
2024-05-11 02:17:11 -07:00
David Rubin
685f828218 riscv: add a custom panic function
this provides a much better indication of when we are having a controlled panic with an error message
or when we are actually segfaulting, as before the `trap` as causing a segfault.
2024-05-11 02:17:11 -07:00
David Rubin
b28c966e33 riscv: fix overflow checks in addition. 2024-05-11 02:17:11 -07:00
David Rubin
e70584e2f8 riscv: change load_symbol psuedo instruction size to 8 2024-05-11 02:17:11 -07:00
David Rubin
06089fc89a riscv: fix how we calculate stack offsets. allows for pass by reference arguments. 2024-05-11 02:17:11 -07:00
David Rubin
c96989aa4b riscv: correctly index struct field access
when the struct is in stack memory, we access it using a byte-offset,
because that's how the stack works. on the other hand when the struct
is in a register, we are working with bits and the field offset should
be a bit offset.
2024-05-11 02:17:11 -07:00
David Rubin
09b7aabe09 riscv: add allocReg helper, and clean up some comparing logic
- Added the basic framework for panicing with an overflow in `airAddWithOverflow`, but there is no check done yet.
- added the `cmp_lt`, `cmp_gte`, and `cmp_imm_eq` MIR instructions, and their respective functionality.
2024-05-11 02:17:11 -07:00
David Rubin
08452b1add riscv: correct the order of the return epilogue 2024-05-11 02:17:11 -07:00
David Rubin
f1fe5c937e riscv: pointer work
lots of thinking later, ive begun to grasp my head around how the pointers should work. this commit allows basic pointer loading and storing to happen.
2024-05-11 02:17:11 -07:00
David Rubin
9229321400 riscv: change up how we do args
- before we were storing each arg in it's own function arg register. with this commit now we store the args in the fa register before calling as per the RISC-V calling convention, however as soon as we enter the callee, aka in airArg, we spill the argument to the stack. this allows us to spend less effort worrying about whether we're going to clobber the function arguments when another function is called inside of the callee.

- we were actually clobbering the fa regs inside of resolveCallingConvetion, because of the null argument to allocReg. now each lock is stored in an array which is then iterated over and unlocked, which actually aids in the first point of this commit.
2024-05-11 02:17:11 -07:00
David Rubin
5e010b6dea riscv: reorganize binOp and implement cmp_imm_gte MIR
this was an annoying one to do, as there is no (to my knowledge) myriad sequence
that will allow us to do `gte` compares with an immediate without allocating a register.
RISC-V provides a single instruction to do compares, that being `lt`, and so you need to
use more than one for other variants, but in this case, i believe you need to allocate a register.
2024-05-11 02:17:11 -07:00
David Rubin
63bbf66553 riscv: remove an allocation from dwarf.zig 2024-05-11 02:17:11 -07:00
David Rubin
190e7d0239 riscv: update builtin names 2024-05-11 02:17:11 -07:00
David Rubin
2cbd8e1deb riscv: progress toward arrays
- implement `airArrayElemVal` for arrays on the stack. This is really easy
as we can just move the offset by the bytes into the array. This only works
when the index access is comptime-known though, this won't work for runtime access.
2024-05-11 02:17:11 -07:00
David Rubin
9b2a4582c9 riscv: implement 64 bit immediate into register loading
LLVM has a better myriad sequence for this, where they don't allocate
a temporary register, but for now this will do.
2024-05-11 02:17:11 -07:00
David Rubin
f67fa73fe8 riscv: 16 bit @byteSwap 2024-05-11 02:17:11 -07:00