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59 lines
No EOL
2 KiB
C
Vendored
59 lines
No EOL
2 KiB
C
Vendored
/*===---------------- movrsintrin.h - MOVRS intrinsics ----------------------===
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*
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* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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* See https://llvm.org/LICENSE.txt for license information.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*
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*===----------------------------------------------------------------------===*/
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#ifndef __IMMINTRIN_H
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#error "Never use <movrsintrin.h> directly; include <immintrin.h> instead."
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#endif // __IMMINTRIN_H
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#ifndef __MOVRSINTRIN_H
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#define __MOVRSINTRIN_H
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#define __DEFAULT_FN_ATTRS \
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__attribute__((__always_inline__, __nodebug__, __target__("movrs")))
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#ifdef __x86_64__
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static __inline__ char __DEFAULT_FN_ATTRS _movrs_i8(const void *__A) {
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return (char)__builtin_ia32_movrsqi((const void *)__A);
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}
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static __inline__ short __DEFAULT_FN_ATTRS _movrs_i16(const void *__A) {
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return (short)__builtin_ia32_movrshi((const void *)__A);
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}
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static __inline__ int __DEFAULT_FN_ATTRS _movrs_i32(const void *__A) {
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return (int)__builtin_ia32_movrssi((const void *)__A);
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}
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static __inline__ long long __DEFAULT_FN_ATTRS _movrs_i64(const void *__A) {
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return (long long)__builtin_ia32_movrsdi((const void *)__A);
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}
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#endif // __x86_64__
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// Loads a memory sequence containing the specified memory address into
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/// the L3 data cache. Data will be shared (read/written) to by requesting
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/// core and other cores.
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///
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/// Note that the effect of this intrinsic is dependent on the processor
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/// implementation.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the \c PREFETCHRS instruction.
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///
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/// \param __P
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/// A pointer specifying the memory address to be prefetched.
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static __inline__ void __DEFAULT_FN_ATTRS
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_m_prefetchrs(volatile const void *__P) {
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#pragma clang diagnostic push
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#pragma clang diagnostic ignored "-Wcast-qual"
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__builtin_ia32_prefetchrs((const void *)__P);
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#pragma clang diagnostic pop
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}
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#undef __DEFAULT_FN_ATTRS
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#endif // __MOVRSINTRIN_H
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