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c26bace606
Upstream commit dddccbc3ef50ac52bf00723fd2f68d98140aab80 * adds ucrtbase.def.in * mingwex: replace mingw crt files with ucrt files * adds missing mingw-w64 ucrt files The rules that govern which set of files are included or excluded is contained in the logic for tools/update_mingw.zig
49 lines
1.3 KiB
Modula-2
Vendored
49 lines
1.3 KiB
Modula-2
Vendored
LIBRARY scsiport.sys
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EXPORTS
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DllInitialize@4
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ScsiDebugPrint
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ScsiPortCompleteRequest@20
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;ScsiPortConvertPhysicalAddressToUlong
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ScsiPortConvertUlongToPhysicalAddress@4
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ScsiPortFlushDma@4
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ScsiPortFreeDeviceBase@8
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ScsiPortGetBusData@24
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ScsiPortGetDeviceBase@28
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ScsiPortGetLogicalUnit@16
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ScsiPortGetPhysicalAddress@16
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ScsiPortGetSrb@20
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ScsiPortGetUncachedExtension@12
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ScsiPortGetVirtualAddress@12
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ScsiPortInitialize@16
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ScsiPortIoMapTransfer@16
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ScsiPortLogError@28
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ScsiPortMoveMemory@12
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ScsiPortNotification
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ScsiPortQuerySystemTime@4
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ScsiPortReadPortBufferUchar@12
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ScsiPortReadPortBufferUlong@12
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ScsiPortReadPortBufferUshort@12
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ScsiPortReadPortUchar@4
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ScsiPortReadPortUlong@4
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ScsiPortReadPortUshort@4
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ScsiPortReadRegisterBufferUchar@12
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ScsiPortReadRegisterBufferUlong@12
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ScsiPortReadRegisterBufferUshort@12
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ScsiPortReadRegisterUchar@4
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ScsiPortReadRegisterUlong@4
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ScsiPortReadRegisterUshort@4
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ScsiPortSetBusDataByOffset@28
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ScsiPortStallExecution@4
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ScsiPortValidateRange@28
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ScsiPortWritePortBufferUchar@12
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ScsiPortWritePortBufferUlong@12
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ScsiPortWritePortBufferUshort@12
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ScsiPortWritePortUchar@8
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ScsiPortWritePortUlong@8
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ScsiPortWritePortUshort@8
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ScsiPortWriteRegisterBufferUchar@12
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ScsiPortWriteRegisterBufferUlong@12
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ScsiPortWriteRegisterBufferUshort@12
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ScsiPortWriteRegisterUchar@8
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ScsiPortWriteRegisterUlong@8
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ScsiPortWriteRegisterUshort@8
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