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sys/param.h was manually adjusted to not define __NetBSD_Version__ since it will be defined by the compiler.
460 lines
No EOL
12 KiB
C
Vendored
460 lines
No EOL
12 KiB
C
Vendored
/* $NetBSD: pte.h,v 1.27 2020/08/22 15:34:51 skrll Exp $ */
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/*-
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* Copyright (c) 1997 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright 1996 The Board of Trustees of The Leland Stanford
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* Junior University. All Rights Reserved.
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*
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* Permission to use, copy, modify, and distribute this
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* software and its documentation for any purpose and without
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* fee is hereby granted, provided that the above copyright
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* notice appear in all copies. Stanford University
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* makes no representations about the suitability of this
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* software for any purpose. It is provided "as is" without
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* express or implied warranty.
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*/
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#ifndef __MIPS_PTE_H__
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#define __MIPS_PTE_H__
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#include <mips/mips1_pte.h>
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#include <mips/mips3_pte.h>
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#define PG_ASID 0x000000ff /* Address space ID */
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#ifndef _LOCORE
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#ifndef __BSD_PTENTRY_T__
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#define __BSD_PTENTRY_T__
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typedef uint32_t pt_entry_t;
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#define PRIxPTE PRIx32
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#endif
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/*
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* Macros/inline functions to hide PTE format differences.
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*/
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#define mips_pg_nv_bit() (MIPS1_PG_NV) /* same on mips1 and mips3 */
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bool pmap_is_page_ro_p(struct pmap *pmap, vaddr_t, uint32_t);
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/* MIPS1-only */
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#if defined(MIPS1) && !defined(MIPS3_PLUS)
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#define mips_pg_v(entry) ((entry) & MIPS1_PG_V)
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#define mips_pg_wired(entry) ((entry) & MIPS1_PG_WIRED)
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#define mips_pg_m_bit() (MIPS1_PG_D)
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#define mips_pg_rw_bit() (MIPS1_PG_RW) /* no RW bits for mips1 */
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#define mips_pg_ro_bit() (MIPS1_PG_RO)
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#define mips_pg_ropage_bit() (MIPS1_PG_RO) /* XXX not MIPS1_PG_ROPAGE? */
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#define mips_pg_rwpage_bit() (MIPS1_PG_RWPAGE)
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#define mips_pg_rwncpage_bit() (MIPS1_PG_RWNCPAGE)
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#define mips_pg_cwpage_bit() (MIPS1_PG_CWPAGE)
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#define mips_pg_cwncpage_bit() (MIPS1_PG_CWNCPAGE)
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#define mips_pg_global_bit() (MIPS1_PG_G)
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#define mips_pg_wired_bit() (MIPS1_PG_WIRED)
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#define pte_to_paddr(pte) MIPS1_PTE_TO_PADDR((pte))
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#define PAGE_IS_RDONLY(pte, va) MIPS1_PAGE_IS_RDONLY((pte), (va))
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#define mips_tlbpfn_to_paddr(x) mips1_tlbpfn_to_paddr((vaddr_t)(x))
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#define mips_paddr_to_tlbpfn(x) mips1_paddr_to_tlbpfn((x))
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#endif /* mips1 */
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/* MIPS3 (or greater) only */
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#if !defined(MIPS1) && defined(MIPS3_PLUS)
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#define mips_pg_v(entry) ((entry) & MIPS3_PG_V)
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#define mips_pg_wired(entry) ((entry) & MIPS3_PG_WIRED)
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#define mips_pg_m_bit() (MIPS3_PG_D)
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#define mips_pg_rw_bit() (MIPS3_PG_D)
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#define mips_pg_ro_bit() (MIPS3_PG_RO)
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#define mips_pg_ropage_bit() (MIPS3_PG_ROPAGE)
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#define mips_pg_rwpage_bit() (MIPS3_PG_RWPAGE)
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#define mips_pg_rwncpage_bit() (MIPS3_PG_RWNCPAGE)
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#define mips_pg_cwpage_bit() (MIPS3_PG_CWPAGE)
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#define mips_pg_cwncpage_bit() (MIPS3_PG_CWNCPAGE)
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#define mips_pg_global_bit() (MIPS3_PG_G)
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#define mips_pg_wired_bit() (MIPS3_PG_WIRED)
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#define pte_to_paddr(pte) MIPS3_PTE_TO_PADDR((pte))
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#define PAGE_IS_RDONLY(pte, va) MIPS3_PAGE_IS_RDONLY((pte), (va))
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#define mips_tlbpfn_to_paddr(x) mips3_tlbpfn_to_paddr((vaddr_t)(x))
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#define mips_paddr_to_tlbpfn(x) mips3_paddr_to_tlbpfn((x))
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#endif /* mips3 */
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/* MIPS1 and MIPS3 (or greater) */
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#if defined(MIPS1) && defined(MIPS3_PLUS)
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static __inline bool
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mips_pg_v(uint32_t entry),
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mips_pg_wired(uint32_t entry),
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PAGE_IS_RDONLY(uint32_t pte, vaddr_t va);
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static __inline uint32_t
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mips_pg_wired_bit(void) __pure,
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mips_pg_m_bit(void) __pure,
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mips_pg_ro_bit(void) __pure,
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mips_pg_rw_bit(void) __pure,
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mips_pg_ropage_bit(void) __pure,
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mips_pg_cwpage_bit(void) __pure,
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mips_pg_rwpage_bit(void) __pure,
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mips_pg_global_bit(void) __pure;
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static __inline paddr_t pte_to_paddr(pt_entry_t pte) __pure;
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static __inline bool PAGE_IS_RDONLY(uint32_t pte, vaddr_t va) __pure;
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static __inline paddr_t mips_tlbpfn_to_paddr(uint32_t pfn) __pure;
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static __inline uint32_t mips_paddr_to_tlbpfn(paddr_t pa) __pure;
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static __inline bool
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mips_pg_v(uint32_t entry)
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{
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if (MIPS_HAS_R4K_MMU)
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return (entry & MIPS3_PG_V) != 0;
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return (entry & MIPS1_PG_V) != 0;
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}
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static __inline bool
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mips_pg_wired(uint32_t entry)
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{
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if (MIPS_HAS_R4K_MMU)
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return (entry & MIPS3_PG_WIRED) != 0;
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return (entry & MIPS1_PG_WIRED) != 0;
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}
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static __inline uint32_t
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mips_pg_m_bit(void)
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{
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if (MIPS_HAS_R4K_MMU)
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return (MIPS3_PG_D);
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return (MIPS1_PG_D);
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}
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static __inline unsigned int
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mips_pg_ro_bit(void)
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{
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if (MIPS_HAS_R4K_MMU)
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return (MIPS3_PG_RO);
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return (MIPS1_PG_RO);
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}
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static __inline unsigned int
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mips_pg_rw_bit(void)
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{
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if (MIPS_HAS_R4K_MMU)
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return (MIPS3_PG_D);
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return (MIPS1_PG_RW);
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}
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static __inline unsigned int
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mips_pg_ropage_bit(void)
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{
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if (MIPS_HAS_R4K_MMU)
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return (MIPS3_PG_ROPAGE);
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return (MIPS1_PG_RO);
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}
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static __inline unsigned int
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mips_pg_rwpage_bit(void)
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{
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if (MIPS_HAS_R4K_MMU)
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return (MIPS3_PG_RWPAGE);
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return (MIPS1_PG_RWPAGE);
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}
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static __inline unsigned int
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mips_pg_cwpage_bit(void)
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{
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if (MIPS_HAS_R4K_MMU)
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return (MIPS3_PG_CWPAGE);
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return (MIPS1_PG_CWPAGE);
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}
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static __inline unsigned int
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mips_pg_global_bit(void)
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{
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if (MIPS_HAS_R4K_MMU)
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return (MIPS3_PG_G);
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return (MIPS1_PG_G);
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}
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static __inline unsigned int
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mips_pg_wired_bit(void)
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{
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if (MIPS_HAS_R4K_MMU)
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return (MIPS3_PG_WIRED);
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return (MIPS1_PG_WIRED);
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}
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static __inline paddr_t
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pte_to_paddr(pt_entry_t pte)
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{
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if (MIPS_HAS_R4K_MMU)
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return (MIPS3_PTE_TO_PADDR(pte));
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return (MIPS1_PTE_TO_PADDR(pte));
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}
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static __inline bool
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PAGE_IS_RDONLY(uint32_t pte, vaddr_t va)
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{
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if (MIPS_HAS_R4K_MMU)
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return (MIPS3_PAGE_IS_RDONLY(pte, va));
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return (MIPS1_PAGE_IS_RDONLY(pte, va));
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}
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static __inline paddr_t
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mips_tlbpfn_to_paddr(uint32_t pfn)
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{
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if (MIPS_HAS_R4K_MMU)
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return (mips3_tlbpfn_to_paddr(pfn));
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return (mips1_tlbpfn_to_paddr(pfn));
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}
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static __inline uint32_t
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mips_paddr_to_tlbpfn(paddr_t pa)
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{
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if (MIPS_HAS_R4K_MMU)
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return (mips3_paddr_to_tlbpfn(pa));
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return (mips1_paddr_to_tlbpfn(pa));
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}
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#endif
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#endif /* ! _LOCORE */
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#if defined(_KERNEL) && !defined(_LOCORE)
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#define MIPS_MMU(X) (MIPS_HAS_R4K_MMU ? MIPS3_##X : MIPS1_##X)
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static inline bool
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pte_valid_p(pt_entry_t pte)
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{
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return (pte & MIPS_MMU(PG_V)) != 0;
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}
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static inline bool
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pte_modified_p(pt_entry_t pte)
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{
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return (pte & MIPS_MMU(PG_D)) != 0;
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}
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static inline bool
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pte_global_p(pt_entry_t pte)
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{
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return (pte & MIPS_MMU(PG_G)) != 0;
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}
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static inline bool
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pte_wired_p(pt_entry_t pte)
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{
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return (pte & MIPS_MMU(PG_WIRED)) != 0;
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}
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static inline pt_entry_t
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pte_wire_entry(pt_entry_t pte)
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{
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return pte | MIPS_MMU(PG_WIRED);
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}
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static inline pt_entry_t
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pte_unwire_entry(pt_entry_t pte)
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{
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return pte & ~MIPS_MMU(PG_WIRED);
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}
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static inline uint32_t
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pte_value(pt_entry_t pte)
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{
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return pte;
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}
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static inline bool
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pte_readonly_p(pt_entry_t pte)
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{
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return (pte & MIPS_MMU(PG_RO)) != 0;
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}
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static inline bool
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pte_cached_p(pt_entry_t pte)
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{
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if (MIPS_HAS_R4K_MMU) {
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return MIPS3_PG_TO_CCA(pte) == MIPS3_PG_TO_CCA(mips_options.mips3_pg_cached);
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} else {
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return (pte & MIPS1_PG_N) == 0;
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}
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}
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static inline bool
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pte_deferred_exec_p(pt_entry_t pte)
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{
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return false;
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}
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static inline pt_entry_t
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pte_nv_entry(bool kernel_p)
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{
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__CTASSERT(MIPS1_PG_NV == MIPS3_PG_NV);
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__CTASSERT(MIPS1_PG_NV == 0);
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return (kernel_p && MIPS_HAS_R4K_MMU) ? MIPS3_PG_G : 0;
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}
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static inline pt_entry_t
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pte_prot_downgrade(pt_entry_t pte, vm_prot_t prot)
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{
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const uint32_t ro_bit = MIPS_MMU(PG_RO);
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const uint32_t rw_bit = MIPS_MMU(PG_D);
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return (pte & ~(ro_bit|rw_bit))
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| ((prot & VM_PROT_WRITE) ? rw_bit : ro_bit);
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}
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static inline pt_entry_t
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pte_prot_nowrite(pt_entry_t pte)
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{
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return pte & ~MIPS_MMU(PG_D);
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}
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static inline pt_entry_t
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pte_cached_change(pt_entry_t pte, bool cached)
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{
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if (MIPS_HAS_R4K_MMU) {
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pte &= ~MIPS3_PG_CACHEMODE;
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pte |= (cached ? MIPS3_PG_CACHED : MIPS3_PG_UNCACHED);
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}
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return pte;
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}
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static inline void
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pte_set(pt_entry_t *ptep, pt_entry_t pte)
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{
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*ptep = pte;
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}
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#ifdef __PMAP_PRIVATE
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struct vm_page_md;
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static inline pt_entry_t
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pte_make_kenter_pa(paddr_t pa, struct vm_page_md *mdpg, vm_prot_t prot,
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u_int flags)
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{
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pt_entry_t pte;
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if (MIPS_HAS_R4K_MMU) {
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pte = mips3_paddr_to_tlbpfn(pa)
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| ((prot & VM_PROT_WRITE) ? MIPS3_PG_D : MIPS3_PG_RO)
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| ((flags & PMAP_NOCACHE) ? MIPS3_PG_UNCACHED : MIPS3_PG_CACHED)
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| MIPS3_PG_WIRED | MIPS3_PG_V | MIPS3_PG_G;
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} else {
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pte = mips1_paddr_to_tlbpfn(pa)
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| ((prot & VM_PROT_WRITE) ? MIPS1_PG_D : MIPS1_PG_RO)
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| ((flags & PMAP_NOCACHE) ? MIPS1_PG_N : 0)
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| MIPS1_PG_WIRED | MIPS1_PG_V | MIPS1_PG_G;
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}
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return pte;
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}
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static inline pt_entry_t
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pte_make_enter(paddr_t pa, const struct vm_page_md *mdpg, vm_prot_t prot,
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u_int flags, bool is_kernel_pmap_p)
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{
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pt_entry_t pte;
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#if defined(_MIPS_PADDR_T_64BIT) || defined(_LP64)
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const bool cached = (flags & PMAP_NOCACHE) == 0
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&& (pa & PGC_NOCACHE) == 0;
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const bool prefetch = (pa & PGC_PREFETCH) != 0;
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pa &= ~(PGC_NOCACHE|PGC_PREFETCH);
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#endif
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#if defined(cobalt) || defined(newsmips) || defined(pmax) /* otherwise ok */
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/* this is not error in general. */
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KASSERTMSG((pa & 0x80000000) == 0, "%#"PRIxPADDR, pa);
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#endif
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if (mdpg != NULL) {
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if ((prot & VM_PROT_WRITE) == 0) {
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/*
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* If page is not yet referenced, we could emulate this
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* by not setting the page valid, and setting the
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* referenced status in the TLB fault handler, similar
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* to how page modified status is done for UTLBmod
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* exceptions.
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*/
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pte = mips_pg_ropage_bit();
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#if defined(_MIPS_PADDR_T_64BIT) || defined(_LP64)
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} else if (cached == false) {
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if (VM_PAGEMD_MODIFIED_P(mdpg)) {
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pte = mips_pg_rwncpage_bit();
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} else {
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pte = mips_pg_cwncpage_bit();
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}
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#endif
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} else {
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if (VM_PAGEMD_MODIFIED_P(mdpg)) {
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pte = mips_pg_rwpage_bit();
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} else {
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pte = mips_pg_cwpage_bit();
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}
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}
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} else if (MIPS_HAS_R4K_MMU) {
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/*
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* Assumption: if it is not part of our managed memory
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* then it must be device memory which may be volatile.
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*/
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u_int cca = PMAP_CCA_FOR_PA(pa);
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#if defined(_MIPS_PADDR_T_64BIT) || defined(_LP64)
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if (prefetch)
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cca = mips_options.mips3_cca_devmem;
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#endif
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pte = MIPS3_PG_IOPAGE(cca) & ~MIPS3_PG_G;
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} else if (prot & VM_PROT_WRITE) {
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pte = MIPS1_PG_N | MIPS1_PG_D;
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} else {
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pte = MIPS1_PG_N | MIPS1_PG_RO;
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}
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if (MIPS_HAS_R4K_MMU) {
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pte |= mips3_paddr_to_tlbpfn(pa)
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| (is_kernel_pmap_p ? MIPS3_PG_G : 0);
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} else {
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pte |= mips1_paddr_to_tlbpfn(pa)
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| MIPS1_PG_V
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| (is_kernel_pmap_p ? MIPS1_PG_G : 0);
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}
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return pte;
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}
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#endif /* __PMAP_PRIVATE */
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#endif /* defined(_KERNEL) && !defined(_LOCORE) */
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#endif /* __MIPS_PTE_H__ */ |