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f4131cf8a6
This was a bit trickier than it should be due to symbol conflicts with zig's compiler-rt implementation. We attempt to use weak linkage in our compiler-rt, but this does not seem to be working in all cases. I manually disabled export of the problematic compiler-rt math functions in order to cross compile musl's libc.so for all targets as input to `tools/gen_stubs.zig`. Other than that, this update went fairly smoothly. Quite a few additional symbols were added to the blacklist in `tools/gen_stubs.zig` due to recent reorganization of zig's compiler-rt.
90 lines
2.6 KiB
C
Vendored
90 lines
2.6 KiB
C
Vendored
#define __SYSCALL_LL_E(x) \
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((union { long long ll; long l[2]; }){ .ll = x }).l[0], \
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((union { long long ll; long l[2]; }){ .ll = x }).l[1]
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#define __SYSCALL_LL_O(x) __SYSCALL_LL_E((x))
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static __inline long __syscall0(long n)
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{
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register unsigned long d0 __asm__("d0") = n;
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__asm__ __volatile__ ("trap #0" : "+r"(d0)
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:
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: "memory");
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return d0;
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}
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static inline long __syscall1(long n, long a)
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{
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register unsigned long d0 __asm__("d0") = n;
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register unsigned long d1 __asm__("d1") = a;
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__asm__ __volatile__ ("trap #0" : "+r"(d0)
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: "r"(d1)
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: "memory");
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return d0;
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}
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static inline long __syscall2(long n, long a, long b)
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{
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register unsigned long d0 __asm__("d0") = n;
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register unsigned long d1 __asm__("d1") = a;
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register unsigned long d2 __asm__("d2") = b;
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__asm__ __volatile__ ("trap #0" : "+r"(d0)
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: "r"(d1), "r"(d2)
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: "memory");
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return d0;
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}
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static inline long __syscall3(long n, long a, long b, long c)
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{
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register unsigned long d0 __asm__("d0") = n;
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register unsigned long d1 __asm__("d1") = a;
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register unsigned long d2 __asm__("d2") = b;
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register unsigned long d3 __asm__("d3") = c;
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__asm__ __volatile__ ("trap #0" : "+r"(d0)
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: "r"(d1), "r"(d2), "r"(d3)
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: "memory");
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return d0;
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}
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static inline long __syscall4(long n, long a, long b, long c, long d)
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{
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register unsigned long d0 __asm__("d0") = n;
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register unsigned long d1 __asm__("d1") = a;
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register unsigned long d2 __asm__("d2") = b;
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register unsigned long d3 __asm__("d3") = c;
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register unsigned long d4 __asm__("d4") = d;
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__asm__ __volatile__ ("trap #0" : "+r"(d0)
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: "r"(d1), "r"(d2), "r"(d3), "r"(d4)
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: "memory");
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return d0;
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}
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static inline long __syscall5(long n, long a, long b, long c, long d, long e)
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{
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register unsigned long d0 __asm__("d0") = n;
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register unsigned long d1 __asm__("d1") = a;
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register unsigned long d2 __asm__("d2") = b;
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register unsigned long d3 __asm__("d3") = c;
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register unsigned long d4 __asm__("d4") = d;
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register unsigned long d5 __asm__("d5") = e;
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__asm__ __volatile__ ("trap #0" : "+r"(d0)
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: "r"(d1), "r"(d2), "r"(d3), "r"(d4), "r"(d5)
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: "memory");
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return d0;
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}
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static inline long __syscall6(long n, long a, long b, long c, long d, long e, long f)
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{
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register unsigned long d0 __asm__("d0") = n;
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register unsigned long d1 __asm__("d1") = a;
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register unsigned long d2 __asm__("d2") = b;
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register unsigned long d3 __asm__("d3") = c;
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register unsigned long d4 __asm__("d4") = d;
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register unsigned long d5 __asm__("d5") = e;
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register unsigned long a0 __asm__("a0") = f;
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__asm__ __volatile__ ("trap #0" : "+r"(d0)
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: "r"(d1), "r"(d2), "r"(d3), "r"(d4), "r"(d5), "r"(a0)
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: "memory");
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return d0;
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}
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#define SYSCALL_IPC_BROKEN_MODE
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