mirror of
https://codeberg.org/ziglang/zig.git
synced 2025-12-07 06:14:33 +00:00
2386bfe854
The code would cause LLVM to emit a jump table for the switch in the loop over
the dynamic tags. That jump table was far enough away that the compiler decided
to go through the GOT, which would of course break at this early stage as we
haven't applied MIPS's local GOT relocations yet, nor can we until we've walked
through the _DYNAMIC array.
The first attempt at rewriting this used code like this:
var sorted_dynv = [_]elf.Addr{0} ** elf.DT_NUM;
But this is also problematic as it results in a memcpy() call. Instead, we
explicitly initialize it to undefined and use a loop of volatile stores to
clear it.
251 lines
8 KiB
Zig
251 lines
8 KiB
Zig
const std = @import("std");
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const builtin = @import("builtin");
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const elf = std.elf;
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const assert = std.debug.assert;
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const R_AMD64_RELATIVE = 8;
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const R_386_RELATIVE = 8;
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const R_ARC_RELATIVE = 56;
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const R_ARM_RELATIVE = 23;
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const R_AARCH64_RELATIVE = 1027;
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const R_CSKY_RELATIVE = 9;
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const R_HEXAGON_RELATIVE = 35;
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const R_LARCH_RELATIVE = 3;
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const R_68K_RELATIVE = 22;
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const R_MIPS_RELATIVE = 128;
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const R_PPC_RELATIVE = 22;
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const R_RISCV_RELATIVE = 3;
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const R_390_RELATIVE = 12;
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const R_SPARC_RELATIVE = 22;
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const R_RELATIVE = switch (builtin.cpu.arch) {
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.x86 => R_386_RELATIVE,
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.x86_64 => R_AMD64_RELATIVE,
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.arc => R_ARC_RELATIVE,
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.arm, .armeb, .thumb, .thumbeb => R_ARM_RELATIVE,
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.aarch64, .aarch64_be => R_AARCH64_RELATIVE,
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.csky => R_CSKY_RELATIVE,
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.hexagon => R_HEXAGON_RELATIVE,
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.loongarch32, .loongarch64 => R_LARCH_RELATIVE,
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.m68k => R_68K_RELATIVE,
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.mips, .mipsel, .mips64, .mips64el => R_MIPS_RELATIVE,
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.powerpc, .powerpcle, .powerpc64, .powerpc64le => R_PPC_RELATIVE,
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.riscv32, .riscv64 => R_RISCV_RELATIVE,
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.s390x => R_390_RELATIVE,
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else => @compileError("Missing R_RELATIVE definition for this target"),
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};
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// Obtain a pointer to the _DYNAMIC array.
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// We have to compute its address as a PC-relative quantity not to require a
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// relocation that, at this point, is not yet applied.
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inline fn getDynamicSymbol() [*]elf.Dyn {
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return switch (builtin.cpu.arch) {
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.x86 => asm volatile (
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\\ .weak _DYNAMIC
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\\ .hidden _DYNAMIC
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\\ call 1f
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\\ 1: pop %[ret]
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\\ lea _DYNAMIC-1b(%[ret]), %[ret]
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: [ret] "=r" (-> [*]elf.Dyn),
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),
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.x86_64 => asm volatile (
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\\ .weak _DYNAMIC
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\\ .hidden _DYNAMIC
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\\ lea _DYNAMIC(%%rip), %[ret]
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: [ret] "=r" (-> [*]elf.Dyn),
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),
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.arc => asm volatile (
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\\ .weak _DYNAMIC
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\\ .hidden _DYNAMIC
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\\ add %[ret], pcl, _DYNAMIC@pcl
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: [ret] "=r" (-> [*]elf.Dyn),
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),
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// Work around the limited offset range of `ldr`
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.arm, .armeb, .thumb, .thumbeb => asm volatile (
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\\ .weak _DYNAMIC
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\\ .hidden _DYNAMIC
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\\ ldr %[ret], 1f
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\\ add %[ret], pc
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\\ b 2f
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\\ 1: .word _DYNAMIC-1b
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\\ 2:
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: [ret] "=r" (-> [*]elf.Dyn),
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),
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// A simple `adr` is not enough as it has a limited offset range
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.aarch64, .aarch64_be => asm volatile (
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\\ .weak _DYNAMIC
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\\ .hidden _DYNAMIC
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\\ adrp %[ret], _DYNAMIC
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\\ add %[ret], %[ret], #:lo12:_DYNAMIC
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: [ret] "=r" (-> [*]elf.Dyn),
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),
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// The CSKY ABI requires the gb register to point to the GOT. Additionally, the first
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// entry in the GOT is defined to hold the address of _DYNAMIC.
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.csky => asm volatile (
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\\ mov %[ret], gb
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\\ ldw %[ret], %[ret]
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: [ret] "=r" (-> [*]elf.Dyn),
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),
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.hexagon => asm volatile (
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\\ .weak _DYNAMIC
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\\ .hidden _DYNAMIC
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\\ jump 1f
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\\ .word _DYNAMIC - .
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\\ 1:
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\\ r1 = pc
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\\ r1 = add(r1, #-4)
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\\ %[ret] = memw(r1)
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\\ %[ret] = add(r1, %[ret])
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: [ret] "=r" (-> [*]elf.Dyn),
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:
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: "r1"
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),
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.loongarch32, .loongarch64 => asm volatile (
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\\ .weak _DYNAMIC
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\\ .hidden _DYNAMIC
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\\ la.local %[ret], _DYNAMIC
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: [ret] "=r" (-> [*]elf.Dyn),
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),
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// Note that the - 8 is needed because pc in the second lea instruction points into the
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// middle of that instruction. (The first lea is 6 bytes, the second is 4 bytes.)
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.m68k => asm volatile (
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\\ .weak _DYNAMIC
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\\ .hidden _DYNAMIC
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\\ lea _DYNAMIC - . - 8, %[ret]
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\\ lea (%[ret], %%pc), %[ret]
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: [ret] "=r" (-> [*]elf.Dyn),
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),
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.mips, .mipsel => asm volatile (
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\\ .weak _DYNAMIC
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\\ .hidden _DYNAMIC
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\\ bal 1f
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\\ .gpword _DYNAMIC
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\\ 1:
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\\ lw %[ret], 0($ra)
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\\ addu %[ret], %[ret], $gp
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: [ret] "=r" (-> [*]elf.Dyn),
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:
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: "lr"
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),
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.mips64, .mips64el => asm volatile (
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\\ .weak _DYNAMIC
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\\ .hidden _DYNAMIC
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\\ .balign 8
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\\ bal 1f
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\\ .gpdword _DYNAMIC
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\\ 1:
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\\ ld %[ret], 0($ra)
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\\ daddu %[ret], %[ret], $gp
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: [ret] "=r" (-> [*]elf.Dyn),
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:
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: "lr"
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),
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.powerpc, .powerpcle => asm volatile (
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\\ .weak _DYNAMIC
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\\ .hidden _DYNAMIC
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\\ bl 1f
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\\ .long _DYNAMIC - .
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\\ 1:
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\\ mflr %[ret]
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\\ lwz 4, 0(%[ret])
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\\ add %[ret], 4, %[ret]
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: [ret] "=r" (-> [*]elf.Dyn),
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:
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: "lr", "r4"
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),
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.powerpc64, .powerpc64le => asm volatile (
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\\ .weak _DYNAMIC
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\\ .hidden _DYNAMIC
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\\ bl 1f
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\\ .quad _DYNAMIC - .
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\\ 1:
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\\ mflr %[ret]
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\\ ld 4, 0(%[ret])
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\\ add %[ret], 4, %[ret]
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: [ret] "=r" (-> [*]elf.Dyn),
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:
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: "lr", "r4"
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),
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.riscv32, .riscv64 => asm volatile (
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\\ .weak _DYNAMIC
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\\ .hidden _DYNAMIC
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\\ lla %[ret], _DYNAMIC
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: [ret] "=r" (-> [*]elf.Dyn),
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),
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.s390x => asm volatile (
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\\ .weak _DYNAMIC
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\\ .hidden _DYNAMIC
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\\ larl %[ret], 1f
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\\ agf %[ret], 0(%[ret])
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\\ b 2f
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\\ 1: .long _DYNAMIC - .
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\\ 2:
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: [ret] "=r" (-> [*]elf.Dyn),
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),
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else => {
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@compileError("PIE startup is not yet supported for this target!");
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},
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};
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}
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pub fn relocate(phdrs: []elf.Phdr) void {
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@setRuntimeSafety(false);
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@disableInstrumentation();
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const dynv = getDynamicSymbol();
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// Recover the delta applied by the loader by comparing the effective and
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// the theoretical load addresses for the `_DYNAMIC` symbol.
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const base_addr = base: {
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for (phdrs) |*phdr| {
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if (phdr.p_type != elf.PT_DYNAMIC) continue;
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break :base @intFromPtr(dynv) - phdr.p_vaddr;
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}
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// This is not supposed to happen for well-formed binaries.
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@trap();
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};
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var sorted_dynv: [elf.DT_NUM]elf.Addr = undefined;
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// Zero-initialized this way to prevent the compiler from turning this into
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// `memcpy` or `memset` calls (which can require relocations).
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for (&sorted_dynv) |*dyn| {
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const pdyn: *volatile elf.Addr = @ptrCast(dyn);
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pdyn.* = 0;
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}
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{
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// `dynv` has no defined order. Fix that.
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var i: usize = 0;
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while (dynv[i].d_tag != elf.DT_NULL) : (i += 1) {
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if (dynv[i].d_tag < elf.DT_NUM) sorted_dynv[@bitCast(dynv[i].d_tag)] = dynv[i].d_val;
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}
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}
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// Apply normal relocations.
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const rel = sorted_dynv[elf.DT_REL];
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if (rel != 0) {
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const rels = @call(.always_inline, std.mem.bytesAsSlice, .{
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elf.Rel,
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@as([*]u8, @ptrFromInt(base_addr + rel))[0..sorted_dynv[elf.DT_RELSZ]],
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});
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for (rels) |r| {
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if (r.r_type() != R_RELATIVE) continue;
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@as(*usize, @ptrFromInt(base_addr + r.r_offset)).* += base_addr;
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}
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}
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const rela = sorted_dynv[elf.DT_RELA];
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if (rela != 0) {
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const relas = @call(.always_inline, std.mem.bytesAsSlice, .{
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elf.Rela,
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@as([*]u8, @ptrFromInt(base_addr + rela))[0..sorted_dynv[elf.DT_RELASZ]],
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});
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for (relas) |r| {
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if (r.r_type() != R_RELATIVE) continue;
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@as(*usize, @ptrFromInt(base_addr + r.r_offset)).* = base_addr + @as(usize, @bitCast(r.r_addend));
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}
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}
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}
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