mirrors/zig
1
0
Fork 0
mirror of https://codeberg.org/ziglang/zig.git synced 2025-12-06 13:54:21 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions 1
zig/lib/std/Target
History
Alex Rønne Petersen 280ced66eb
std.Target: Define and use lime1 as the baseline CPU model for WebAssembly. 
See: https://github.com/WebAssembly/tool-conventions/pull/235

This is not *quite* using the same features as the spec'd lime1 model because
LLVM 19 doesn't have the level of feature granularity that we need for that.
This will be fixed once we upgrade to LLVM 20.

Part of #21818.
2025-01-22 03:01:05 +01:00
..
aarch64.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
amdgcn.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
arc.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
arm.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
avr.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
bpf.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
csky.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
hexagon.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
lanai.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
loongarch.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
m68k.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
mips.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
msp430.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
nvptx.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
powerpc.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
propeller.zig Adds new cpu architectures propeller1 and propeller2. (#21563) 2024-10-04 13:53:28 -07:00
Query.zig x86_64: implement clz and not 2025-01-16 20:42:08 -05:00
riscv.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
s390x.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
sparc.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
spirv.zig std: update std.builtin.Type fields to follow naming conventions 2024-08-28 08:39:59 +01:00
ve.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
wasm.zig std.Target: Define and use lime1 as the baseline CPU model for WebAssembly. 2025-01-22 03:01:05 +01:00
x86.zig x86_64: implement clz and not 2025-01-16 20:42:08 -05:00
xcore.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
xtensa.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00