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* Remove the generic model; we already have generic_la32 and generic_la64 and pick appropriately based on bitness. * Remove the loongarch64 model. We used this as our baseline for 64-bit, but it's actually pretty misleading and useless; it doesn't represent any real CPU and has less features than generic_la64. * Add la64v1_0 and la64v1_1 models. * Change our baseline CPU model for 64-bit to be la64v1_0, thus adding LSX to the baseline feature set.
230 lines
7 KiB
Zig
230 lines
7 KiB
Zig
//! This file is auto-generated by tools/update_cpu_features.zig.
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const std = @import("../std.zig");
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const CpuFeature = std.Target.Cpu.Feature;
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const CpuModel = std.Target.Cpu.Model;
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pub const Feature = enum {
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@"32bit",
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@"32s",
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@"64bit",
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d,
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div32,
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f,
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frecipe,
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la_global_with_abs,
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la_global_with_pcrel,
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la_local_with_abs,
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lam_bh,
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lamcas,
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lasx,
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lbt,
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ld_seq_sa,
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lsx,
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lvz,
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prefer_w_inst,
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relax,
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scq,
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ual,
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};
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pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
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pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
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pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
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pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
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pub const all_features = blk: {
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const len = @typeInfo(Feature).@"enum".fields.len;
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std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
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var result: [len]CpuFeature = undefined;
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result[@intFromEnum(Feature.@"32bit")] = .{
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.llvm_name = "32bit",
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.description = "LA32 Basic Integer and Privilege Instruction Set",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@intFromEnum(Feature.@"32s")] = .{
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.llvm_name = "32s",
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.description = "LA32 Standard Basic Instruction Extension",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@intFromEnum(Feature.@"64bit")] = .{
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.llvm_name = "64bit",
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.description = "LA64 Basic Integer and Privilege Instruction Set",
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.dependencies = featureSet(&[_]Feature{
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.@"32s",
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}),
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};
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result[@intFromEnum(Feature.d)] = .{
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.llvm_name = "d",
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.description = "'D' (Double-Precision Floating-Point)",
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.dependencies = featureSet(&[_]Feature{
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.f,
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}),
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};
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result[@intFromEnum(Feature.div32)] = .{
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.llvm_name = "div32",
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.description = "Assume div.w[u] and mod.w[u] can handle inputs that are not sign-extended",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@intFromEnum(Feature.f)] = .{
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.llvm_name = "f",
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.description = "'F' (Single-Precision Floating-Point)",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@intFromEnum(Feature.frecipe)] = .{
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.llvm_name = "frecipe",
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.description = "Support frecipe.{s/d} and frsqrte.{s/d} instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@intFromEnum(Feature.la_global_with_abs)] = .{
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.llvm_name = "la-global-with-abs",
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.description = "Expand la.global as la.abs",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@intFromEnum(Feature.la_global_with_pcrel)] = .{
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.llvm_name = "la-global-with-pcrel",
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.description = "Expand la.global as la.pcrel",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@intFromEnum(Feature.la_local_with_abs)] = .{
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.llvm_name = "la-local-with-abs",
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.description = "Expand la.local as la.abs",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@intFromEnum(Feature.lam_bh)] = .{
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.llvm_name = "lam-bh",
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.description = "Support amswap[_db].{b/h} and amadd[_db].{b/h} instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@intFromEnum(Feature.lamcas)] = .{
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.llvm_name = "lamcas",
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.description = "Support amcas[_db].{b/h/w/d}",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@intFromEnum(Feature.lasx)] = .{
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.llvm_name = "lasx",
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.description = "'LASX' (Loongson Advanced SIMD Extension)",
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.dependencies = featureSet(&[_]Feature{
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.lsx,
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}),
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};
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result[@intFromEnum(Feature.lbt)] = .{
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.llvm_name = "lbt",
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.description = "'LBT' (Loongson Binary Translation Extension)",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@intFromEnum(Feature.ld_seq_sa)] = .{
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.llvm_name = "ld-seq-sa",
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.description = "Don't use a same-address load-load barrier (dbar 0x700)",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@intFromEnum(Feature.lsx)] = .{
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.llvm_name = "lsx",
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.description = "'LSX' (Loongson SIMD Extension)",
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.dependencies = featureSet(&[_]Feature{
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.d,
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}),
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};
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result[@intFromEnum(Feature.lvz)] = .{
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.llvm_name = "lvz",
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.description = "'LVZ' (Loongson Virtualization Extension)",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@intFromEnum(Feature.prefer_w_inst)] = .{
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.llvm_name = "prefer-w-inst",
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.description = "Prefer instructions with W suffix",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@intFromEnum(Feature.relax)] = .{
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.llvm_name = "relax",
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.description = "Enable Linker relaxation",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@intFromEnum(Feature.scq)] = .{
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.llvm_name = "scq",
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.description = "Support sc.q instruction",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@intFromEnum(Feature.ual)] = .{
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.llvm_name = "ual",
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.description = "Allow memory accesses to be unaligned",
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.dependencies = featureSet(&[_]Feature{}),
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};
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const ti = @typeInfo(Feature);
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for (&result, 0..) |*elem, i| {
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elem.index = i;
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elem.name = ti.@"enum".fields[i].name;
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}
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break :blk result;
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};
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pub const cpu = struct {
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pub const generic_la32: CpuModel = .{
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.name = "generic_la32",
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.llvm_name = "generic-la32",
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.features = featureSet(&[_]Feature{
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.@"32bit",
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}),
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};
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pub const generic_la64: CpuModel = .{
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.name = "generic_la64",
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.llvm_name = "generic-la64",
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.features = featureSet(&[_]Feature{
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.@"64bit",
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.lsx,
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.ual,
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}),
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};
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pub const la464: CpuModel = .{
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.name = "la464",
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.llvm_name = "la464",
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.features = featureSet(&[_]Feature{
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.@"64bit",
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.lasx,
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.lbt,
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.lvz,
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.ual,
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}),
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};
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pub const la64v1_0: CpuModel = .{
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.name = "la64v1_0",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{
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.@"64bit",
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.lsx,
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.ual,
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}),
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};
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pub const la64v1_1: CpuModel = .{
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.name = "la64v1_1",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{
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.@"64bit",
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.div32,
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.frecipe,
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.lam_bh,
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.lamcas,
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.ld_seq_sa,
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.lsx,
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.scq,
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.ual,
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}),
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};
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pub const la664: CpuModel = .{
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.name = "la664",
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.llvm_name = "la664",
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.features = featureSet(&[_]Feature{
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.@"64bit",
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.div32,
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.frecipe,
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.lam_bh,
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.lamcas,
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.lasx,
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.lbt,
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.ld_seq_sa,
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.lvz,
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.scq,
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.ual,
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}),
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};
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};
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