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The big endian RISC-V effort is mostly driven by MIPS (the company) which is pivoting to RISC-V, and presumably needs a big endian variant to fill the niche that big endian MIPS (the ISA) did. GCC already supports these targets, but LLVM support will only appear in 22; this commit just adds the necessary target knowledge and checks on our end. |
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| .. | ||
| aro | ||
| aro_translate_c | ||
| reduce | ||
| resinator | ||
| aro_translate_c.zig | ||
| build_runner.zig | ||
| libc.zig | ||
| objcopy.zig | ||
| reduce.zig | ||
| std-docs.zig | ||
| test_runner.zig | ||