mirrors/zig
1
0
Fork 0
mirror of https://codeberg.org/ziglang/zig.git synced 2025-12-06 22:04:21 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions 1
zig/lib/std/Target
History
Alex Rønne Petersen 9d534790eb std.Target: Introduce Cpu convenience functions for feature tests. 
Before:

* std.Target.arm.featureSetHas(target.cpu.features, .has_v7)
* std.Target.x86.featureSetHasAny(target.cpu.features, .{ .sse, .avx, .cmov })
* std.Target.wasm.featureSetHasAll(target.cpu.features, .{ .atomics, .bulk_memory })

After:

* target.cpu.has(.arm, .has_v7)
* target.cpu.hasAny(.x86, &.{ .sse, .avx, .cmov })
* target.cpu.hasAll(.wasm, &.{ .atomics, .bulk_memory })
2025-06-05 06:12:00 +02:00
..
aarch64.zig std.Target: Update CPU models/features for LLVM 20. 2025-04-04 06:08:09 +02:00
amdgcn.zig std.Target: Update CPU models/features for LLVM 20. 2025-04-04 06:08:09 +02:00
arc.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
arm.zig std.Target: Update CPU models/features for LLVM 20. 2025-04-04 06:08:09 +02:00
avr.zig std.Target: Update CPU models/features for LLVM 20. 2025-04-04 06:08:09 +02:00
bpf.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
csky.zig std.Target: Update CPU models/features for LLVM 20. 2025-04-04 06:08:09 +02:00
generic.zig std.Target: Introduce Cpu convenience functions for feature tests. 2025-06-05 06:12:00 +02:00
hexagon.zig std.Target: Update CPU models/features for LLVM 20. 2025-04-04 06:08:09 +02:00
lanai.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
loongarch.zig std.Target: Update CPU models/features for LLVM 20. 2025-04-04 06:08:09 +02:00
m68k.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
mips.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
msp430.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
nvptx.zig std.Target: Update CPU models/features for LLVM 20. 2025-04-04 06:08:09 +02:00
powerpc.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
propeller.zig std.Target: Remove Cpu.Arch.propeller2 and use a CPU feature instead. 2025-02-17 19:17:55 +01:00
Query.zig std.Target: Introduce Cpu convenience functions for feature tests. 2025-06-05 06:12:00 +02:00
riscv.zig std.Target: Update CPU models/features for LLVM 20. 2025-04-04 06:08:09 +02:00
s390x.zig std.Target: Update CPU models/features for LLVM 20. 2025-04-04 06:08:09 +02:00
sparc.zig std.Target: Update CPU models/features for LLVM 20. 2025-04-04 06:08:09 +02:00
spirv.zig target: auto-generated spirv features 2025-05-21 15:26:18 +03:30
ve.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
wasm.zig std.Target: Update CPU models/features for LLVM 20. 2025-04-04 06:08:09 +02:00
x86.zig std.Target: Update CPU models/features for LLVM 20. 2025-04-04 06:08:09 +02:00
xcore.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00
xtensa.zig refactor update_cpu_features.zig 2024-11-25 01:11:15 -08:00