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sys/param.h was manually adjusted to not define __NetBSD_Version__ since it will be defined by the compiler.
320 lines
No EOL
11 KiB
C
Vendored
320 lines
No EOL
11 KiB
C
Vendored
/* $NetBSD: cpu_extended_state.h,v 1.17.28.1 2023/07/25 11:41:42 martin Exp $ */
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#ifndef _X86_CPU_EXTENDED_STATE_H_
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#define _X86_CPU_EXTENDED_STATE_H_
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#ifdef __lint__
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/* Lint has different packing rules and doesn't understand __aligned() */
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#define __CTASSERT_NOLINT(x) __CTASSERT(1)
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#else
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#define __CTASSERT_NOLINT(x) __CTASSERT(x)
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#endif
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/*
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* This file contains definitions of structures that match the memory layouts
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* used on x86 processors to save floating point registers and other extended
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* cpu states.
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*
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* This includes registers (etc) used by SSE/SSE2/SSE3/SSSE3/SSE4 and the later
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* AVX instructions.
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*
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* The definitions are such that any future 'extended state' should be handled,
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* provided the kernel doesn't need to know the actual contents.
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*
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* The actual structures the cpu accesses must be aligned to 16 bytes for FXSAVE
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* and 64 for XSAVE. The types aren't aligned because copies do not need extra
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* alignment.
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*
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* The slightly different layout saved by the i387 fsave is also defined.
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* This is only normally written by pre Pentium II type cpus that don't
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* support the fxsave instruction.
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*
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* Associated save instructions:
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* FNSAVE: Saves x87 state in 108 bytes (original i387 layout). Then
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* reinitializes the fpu.
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* FSAVE: Encodes to FWAIT followed by FNSAVE.
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* FXSAVE: Saves the x87 state and XMM (aka SSE) registers to the first
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* 448 (max) bytes of a 512 byte area. This layout does not match
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* that written by FNSAVE.
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* XSAVE: Uses the same layout for the x87 and XMM registers, followed by
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* a 64byte header and separate save areas for additional extended
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* cpu states. The x87 state is always saved, the others
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* conditionally.
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* XSAVEOPT: Same as XSAVE but only writes the registers blocks that have
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* been modified.
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*/
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/*
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* Layout for code/data pointers relating to FP exceptions. Marked 'packed'
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* because they aren't always 64bit aligned. Since the x86 cpu supports
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* misaligned accesses it isn't worth avoiding the 'packed' attribute.
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*/
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union fp_addr {
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uint64_t fa_64; /* Linear address for 64bit systems */
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struct {
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uint32_t fa_off; /* linear address for 32 bit */
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uint16_t fa_seg; /* code/data (etc) segment */
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uint16_t fa_opcode; /* last opcode (sometimes) */
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} fa_32;
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} __packed __aligned(4);
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/* The x87 registers are 80 bits */
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struct fpacc87 {
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uint64_t f87_mantissa; /* mantissa */
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uint16_t f87_exp_sign; /* exponent and sign */
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} __packed __aligned(2);
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/* The x87 registers padded out to 16 bytes for fxsave */
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struct fpaccfx {
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struct fpacc87 r __aligned(16);
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};
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/* The SSE/SSE2 registers are 128 bits */
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struct xmmreg {
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uint8_t xmm_bytes[16];
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};
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/* The AVX registers are 256 bits, but the low bits are the xmmregs */
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struct ymmreg {
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uint8_t ymm_bytes[16];
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};
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/* The AVX-512 registers are 512 bits but the low bits are in xmmregs
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* and ymmregs */
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struct zmmreg {
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uint8_t zmm_bytes[32];
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};
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/* 512-bit ZMM register. */
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struct hi16_zmmreg {
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uint8_t zmm_bytes[64];
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};
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/*
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* Floating point unit registers (FSAVE instruction).
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*
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* The s87_ac[] and fx_87_ac[] are relative to the stack top. The 'tag word'
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* contains 2 bits per register and refers to absolute register numbers.
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*
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* The cpu sets the tag values 0b01 (zero) and 0b10 (special) when a value
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* is loaded. The software need only set 0b00 (used) and 0xb11 (unused).
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* The fxsave 'Abridged tag word' in inverted.
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*/
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struct save87 {
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uint16_t s87_cw __aligned(4); /* control word */
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uint16_t s87_sw __aligned(4); /* status word */
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uint16_t s87_tw __aligned(4); /* tag word */
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union fp_addr s87_ip; /* floating point instruction pointer */
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#define s87_opcode s87_ip.fa_32.fa_opcode /* opcode last executed (11bits) */
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union fp_addr s87_dp; /* floating operand offset */
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struct fpacc87 s87_ac[8]; /* accumulator contents */
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};
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__CTASSERT_NOLINT(sizeof(struct save87) == 108);
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/*
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* FPU/MMX/SSE/SSE2 context (FXSAVE instruction).
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*/
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struct fxsave {
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uint16_t fx_cw; /* FPU Control Word */
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uint16_t fx_sw; /* FPU Status Word */
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uint8_t fx_tw; /* FPU Tag Word (abridged) */
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uint8_t fx_zero; /* zero */
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uint16_t fx_opcode; /* FPU Opcode */
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union fp_addr fx_ip; /* FPU Instruction Pointer */
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union fp_addr fx_dp; /* FPU Data pointer */
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uint32_t fx_mxcsr; /* MXCSR Register State */
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uint32_t fx_mxcsr_mask;
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struct fpaccfx fx_87_ac[8]; /* 8 x87 registers */
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struct xmmreg fx_xmm[16]; /* XMM regs (8 in 32bit modes) */
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uint8_t fx_rsvd[96];
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} __aligned(16);
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__CTASSERT_NOLINT(sizeof(struct fxsave) == 512);
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/*
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* For XSAVE, a 64byte header follows the fxsave data.
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*/
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struct xsave_header {
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uint8_t xsh_fxsave[512]; /* struct fxsave */
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uint64_t xsh_xstate_bv; /* bitmap of saved sub structures */
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uint64_t xsh_xcomp_bv; /* bitmap of compact sub structures */
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uint8_t xsh_rsrvd[8]; /* must be zero */
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uint8_t xsh_reserved[40]; /* best if zero */
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};
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__CTASSERT(sizeof(struct xsave_header) == 512 + 64);
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/*
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* The ymm save area actually follows the xsave_header.
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*/
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struct xsave_ymm {
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struct ymmreg xs_ymm[16]; /* High bits of YMM registers */
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};
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__CTASSERT(sizeof(struct xsave_ymm) == 256);
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/*
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* AVX-512: opmask state.
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*/
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struct xsave_opmask {
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uint64_t xs_k[8]; /* k0..k7 registers. */
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};
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__CTASSERT(sizeof(struct xsave_opmask) == 64);
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/*
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* AVX-512: ZMM_Hi256 state.
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*/
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struct xsave_zmm_hi256 {
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struct zmmreg xs_zmm[16]; /* High bits of zmm0..zmm15 registers. */
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};
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__CTASSERT(sizeof(struct xsave_zmm_hi256) == 512);
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/*
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* AVX-512: Hi16_ZMM state.
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*/
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struct xsave_hi16_zmm {
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struct hi16_zmmreg xs_hi16_zmm[16]; /* zmm16..zmm31 registers. */
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};
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__CTASSERT(sizeof(struct xsave_hi16_zmm) == 1024);
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/*
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* Structure used to hold all interesting data from XSAVE, in predictable form.
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* Note that this structure can have new members added to the end.
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*/
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struct xstate {
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/*
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* The two following fields are bitmaps of XSAVE components. They can be
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* matched against XCR0_* constants from <machine/specialreg.h>).
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*/
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/*
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* XSAVE/XRSTOR RFBM parameter.
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*
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* PT_GETXSTATE: 1 indicates that the respective XSAVE component is
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* supported and has been enabled for saving. 0 indicates that it is not
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* supported by the platform or kernel.
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*
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* PT_SETXSTATE: 1 indicates that the respective XSAVE component should
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* be updated to the value of respective field (or reset if xs_xsave_bv
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* bit is 0). 0 indicates that it should be left intact. It is an error
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* to enable bits that are not supported by the platform or kernel.
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*/
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uint64_t xs_rfbm;
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/*
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* XSAVE/XRSTOR xstate header.
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*
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* PT_GETXSTATE: 1 indicates that the respective XSAVE component has been
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* saved. 0 indicates that it had been in its CPU-defined initial value
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* at the time of saving (i.e. was not used by the program).
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*
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* PT_SETXSTATE: 1 indicates that the respective XSAVE component (if present
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* in xs_rfbm) should be set to the values in respective field. 0 indicates
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* that it should be reset to CPU-defined initial value.
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*/
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uint64_t xs_xstate_bv;
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/* legacy FXSAVE area (used for x87 & SSE state) */
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struct fxsave xs_fxsave;
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/* AVX state: high bits of ymm0..ymm15 registers */
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struct xsave_ymm xs_ymm_hi128;
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/* AVX-512: opmask */
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struct xsave_opmask xs_opmask;
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/* AVX-512: high bits of zmm0..zmm15 registers */
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struct xsave_zmm_hi256 xs_zmm_hi256;
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/* AVX-512: whole zmm16..zmm31 registers */
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struct xsave_hi16_zmm xs_hi16_zmm;
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};
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/*
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* The following union is placed at the end of the pcb.
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* It is defined this way to separate the definitions and to
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* minimise the number of union/struct selectors.
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* NB: Some userspace stuff (eg firefox) uses it to parse ucontext.
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*/
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union savefpu {
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struct save87 sv_87;
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struct fxsave sv_xmm;
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#ifdef _KERNEL
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struct xsave_header sv_xsave_hdr;
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#endif
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};
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/*
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* 80387 control and status word bits
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*
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* The only reference I can find to bits 0x40 and 0x80 in the control word
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* is for the Weitek 1167/3167.
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* I (dsl) can't find why the default word has 0x40 set.
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*
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* A stack error is signalled as an INVOP that also sets STACK_FAULT
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* (other INVOP do not clear STACK_FAULT).
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*/
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/* Interrupt masks (set masks interrupt) and status bits */
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#define EN_SW_INVOP 0x0001 /* Invalid operation */
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#define EN_SW_DENORM 0x0002 /* Denormalized operand */
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#define EN_SW_ZERODIV 0x0004 /* Divide by zero */
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#define EN_SW_OVERFLOW 0x0008 /* Overflow */
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#define EN_SW_UNDERFLOW 0x0010 /* Underflow */
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#define EN_SW_PRECLOSS 0x0020 /* Loss of precision */
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/* Status word bits (reserved in control word) */
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#define EN_SW_STACK_FAULT 0x0040 /* Stack under/overflow */
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#define EN_SW_ERROR_SUMMARY 0x0080 /* Unmasked error has occurred */
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/* Control bits (badly named) */
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#define EN_SW_CTL_PREC 0x0300 /* Precision control */
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#define EN_SW_PREC_24 0x0000 /* Single precision */
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#define EN_SW_PREC_53 0x0200 /* Double precision */
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#define EN_SW_PREC_64 0x0300 /* Extended precision */
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#define EN_SW_CTL_ROUND 0x0c00 /* Rounding control */
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#define EN_SW_ROUND_EVEN 0x0000 /* Round to nearest even */
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#define EN_SW_ROUND_DOWN 0x0400 /* Round towards minus infinity */
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#define EN_SW_ROUND_UP 0x0800 /* Round towards plus infinity */
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#define EN_SW_ROUND_ZERO 0x0c00 /* Round towards zero (truncates) */
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#define EN_SW_CTL_INF 0x1000 /* Infinity control, not used */
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/*
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* The standard 0x87 control word from finit is 0x37F, giving:
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* round to nearest
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* 64-bit precision
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* all exceptions masked.
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*
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* NetBSD used to select:
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* round to nearest
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* 53-bit precision
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* all exceptions masked.
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* Stating: 64-bit precision often gives bad results with high level
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* languages because it makes the results of calculations depend on whether
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* intermediate values are stored in memory or in FPU registers.
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* Also some 'pathological divisions' give an error in the LSB because
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* the value is first rounded up when the 64bit mantissa is generated,
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* and then again when it is truncated to 53 bits.
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*
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* However the C language explicitly allows the extra precision.
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*/
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#define __INITIAL_NPXCW__ 0x037f
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/* Modern NetBSD uses the default control word.. */
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#define __NetBSD_NPXCW__ __INITIAL_NPXCW__
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/* NetBSD before 6.99.26 forced IEEE double precision. */
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#define __NetBSD_COMPAT_NPXCW__ 0x127f
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/* FreeBSD leaves some exceptions unmasked as well. */
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#define __FreeBSD_NPXCW__ 0x1272
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/* Linux just uses the default control word. */
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#define __Linux_NPXCW__ __INITIAL_NPXCW__
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/*
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* The default MXCSR value at reset is 0x1f80, IA-32 Instruction
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* Set Reference, pg. 3-369.
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*
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* The low 6 bits of the mxcsr are the fp status bits (same order as x87).
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* Bit 6 is 'denormals are zero' (speeds up calculations).
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* Bits 7-16 are the interrupt mask bits (same order, 1 to mask).
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* Bits 13 and 14 are rounding control.
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* Bit 15 is 'flush to zero' - affects underflow.
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* Bits 16-31 must be zero.
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*
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* The safe MXCSR is fit for constant-time use, e.g. in crypto. Some
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* CPU instructions take input- dependent time if an exception status
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* bit is not set; __SAFE_MXCSR__ has the exception status bits all set
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* already to mitigate this. See:
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* https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/best-practices/mxcsr-configuration-dependent-timing.html
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*/
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#define __INITIAL_MXCSR__ 0x1f80
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#define __INITIAL_MXCSR_MASK__ 0xffbf
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#define __SAFE_MXCSR__ 0x1fbf
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#endif /* _X86_CPU_EXTENDED_STATE_H_ */ |