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553cb3ed46
sys/param.h was manually adjusted to not define __NetBSD_Version__ since it will be defined by the compiler.
257 lines
No EOL
7 KiB
C
Vendored
257 lines
No EOL
7 KiB
C
Vendored
/* $NetBSD: cpu.h,v 1.48.2.1 2024/10/13 10:43:11 martin Exp $ */
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/*-
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* Copyright (c) 2014, 2020 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _AARCH64_CPU_H_
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#define _AARCH64_CPU_H_
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#include <arm/cpu.h>
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#ifdef __aarch64__
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#ifdef _KERNEL_OPT
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#include "opt_gprof.h"
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#include "opt_multiprocessor.h"
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#include "opt_pmap.h"
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#endif
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#include <sys/param.h>
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#if defined(_KERNEL) || defined(_KMEMUSER)
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#include <sys/evcnt.h>
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#include <aarch64/armreg.h>
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#include <aarch64/frame.h>
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struct clockframe {
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struct trapframe cf_tf;
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};
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/* (spsr & 15) == SPSR_M_EL0T(64bit,0) or USER(32bit,0) */
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#define CLKF_USERMODE(cf) ((((cf)->cf_tf.tf_spsr) & 0x0f) == 0)
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#define CLKF_PC(cf) ((cf)->cf_tf.tf_pc)
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#define CLKF_INTR(cf) ((void)(cf), curcpu()->ci_intr_depth > 1)
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/*
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* LWP_PC: Find out the program counter for the given lwp.
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*/
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#define LWP_PC(l) ((l)->l_md.md_utf->tf_pc)
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#include <sys/cpu_data.h>
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#include <sys/device_if.h>
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#include <sys/intr.h>
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struct aarch64_cpufuncs {
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void (*cf_set_ttbr0)(uint64_t);
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void (*cf_icache_sync_range)(vaddr_t, vsize_t);
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};
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#define MAX_CACHE_LEVEL 8 /* ARMv8 has maximum 8 level cache */
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struct aarch64_cache_unit {
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u_int cache_type;
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#define CACHE_TYPE_VPIPT 0 /* VMID-aware PIPT */
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#define CACHE_TYPE_VIVT 1 /* ASID-tagged VIVT */
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#define CACHE_TYPE_VIPT 2
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#define CACHE_TYPE_PIPT 3
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u_int cache_line_size;
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u_int cache_ways;
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u_int cache_sets;
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u_int cache_way_size;
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u_int cache_size;
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};
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struct aarch64_cache_info {
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u_int cacheable;
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#define CACHE_CACHEABLE_NONE 0
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#define CACHE_CACHEABLE_ICACHE 1 /* instruction cache only */
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#define CACHE_CACHEABLE_DCACHE 2 /* data cache only */
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#define CACHE_CACHEABLE_IDCACHE 3 /* instruction and data caches */
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#define CACHE_CACHEABLE_UNIFIED 4 /* unified cache */
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struct aarch64_cache_unit icache;
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struct aarch64_cache_unit dcache;
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};
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struct cpu_info {
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struct cpu_data ci_data;
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device_t ci_dev;
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cpuid_t ci_cpuid;
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/*
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* the following are in their own cache line, as they are stored to
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* regularly by remote CPUs; when they were mixed with other fields
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* we observed frequent cache misses.
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*/
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int ci_want_resched __aligned(COHERENCY_UNIT);
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/* XXX pending IPIs? */
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/*
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* this is stored frequently, and is fetched by remote CPUs.
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*/
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struct lwp *ci_curlwp __aligned(COHERENCY_UNIT);
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struct lwp *ci_onproc;
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/*
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* largely CPU-private.
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*/
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struct lwp *ci_softlwps[SOFTINT_COUNT] __aligned(COHERENCY_UNIT);
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uint64_t ci_lastintr;
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int ci_mtx_oldspl;
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int ci_mtx_count;
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int ci_cpl; /* current processor level (spl) */
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volatile int ci_hwpl; /* current hardware priority */
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volatile u_int ci_softints;
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volatile u_int ci_intr_depth;
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volatile uint32_t ci_blocked_pics;
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volatile uint32_t ci_pending_pics;
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volatile uint32_t ci_pending_ipls;
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int ci_kfpu_spl;
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#if defined(PMAP_MI)
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struct pmap_tlb_info *ci_tlb_info;
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struct pmap *ci_pmap_lastuser;
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struct pmap *ci_pmap_cur;
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#endif
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/* ASID of current pmap */
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tlb_asid_t ci_pmap_asid_cur;
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/* event counters */
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struct evcnt ci_vfp_use;
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struct evcnt ci_vfp_reuse;
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struct evcnt ci_vfp_save;
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struct evcnt ci_vfp_release;
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struct evcnt ci_uct_trap;
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struct evcnt ci_intr_preempt;
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struct evcnt ci_rndrrs_fail;
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/* FDT or similar supplied "cpu capacity" */
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uint32_t ci_capacity_dmips_mhz;
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/* interrupt controller */
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u_int ci_gic_redist; /* GICv3 redistributor index */
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uint64_t ci_gic_sgir; /* GICv3 SGIR target */
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/* ACPI */
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uint32_t ci_acpiid; /* ACPI Processor Unique ID */
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/* cached system registers */
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uint64_t ci_sctlr_el1;
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uint64_t ci_sctlr_el2;
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/* sysctl(9) exposed system registers */
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struct aarch64_sysctl_cpu_id ci_id;
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/* cache information and function pointers */
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struct aarch64_cache_info ci_cacheinfo[MAX_CACHE_LEVEL];
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struct aarch64_cpufuncs ci_cpufuncs;
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#if defined(GPROF) && defined(MULTIPROCESSOR)
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struct gmonparam *ci_gmon; /* MI per-cpu GPROF */
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#endif
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} __aligned(COHERENCY_UNIT);
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#ifdef _KERNEL
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static inline __always_inline struct lwp * __attribute__ ((const))
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aarch64_curlwp(void)
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{
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struct lwp *l;
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__asm("mrs %0, tpidr_el1" : "=r"(l));
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return l;
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}
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/* forward declaration; defined in sys/lwp.h. */
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static __inline struct cpu_info *lwp_getcpu(struct lwp *);
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#define curcpu() (lwp_getcpu(aarch64_curlwp()))
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#define setsoftast(ci) (cpu_signotify((ci)->ci_onproc))
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#undef curlwp
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#define curlwp (aarch64_curlwp())
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#define curpcb ((struct pcb *)lwp_getpcb(curlwp))
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void cpu_signotify(struct lwp *l);
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void cpu_need_proftick(struct lwp *l);
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void cpu_hatch(struct cpu_info *);
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extern struct cpu_info *cpu_info[];
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extern struct cpu_info cpu_info_store[];
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#define CPU_INFO_ITERATOR int
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#if defined(MULTIPROCESSOR) || defined(_MODULE)
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#define cpu_number() (curcpu()->ci_index)
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#define CPU_IS_PRIMARY(ci) ((ci)->ci_index == 0)
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#define CPU_INFO_FOREACH(cii, ci) \
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cii = 0, ci = cpu_info[0]; \
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cii < (ncpu ? ncpu : 1) && (ci = cpu_info[cii]) != NULL; \
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cii++
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#else /* MULTIPROCESSOR */
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#define cpu_number() 0
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#define CPU_IS_PRIMARY(ci) true
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#define CPU_INFO_FOREACH(cii, ci) \
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cii = 0, __USE(cii), ci = curcpu(); ci != NULL; ci = NULL
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#endif /* MULTIPROCESSOR */
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#define LWP0_CPU_INFO (&cpu_info_store[0])
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#define __HAVE_CPU_DOSOFTINTS_CI
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static inline void
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cpu_dosoftints_ci(struct cpu_info *ci)
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{
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#if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS)
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void dosoftints(void);
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if (ci->ci_intr_depth == 0 && (ci->ci_softints >> ci->ci_cpl) > 0) {
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dosoftints();
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}
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#endif
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}
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static inline void
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cpu_dosoftints(void)
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{
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#if defined(__HAVE_FAST_SOFTINTS) && !defined(__HAVE_PIC_FAST_SOFTINTS)
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cpu_dosoftints_ci(curcpu());
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#endif
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}
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#endif /* _KERNEL */
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#endif /* _KERNEL || _KMEMUSER */
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#endif
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#endif /* _AARCH64_CPU_H_ */ |