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bdca0f93c4
Fixes #25209. On PowerPC, some registers are both inputs to syscalls and clobbered by them. An example is r0, which initially contains the syscall number, but may be overwritten during execution of the syscall. musl and glibc use a `+` (read-write) constraint to indicate this, which isn't supported in Zig. The current implementation of PowerPC syscalls in the Zig standard library instead lists these registers as both inputs and clobbers, but this results in the C backend generating code that is invalid for at least some C compilers, like GCC, which doesn't support the specifying the same register as both an input and a clobber. This PR changes the PowerPC syscall functions to list such registers as inputs and outputs rather than inputs and clobbers. Thanks to jacobly0 who pointed out that it's possible to have multiple outputs; I had gotten the wrong idea from the documentation. |
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| .. | ||
| bpf | ||
| aarch64.zig | ||
| arm.zig | ||
| bpf.zig | ||
| hexagon.zig | ||
| io_uring_sqe.zig | ||
| ioctl.zig | ||
| IoUring.zig | ||
| loongarch64.zig | ||
| m68k.zig | ||
| mips.zig | ||
| mips64.zig | ||
| powerpc.zig | ||
| powerpc64.zig | ||
| riscv32.zig | ||
| riscv64.zig | ||
| s390x.zig | ||
| seccomp.zig | ||
| sparc64.zig | ||
| syscalls.zig | ||
| test.zig | ||
| thumb.zig | ||
| tls.zig | ||
| vdso.zig | ||
| x86.zig | ||
| x86_64.zig | ||