mirror of
https://codeberg.org/ziglang/zig.git
synced 2025-12-07 14:24:43 +00:00
495 lines
17 KiB
Zig
495 lines
17 KiB
Zig
const builtin = @import("builtin");
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const std = @import("std");
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const Io = std.Io;
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const mem = std.mem;
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const fs = std.fs;
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const fmt = std.fmt;
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const testing = std.testing;
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const Target = std.Target;
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const assert = std.debug.assert;
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const SparcCpuinfoImpl = struct {
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model: ?*const Target.Cpu.Model = null,
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const cpu_names = .{
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.{ "SuperSparc", &Target.sparc.cpu.supersparc },
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.{ "HyperSparc", &Target.sparc.cpu.hypersparc },
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.{ "SpitFire", &Target.sparc.cpu.ultrasparc },
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.{ "BlackBird", &Target.sparc.cpu.ultrasparc },
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.{ "Sabre", &Target.sparc.cpu.ultrasparc },
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.{ "Hummingbird", &Target.sparc.cpu.ultrasparc },
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.{ "Cheetah", &Target.sparc.cpu.ultrasparc3 },
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.{ "Jalapeno", &Target.sparc.cpu.ultrasparc3 },
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.{ "Jaguar", &Target.sparc.cpu.ultrasparc3 },
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.{ "Panther", &Target.sparc.cpu.ultrasparc3 },
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.{ "Serrano", &Target.sparc.cpu.ultrasparc3 },
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.{ "UltraSparc T1", &Target.sparc.cpu.niagara },
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.{ "UltraSparc T2", &Target.sparc.cpu.niagara2 },
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.{ "UltraSparc T3", &Target.sparc.cpu.niagara3 },
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.{ "UltraSparc T4", &Target.sparc.cpu.niagara4 },
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.{ "UltraSparc T5", &Target.sparc.cpu.niagara4 },
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.{ "LEON", &Target.sparc.cpu.leon3 },
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};
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fn line_hook(self: *SparcCpuinfoImpl, key: []const u8, value: []const u8) !bool {
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if (mem.eql(u8, key, "cpu")) {
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inline for (cpu_names) |pair| {
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if (mem.findPos(u8, value, 0, pair[0]) != null) {
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self.model = pair[1];
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break;
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}
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}
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}
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return true;
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}
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fn finalize(self: *const SparcCpuinfoImpl, arch: Target.Cpu.Arch) ?Target.Cpu {
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const model = self.model orelse return null;
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return Target.Cpu{
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.arch = arch,
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.model = model,
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.features = model.features,
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};
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}
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};
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const SparcCpuinfoParser = CpuinfoParser(SparcCpuinfoImpl);
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test "cpuinfo: SPARC" {
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try testParser(SparcCpuinfoParser, .sparc64, &Target.sparc.cpu.niagara2,
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\\cpu : UltraSparc T2 (Niagara2)
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\\fpu : UltraSparc T2 integrated FPU
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\\pmu : niagara2
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\\type : sun4v
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);
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}
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const RiscvCpuinfoImpl = struct {
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model: ?*const Target.Cpu.Model = null,
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const cpu_names = .{
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.{ "sifive,u54", &Target.riscv.cpu.sifive_u54 },
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.{ "sifive,u54-mc", &Target.riscv.cpu.sifive_u54 },
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.{ "sifive,u7", &Target.riscv.cpu.sifive_7_series },
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.{ "sifive,u74", &Target.riscv.cpu.sifive_u74 },
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.{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 },
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.{ "spacemit,x60", &Target.riscv.cpu.spacemit_x60 },
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};
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fn line_hook(self: *RiscvCpuinfoImpl, key: []const u8, value: []const u8) !bool {
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if (mem.eql(u8, key, "uarch")) {
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inline for (cpu_names) |pair| {
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if (mem.eql(u8, value, pair[0])) {
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self.model = pair[1];
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break;
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}
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}
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return false;
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}
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return true;
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}
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fn finalize(self: *const RiscvCpuinfoImpl, arch: Target.Cpu.Arch) ?Target.Cpu {
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const model = self.model orelse return null;
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return Target.Cpu{
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.arch = arch,
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.model = model,
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.features = model.features,
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};
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}
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};
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const RiscvCpuinfoParser = CpuinfoParser(RiscvCpuinfoImpl);
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test "cpuinfo: RISC-V" {
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try testParser(RiscvCpuinfoParser, .riscv64, &Target.riscv.cpu.sifive_u74,
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\\processor : 0
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\\hart : 1
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\\isa : rv64imafdc
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\\mmu : sv39
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\\isa-ext :
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\\uarch : sifive,u74-mc
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);
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}
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const PowerpcCpuinfoImpl = struct {
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model: ?*const Target.Cpu.Model = null,
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const cpu_names = .{
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.{ "604e", &Target.powerpc.cpu.@"604e" },
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.{ "604", &Target.powerpc.cpu.@"604" },
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.{ "7400", &Target.powerpc.cpu.@"7400" },
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.{ "7410", &Target.powerpc.cpu.@"7400" },
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.{ "7447", &Target.powerpc.cpu.@"7400" },
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.{ "7455", &Target.powerpc.cpu.@"7450" },
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.{ "G4", &Target.powerpc.cpu.g4 },
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.{ "POWER4", &Target.powerpc.cpu.@"970" },
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.{ "PPC970FX", &Target.powerpc.cpu.@"970" },
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.{ "PPC970MP", &Target.powerpc.cpu.@"970" },
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.{ "G5", &Target.powerpc.cpu.g5 },
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.{ "POWER5", &Target.powerpc.cpu.g5 },
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.{ "A2", &Target.powerpc.cpu.a2 },
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.{ "POWER6", &Target.powerpc.cpu.pwr6 },
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.{ "POWER7", &Target.powerpc.cpu.pwr7 },
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.{ "POWER8", &Target.powerpc.cpu.pwr8 },
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.{ "POWER8E", &Target.powerpc.cpu.pwr8 },
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.{ "POWER8NVL", &Target.powerpc.cpu.pwr8 },
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.{ "POWER9", &Target.powerpc.cpu.pwr9 },
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.{ "POWER10", &Target.powerpc.cpu.pwr10 },
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.{ "POWER11", &Target.powerpc.cpu.pwr11 },
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};
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fn line_hook(self: *PowerpcCpuinfoImpl, key: []const u8, value: []const u8) !bool {
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if (mem.eql(u8, key, "cpu")) {
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// The model name is often followed by a comma or space and extra
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// info.
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inline for (cpu_names) |pair| {
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const end_index = mem.findAny(u8, value, ", ") orelse value.len;
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if (mem.eql(u8, value[0..end_index], pair[0])) {
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self.model = pair[1];
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break;
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}
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}
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// Stop the detection once we've seen the first core.
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return false;
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}
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return true;
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}
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fn finalize(self: *const PowerpcCpuinfoImpl, arch: Target.Cpu.Arch) ?Target.Cpu {
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const model = self.model orelse return null;
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return Target.Cpu{
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.arch = arch,
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.model = model,
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.features = model.features,
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};
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}
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};
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const PowerpcCpuinfoParser = CpuinfoParser(PowerpcCpuinfoImpl);
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test "cpuinfo: PowerPC" {
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try testParser(PowerpcCpuinfoParser, .powerpc, &Target.powerpc.cpu.@"970",
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\\processor : 0
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\\cpu : PPC970MP, altivec supported
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\\clock : 1250.000000MHz
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\\revision : 1.1 (pvr 0044 0101)
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);
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try testParser(PowerpcCpuinfoParser, .powerpc64le, &Target.powerpc.cpu.pwr8,
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\\processor : 0
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\\cpu : POWER8 (raw), altivec supported
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\\clock : 2926.000000MHz
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\\revision : 2.0 (pvr 004d 0200)
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);
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}
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const S390xCpuinfoImpl = struct {
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model: ?*const Target.Cpu.Model = null,
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const cpu_names = .{
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// z900: 2064, 2066
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// z990: 2084, 2086
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// z9: 2094, 2096
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.{ "2097", &Target.s390x.cpu.z10 },
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.{ "2098", &Target.s390x.cpu.z10 },
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.{ "2817", &Target.s390x.cpu.z196 },
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.{ "2818", &Target.s390x.cpu.z196 },
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.{ "2827", &Target.s390x.cpu.zEC12 },
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.{ "2828", &Target.s390x.cpu.zEC12 },
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.{ "2964", &Target.s390x.cpu.z13 },
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.{ "2965", &Target.s390x.cpu.z13 },
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.{ "3906", &Target.s390x.cpu.z14 },
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.{ "3907", &Target.s390x.cpu.z14 },
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.{ "8561", &Target.s390x.cpu.z15 },
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.{ "8562", &Target.s390x.cpu.z15 },
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.{ "3931", &Target.s390x.cpu.z16 },
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.{ "3932", &Target.s390x.cpu.z16 },
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.{ "9175", &Target.s390x.cpu.z17 },
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.{ "9176", &Target.s390x.cpu.z17 },
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};
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fn line_hook(self: *S390xCpuinfoImpl, key: []const u8, value: []const u8) !bool {
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if (mem.eql(u8, key, "machine")) {
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inline for (cpu_names) |pair| {
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if (mem.eql(u8, value, pair[0])) {
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self.model = pair[1];
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break;
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}
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}
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return false;
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}
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return true;
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}
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fn finalize(self: *const S390xCpuinfoImpl, arch: Target.Cpu.Arch) ?Target.Cpu {
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const model = self.model orelse return null;
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return Target.Cpu{
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.arch = arch,
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.model = model,
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.features = model.features,
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};
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}
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};
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const S390xCpuinfoParser = CpuinfoParser(S390xCpuinfoImpl);
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test "cpuinfo: S390x" {
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try testParser(S390xCpuinfoParser, .s390x, &Target.s390x.cpu.z15,
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\\physical id : 5
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\\core id : 5
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\\book id : 5
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\\drawer id : 5
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\\dedicated : 0
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\\address : 5
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\\siblings : 1
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\\cpu cores : 1
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\\version : FF
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\\identification : 09DD98
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\\machine : 8561
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\\cpu MHz dynamic : 5200
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\\cpu MHz static : 5200
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);
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}
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const ArmCpuinfoImpl = struct {
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const num_cores = 4;
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cores: [num_cores]CoreInfo = undefined,
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core_no: usize = 0,
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have_fields: usize = 0,
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const CoreInfo = struct {
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architecture: u8 = 0,
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implementer: u8 = 0,
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variant: u8 = 0,
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part: u16 = 0,
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is_really_v6: bool = false,
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};
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const cpu_models = @import("arm.zig").cpu_models;
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fn addOne(self: *ArmCpuinfoImpl) void {
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if (self.have_fields == 4 and self.core_no < num_cores) {
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if (self.core_no > 0) {
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// Deduplicate the core info.
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for (self.cores[0..self.core_no]) |it| {
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if (std.meta.eql(it, self.cores[self.core_no]))
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return;
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}
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}
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self.core_no += 1;
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}
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}
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fn line_hook(self: *ArmCpuinfoImpl, key: []const u8, value: []const u8) !bool {
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const info = &self.cores[self.core_no];
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if (mem.eql(u8, key, "processor")) {
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// Handle both old-style and new-style cpuinfo formats.
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// The former prints a sequence of "processor: N" lines for each
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// core and then the info for the core that's executing this code(!)
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// while the latter prints the infos for each core right after the
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// "processor" key.
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self.have_fields = 0;
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self.cores[self.core_no] = .{};
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} else if (mem.eql(u8, key, "CPU implementer")) {
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info.implementer = try fmt.parseInt(u8, value, 0);
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self.have_fields += 1;
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} else if (mem.eql(u8, key, "CPU architecture")) {
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// "AArch64" on older kernels.
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info.architecture = if (mem.startsWith(u8, value, "AArch64"))
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8
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else
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try fmt.parseInt(u8, value, 0);
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self.have_fields += 1;
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} else if (mem.eql(u8, key, "CPU variant")) {
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info.variant = try fmt.parseInt(u8, value, 0);
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self.have_fields += 1;
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} else if (mem.eql(u8, key, "CPU part")) {
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info.part = try fmt.parseInt(u16, value, 0);
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self.have_fields += 1;
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} else if (mem.eql(u8, key, "model name")) {
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// ARMv6 cores report "CPU architecture" equal to 7.
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if (mem.find(u8, value, "(v6l)")) |_| {
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info.is_really_v6 = true;
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}
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} else if (mem.eql(u8, key, "CPU revision")) {
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// This field is always the last one for each CPU section.
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_ = self.addOne();
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}
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return true;
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}
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fn finalize(self: *ArmCpuinfoImpl, arch: Target.Cpu.Arch) ?Target.Cpu {
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if (self.core_no == 0) return null;
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const is_64bit = switch (arch) {
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.aarch64, .aarch64_be => true,
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else => false,
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};
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var known_models: [num_cores]?*const Target.Cpu.Model = undefined;
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for (self.cores[0..self.core_no], 0..) |core, i| {
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known_models[i] = cpu_models.isKnown(.{
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.architecture = core.architecture,
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.implementer = core.implementer,
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.variant = core.variant,
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.part = core.part,
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}, is_64bit);
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}
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// XXX We pick the first core on big.LITTLE systems, hopefully the
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// LITTLE one.
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const model = known_models[0] orelse return null;
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return Target.Cpu{
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.arch = arch,
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.model = model,
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.features = model.features,
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};
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}
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};
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const ArmCpuinfoParser = CpuinfoParser(ArmCpuinfoImpl);
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test "cpuinfo: ARM" {
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try testParser(ArmCpuinfoParser, .arm, &Target.arm.cpu.arm1176jz_s,
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\\processor : 0
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\\model name : ARMv6-compatible processor rev 7 (v6l)
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\\BogoMIPS : 997.08
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\\Features : half thumb fastmult vfp edsp java tls
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\\CPU implementer : 0x41
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\\CPU architecture: 7
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\\CPU variant : 0x0
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\\CPU part : 0xb76
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\\CPU revision : 7
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);
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try testParser(ArmCpuinfoParser, .arm, &Target.arm.cpu.cortex_a7,
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\\processor : 0
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\\model name : ARMv7 Processor rev 3 (v7l)
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\\BogoMIPS : 18.00
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\\Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae
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\\CPU implementer : 0x41
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\\CPU architecture: 7
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\\CPU variant : 0x0
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\\CPU part : 0xc07
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\\CPU revision : 3
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\\
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\\processor : 4
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\\model name : ARMv7 Processor rev 3 (v7l)
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\\BogoMIPS : 90.00
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\\Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae
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\\CPU implementer : 0x41
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\\CPU architecture: 7
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\\CPU variant : 0x2
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\\CPU part : 0xc0f
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\\CPU revision : 3
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);
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try testParser(ArmCpuinfoParser, .aarch64, &Target.aarch64.cpu.cortex_a72,
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\\processor : 0
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\\BogoMIPS : 108.00
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\\Features : fp asimd evtstrm crc32 cpuid
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\\CPU implementer : 0x41
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\\CPU architecture: 8
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\\CPU variant : 0x0
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\\CPU part : 0xd08
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\\CPU revision : 3
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);
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}
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fn testParser(
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parser: anytype,
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arch: Target.Cpu.Arch,
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expected_model: *const Target.Cpu.Model,
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input: []const u8,
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) !void {
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var r: Io.Reader = .fixed(input);
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const result = try parser.parse(arch, &r);
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try testing.expectEqual(expected_model, result.?.model);
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try testing.expect(expected_model.features.eql(result.?.features));
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}
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// The generic implementation of a /proc/cpuinfo parser.
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// For every line it invokes the line_hook method with the key and value strings
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// as first and second parameters. Returning false from the hook function stops
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// the iteration without raising an error.
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// When all the lines have been analyzed the finalize method is called.
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fn CpuinfoParser(comptime impl: anytype) type {
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return struct {
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fn parse(arch: Target.Cpu.Arch, reader: *Io.Reader) !?Target.Cpu {
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var obj: impl = .{};
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while (try reader.takeDelimiter('\n')) |line| {
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const colon_pos = mem.findScalar(u8, line, ':') orelse continue;
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const key = mem.trimEnd(u8, line[0..colon_pos], " \t");
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const value = mem.trimStart(u8, line[colon_pos + 1 ..], " \t");
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if (!try obj.line_hook(key, value)) break;
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}
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return obj.finalize(arch);
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}
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};
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}
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inline fn getAArch64CpuFeature(comptime feat_reg: []const u8) u64 {
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return asm ("mrs %[ret], " ++ feat_reg
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: [ret] "=r" (-> u64),
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);
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}
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pub fn detectNativeCpuAndFeatures(io: Io) ?Target.Cpu {
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var file = fs.openFileAbsolute("/proc/cpuinfo", .{}) catch |err| switch (err) {
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else => return null,
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};
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defer file.close();
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var buffer: [4096]u8 = undefined; // "flags" lines can get pretty long.
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var file_reader = file.reader(io, &buffer);
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const current_arch = builtin.cpu.arch;
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switch (current_arch) {
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.arm, .armeb, .thumb, .thumbeb => {
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return ArmCpuinfoParser.parse(current_arch, &file_reader.interface) catch null;
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|
},
|
|
.aarch64, .aarch64_be => {
|
|
const registers = [12]u64{
|
|
getAArch64CpuFeature("MIDR_EL1"),
|
|
getAArch64CpuFeature("ID_AA64PFR0_EL1"),
|
|
getAArch64CpuFeature("ID_AA64PFR1_EL1"),
|
|
getAArch64CpuFeature("ID_AA64DFR0_EL1"),
|
|
getAArch64CpuFeature("ID_AA64DFR1_EL1"),
|
|
getAArch64CpuFeature("ID_AA64AFR0_EL1"),
|
|
getAArch64CpuFeature("ID_AA64AFR1_EL1"),
|
|
getAArch64CpuFeature("ID_AA64ISAR0_EL1"),
|
|
getAArch64CpuFeature("ID_AA64ISAR1_EL1"),
|
|
getAArch64CpuFeature("ID_AA64MMFR0_EL1"),
|
|
getAArch64CpuFeature("ID_AA64MMFR1_EL1"),
|
|
getAArch64CpuFeature("ID_AA64MMFR2_EL1"),
|
|
};
|
|
|
|
const core = @import("arm.zig").aarch64.detectNativeCpuAndFeatures(current_arch, registers);
|
|
return core;
|
|
},
|
|
.sparc, .sparc64 => {
|
|
return SparcCpuinfoParser.parse(current_arch, &file_reader.interface) catch null;
|
|
},
|
|
.powerpc, .powerpcle, .powerpc64, .powerpc64le => {
|
|
return PowerpcCpuinfoParser.parse(current_arch, &file_reader.interface) catch null;
|
|
},
|
|
.riscv64, .riscv32 => {
|
|
return RiscvCpuinfoParser.parse(current_arch, &file_reader.interface) catch null;
|
|
},
|
|
.s390x => {
|
|
return S390xCpuinfoParser.parse(current_arch, &file_reader.interface) catch null;
|
|
},
|
|
else => {},
|
|
}
|
|
|
|
return null;
|
|
}
|