Alex Rønne Petersen 5d019abe4e start adding big endian RISC-V support ... The big endian RISC-V effort is mostly driven by MIPS (the company) which is pivoting to RISC-V, and presumably needs a big endian variant to fill the niche that big endian MIPS (the ISA) did. GCC already supports these targets, but LLVM support will only appear in 22; this commit just adds the necessary target knowledge and checks on our end.		2025-08-25 16:15:17 +02:00
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assembly.zig	start adding big endian RISC-V support	2025-08-25 16:15:17 +02:00