std.Target: Remove sparcel architecture tag.

What is `sparcel`, you might ask? Good question!

If you take a peek in the SPARC v8 manual, §2.2, it is quite explicit that SPARC
v8 is a big-endian architecture. No little-endian or mixed-endian support to be
found here.

On the other hand, the SPARC v9 manual, in §3.2.1.2, states that it has support
for mixed-endian operation, with big-endian mode being the default.

Ok, so `sparcel` must just be referring to SPARC v9 running in little-endian
mode, surely?

Nope:

* 40b4fd7a3e/llvm/lib/Target/Sparc/SparcTargetMachine.cpp (L226)
* 40b4fd7a3e/llvm/lib/Target/Sparc/SparcTargetMachine.cpp (L104)

So, `sparcel` in LLVM is referring to some sort of fantastical little-endian
SPARC v8 architecture. I've scoured the internet and I can find absolutely no
evidence that such a thing exists or has ever existed. In fact, I can find no
evidence that a little-endian implementation of SPARC v9 ever existed, either.
Or any SPARC version, actually!

The support was added here: https://reviews.llvm.org/D8741

Notably, there is no mention whatsoever of what CPU this might be referring to,
and no justification given for the "but some are little" comment added in the
patch.

My best guess is that this might have been some private exercise in creating a
little-endian version of SPARC that never saw the light of day. Given that SPARC
v8 explicitly doesn't support little-endian operation (let alone little-endian
instruction encoding!), and no CPU is known to be implemented as such, I think
it's very reasonable for us to just remove this support.

lib/compiler/aro/aro/Compilation.zig

@@ -363,7 +363,7 @@ fn generateSystemDefines(comp: *Compilation, w: anytype) !void {
             \\#define __sparc_v9__ 1
             \\
         ),
-        .sparc, .sparcel => try w.writeAll(
+        .sparc => try w.writeAll(
             \\#define __sparc__ 1
             \\#define __sparc 1
             \\

lib/compiler/aro/aro/Driver/GCCDetector.zig

@@ -376,7 +376,7 @@ fn collectLibDirsAndTriples(
             biarch_libdirs.appendSliceAssumeCapacity(&RISCV32LibDirs);
             biarch_triple_aliases.appendSliceAssumeCapacity(&RISCV32Triples);
         },
-        .sparc, .sparcel => {
+        .sparc => {
             lib_dirs.appendSliceAssumeCapacity(&SPARCv8LibDirs);
             triple_aliases.appendSliceAssumeCapacity(&SPARCv8Triples);
             biarch_libdirs.appendSliceAssumeCapacity(&SPARCv9LibDirs);

lib/compiler/aro/aro/target.zig

@@ -58,7 +58,7 @@ pub fn intPtrType(target: std.Target) Type {
         .avr,
         => return .{ .specifier = .int },
 
-        .sparc, .sparcel => switch (target.os.tag) {
+        .sparc => switch (target.os.tag) {
             .netbsd, .openbsd => {},
             else => return .{ .specifier = .int },
         },
@@ -132,7 +132,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u8 {
     return switch (target.cpu.arch) {
         .arm, .armeb => 4,
         .aarch64, .aarch64_be => 4,
-        .sparc, .sparcel, .sparc64 => 4,
+        .sparc, .sparc64 => 4,
         .riscv64 => 2,
         else => 1,
     };
@@ -426,7 +426,7 @@ pub fn ldEmulationOption(target: std.Target, arm_endianness: ?std.builtin.Endian
         .powerpc64le => "elf64lppc",
         .riscv32 => "elf32lriscv",
         .riscv64 => "elf64lriscv",
-        .sparc, .sparcel => "elf32_sparc",
+        .sparc => "elf32_sparc",
         .sparc64 => "elf64_sparc",
         .loongarch32 => "elf32loongarch",
         .loongarch64 => "elf64loongarch",
@@ -466,7 +466,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
         .powerpcle,
         .riscv32,
         .sparc,
-        .sparcel,
         .thumb,
         .thumbeb,
         .x86,
@@ -510,7 +509,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
         .lanai,
         .m68k,
         .msp430,
-        .sparcel,
         .spu_2,
         .xcore,
         .xtensa,
@@ -592,7 +590,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
         .riscv64 => "riscv64",
         .sparc => "sparc",
         .sparc64 => "sparc64",
-        .sparcel => "sparcel",
         .s390x => "s390x",
         .thumb => "thumb",
         .thumbeb => "thumbeb",

lib/compiler/aro/aro/toolchains/Linux.zig

@@ -357,7 +357,6 @@ fn getOSLibDir(target: std.Target) []const u8 {
         .powerpc,
         .powerpcle,
         .sparc,
-        .sparcel,
         => return "lib32",
         else => {},
     }

lib/compiler_rt/atomics.zig

@@ -30,7 +30,7 @@ const largest_atomic_size = switch (arch) {
     // On SPARC systems that lacks CAS and/or swap instructions, the only
     // available atomic operation is a test-and-set (`ldstub`), so we force
     // every atomic memory access to go through the lock.
-    .sparc, .sparcel => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
+    .sparc => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
 
     // XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b
     // and set this parameter accordingly.

lib/compiler_rt/clear_cache.zig

@@ -41,7 +41,7 @@ fn clear_cache(start: usize, end: usize) callconv(.C) void {
         else => false,
     };
     const sparc = switch (arch) {
-        .sparc, .sparc64, .sparcel => true,
+        .sparc, .sparc64 => true,
         else => false,
     };
     const apple = switch (os) {

lib/std/Target.zig

@@ -201,7 +201,7 @@ pub const Os = struct {
                     .mips, .mipsel, .mips64, .mips64el => "mips",
                     .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
                     .riscv32, .riscv64 => "riscv",
-                    .sparc, .sparcel, .sparc64 => "sparc",
+                    .sparc, .sparc64 => "sparc",
                     .x86, .x86_64 => "x86",
                     else => @tagName(arch),
                 },
@@ -1017,7 +1017,6 @@ pub const Cpu = struct {
         riscv64,
         sparc,
         sparc64,
-        sparcel,
         s390x,
         thumb,
         thumbeb,
@@ -1040,6 +1039,7 @@ pub const Cpu = struct {
         // LLVM tags deliberately omitted:
         // - aarch64_32
         // - r600
+        // - sparcel
         // - le32
         // - le64
         // - amdil
@@ -1121,7 +1121,7 @@ pub const Cpu = struct {
 
         pub inline fn isSPARC(arch: Arch) bool {
             return switch (arch) {
-                .sparc, .sparcel, .sparc64 => true,
+                .sparc, .sparc64 => true,
                 else => false,
             };
         }
@@ -1171,7 +1171,6 @@ pub const Cpu = struct {
                 .powerpc, .powerpcle => .PPC,
                 .riscv32 => .RISCV,
                 .sparc => .SPARC,
-                .sparcel => .SPARC,
                 .thumb => .ARM,
                 .thumbeb => .ARM,
                 .x86 => .@"386",
@@ -1222,7 +1221,6 @@ pub const Cpu = struct {
                 .powerpc, .powerpcle => .POWERPC,
                 .riscv32 => .RISCV32,
                 .sparc => .Unknown,
-                .sparcel => .Unknown,
                 .thumb => .Thumb,
                 .thumbeb => .Thumb,
                 .x86 => .I386,
@@ -1274,7 +1272,6 @@ pub const Cpu = struct {
                 .msp430,
                 .nvptx,
                 .nvptx64,
-                .sparcel,
                 .powerpcle,
                 .powerpc64le,
                 .riscv32,
@@ -1341,7 +1338,7 @@ pub const Cpu = struct {
                 .powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
                 .amdgcn => "amdgpu",
                 .riscv32, .riscv64 => "riscv",
-                .sparc, .sparc64, .sparcel => "sparc",
+                .sparc, .sparc64 => "sparc",
                 .s390x => "s390x",
                 .x86, .x86_64 => "x86",
                 .nvptx, .nvptx64 => "nvptx",
@@ -1368,7 +1365,7 @@ pub const Cpu = struct {
                 .powerpc, .powerpcle, .powerpc64, .powerpc64le => &powerpc.all_features,
                 .amdgcn => &amdgpu.all_features,
                 .riscv32, .riscv64 => &riscv.all_features,
-                .sparc, .sparc64, .sparcel => &sparc.all_features,
+                .sparc, .sparc64 => &sparc.all_features,
                 .spirv32, .spirv64 => &spirv.all_features,
                 .s390x => &s390x.all_features,
                 .x86, .x86_64 => &x86.all_features,
@@ -1398,7 +1395,7 @@ pub const Cpu = struct {
                 .powerpc, .powerpcle, .powerpc64, .powerpc64le => comptime allCpusFromDecls(powerpc.cpu),
                 .amdgcn => comptime allCpusFromDecls(amdgpu.cpu),
                 .riscv32, .riscv64 => comptime allCpusFromDecls(riscv.cpu),
-                .sparc, .sparc64, .sparcel => comptime allCpusFromDecls(sparc.cpu),
+                .sparc, .sparc64 => comptime allCpusFromDecls(sparc.cpu),
                 .spirv32, .spirv64 => comptime allCpusFromDecls(spirv.cpu),
                 .s390x => comptime allCpusFromDecls(s390x.cpu),
                 .x86, .x86_64 => comptime allCpusFromDecls(x86.cpu),
@@ -1490,7 +1487,7 @@ pub const Cpu = struct {
                 .riscv32 => &riscv.cpu.generic_rv32,
                 .riscv64 => &riscv.cpu.generic_rv64,
                 .spirv32, .spirv64 => &spirv.cpu.generic,
-                .sparc, .sparcel => &sparc.cpu.generic,
+                .sparc => &sparc.cpu.generic,
                 .sparc64 => &sparc.cpu.v9, // 64-bit SPARC needs v9 as the baseline
                 .s390x => &s390x.cpu.generic,
                 .x86 => &x86.cpu.i386,
@@ -1511,7 +1508,7 @@ pub const Cpu = struct {
                 .x86 => &x86.cpu.pentium4,
                 .nvptx, .nvptx64 => &nvptx.cpu.sm_20,
                 .s390x => &s390x.cpu.arch8,
-                .sparc, .sparcel => &sparc.cpu.v8,
+                .sparc => &sparc.cpu.v8,
                 .loongarch64 => &loongarch.cpu.loongarch64,
 
                 else => generic(arch),
@@ -1696,7 +1693,6 @@ pub const DynamicLinker = struct {
             .linux => switch (cpu.arch) {
                 .x86,
                 .sparc,
-                .sparcel,
                 => init("/lib/ld-linux.so.2"),
 
                 .aarch64 => init("/lib/ld-linux-aarch64.so.1"),
@@ -1854,7 +1850,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
         .powerpc,
         .powerpcle,
         .riscv32,
-        .sparcel,
         .thumb,
         .thumbeb,
         .x86,
@@ -1914,7 +1909,6 @@ pub fn stackAlignment(target: Target) u16 {
         .mips,
         .mipsel,
         .sparc,
-        .sparcel,
         => 8,
         .aarch64,
         .aarch64_be,
@@ -2075,7 +2069,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
                     .s390x,
                     .sparc,
                     .sparc64,
-                    .sparcel,
                     .wasm32,
                     .wasm64,
                     => return 128,
@@ -2180,7 +2173,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
                     .mips64el,
                     .sparc,
                     .sparc64,
-                    .sparcel,
                     .wasm32,
                     .wasm64,
                     => return 128,
@@ -2374,7 +2366,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
             .mips,
             .mipsel,
             .sparc,
-            .sparcel,
             .sparc64,
             .lanai,
             .nvptx,
@@ -2487,7 +2478,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
             .mips,
             .mipsel,
             .sparc,
-            .sparcel,
             .sparc64,
             .lanai,
             .nvptx,

lib/std/atomic.zig

@@ -486,7 +486,6 @@ pub const cache_line = switch (builtin.cpu.arch) {
     .riscv32,
     .riscv64,
     .sparc,
-    .sparcel,
     .sparc64,
     => 32,
 

lib/std/builtin.zig

@@ -615,7 +615,7 @@ pub const VaList = switch (builtin.cpu.arch) {
         else => VaListPowerPc,
     },
     .powerpc64, .powerpc64le => *u8,
-    .sparc, .sparcel, .sparc64 => *anyopaque,
+    .sparc, .sparc64 => *anyopaque,
     .spirv32, .spirv64 => *anyopaque,
     .s390x => VaListS390x,
     .wasm32, .wasm64 => *anyopaque,

lib/std/c.zig

@@ -5779,7 +5779,7 @@ pub const ucontext_t = switch (native_os) {
                 .x86 => 4,
                 .mips, .mipsel, .mips64, .mips64el => 14,
                 .arm, .armeb, .thumb, .thumbeb => 1,
-                .sparc, .sparcel, .sparc64 => if (@sizeOf(usize) == 4) 43 else 8,
+                .sparc, .sparc64 => if (@sizeOf(usize) == 4) 43 else 8,
                 else => 0,
             }
         ]u32,
@@ -6821,7 +6821,7 @@ pub const pthread_key_t = switch (native_os) {
 pub const padded_pthread_spin_t = switch (native_os) {
     .netbsd => switch (builtin.cpu.arch) {
         .x86, .x86_64 => u32,
-        .sparc, .sparcel, .sparc64 => u32,
+        .sparc, .sparc64 => u32,
         else => pthread_spin_t,
     },
     else => void,
@@ -6834,7 +6834,7 @@ pub const pthread_spin_t = switch (native_os) {
         .powerpc, .powerpc64, .powerpc64le => i32,
         .x86, .x86_64 => u8,
         .arm, .armeb, .thumb, .thumbeb => i32,
-        .sparc, .sparcel, .sparc64 => u8,
+        .sparc, .sparc64 => u8,
         .riscv32, .riscv64 => u32,
         else => @compileError("undefined pthread_spin_t for this arch"),
     },

lib/std/os/linux.zig

@@ -2485,7 +2485,7 @@ pub const E = switch (native_arch) {
 
         pub const init = errnoFromSyscall;
     },
-    .sparc, .sparcel, .sparc64 => enum(u16) {
+    .sparc, .sparc64 => enum(u16) {
         /// No error occurred.
         SUCCESS = 0,
 
@@ -4832,7 +4832,6 @@ pub const MINSIGSTKSZ = switch (native_arch) {
     => 2048,
     .loongarch64,
     .sparc,
-    .sparcel,
     .sparc64,
     => 4096,
     .aarch64,
@@ -4869,7 +4868,6 @@ pub const SIGSTKSZ = switch (native_arch) {
     .aarch64_be,
     .loongarch64,
     .sparc,
-    .sparcel,
     .sparc64,
     => 16384,
     .powerpc64,

lib/std/os/linux/ioctl.zig

@@ -11,7 +11,6 @@ const bits = switch (@import("builtin").cpu.arch) {
     .powerpc64le,
     .sparc,
     .sparc64,
-    .sparcel,
     => .{ .size = 13, .dir = 3, .none = 1, .read = 2, .write = 4 },
     else => .{ .size = 14, .dir = 2, .none = 0, .read = 2, .write = 1 },
 };

src/Type.zig

@@ -1602,7 +1602,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
         .amdgcn,
         .riscv32,
         .sparc,
-        .sparcel,
         .s390x,
         .lanai,
         .wasm32,

src/Zcu.zig

@@ -3248,7 +3248,6 @@ pub fn atomicPtrAlignment(
         .powerpcle,
         .riscv32,
         .sparc,
-        .sparcel,
         .thumb,
         .thumbeb,
         .x86,

src/codegen/llvm.zig

@@ -69,7 +69,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
         .riscv64 => "riscv64",
         .sparc => "sparc",
         .sparc64 => "sparc64",
-        .sparcel => "sparcel",
         .s390x => "s390x",
         .thumb => "thumb",
         .thumbeb => "thumbeb",
@@ -280,7 +279,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
         .riscv64 => .riscv64,
         .sparc => .sparc,
         .sparc64 => .sparcv9, // In LLVM, sparc64 == sparcv9.
-        .sparcel => .sparcel,
         .s390x => .systemz,
         .thumb => .thumb,
         .thumbeb => .thumbeb,
@@ -469,7 +467,6 @@ const DataLayoutBuilder = struct {
             .powerpcle,
             .riscv32,
             .sparc,
-            .sparcel,
             .thumb,
             .thumbeb,
             .xtensa,
@@ -12004,7 +12001,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
             llvm.LLVMInitializeRISCVAsmPrinter();
             llvm.LLVMInitializeRISCVAsmParser();
         },
-        .sparc, .sparc64, .sparcel => {
+        .sparc, .sparc64 => {
             llvm.LLVMInitializeSparcTarget();
             llvm.LLVMInitializeSparcTargetInfo();
             llvm.LLVMInitializeSparcTargetMC();

src/glibc.zig

@@ -394,7 +394,7 @@ fn start_asm_path(comp: *Compilation, arena: Allocator, basename: []const u8) ![
     const arch = comp.getTarget().cpu.arch;
     const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le;
     const is_aarch64 = arch == .aarch64 or arch == .aarch64_be;
-    const is_sparc = arch == .sparc or arch == .sparcel or arch == .sparc64;
+    const is_sparc = arch == .sparc or arch == .sparc64;
     const is_64 = comp.getTarget().ptrBitWidth() == 64;
 
     const s = path.sep_str;
@@ -532,7 +532,7 @@ fn add_include_dirs_arch(
     const is_x86 = arch == .x86 or arch == .x86_64;
     const is_aarch64 = arch == .aarch64 or arch == .aarch64_be;
     const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le;
-    const is_sparc = arch == .sparc or arch == .sparcel or arch == .sparc64;
+    const is_sparc = arch == .sparc or arch == .sparc64;
     const is_64 = target.ptrBitWidth() == 64;
 
     const s = path.sep_str;

src/link/Elf.zig

@@ -5175,7 +5175,7 @@ fn getLDMOption(target: std.Target) ?[]const u8 {
         .powerpc => return "elf32ppclinux",
         .powerpc64 => return "elf64ppc",
         .powerpc64le => return "elf64lppc",
-        .sparc, .sparcel => return "elf32_sparc",
+        .sparc => return "elf32_sparc",
         .sparc64 => return "elf64_sparc",
         .mips => return "elf32btsmip",
         .mipsel => return "elf32ltsmip",

src/link/Plan9/aout.zig

@@ -110,7 +110,7 @@ pub const R_MAGIC = _MAGIC(HDR_MAGIC, 28); // arm64
 pub fn magicFromArch(arch: std.Target.Cpu.Arch) !u32 {
     return switch (arch) {
         .x86 => I_MAGIC,
-        .sparc => K_MAGIC, // TODO should sparc64 and sparcel go here?
+        .sparc => K_MAGIC, // TODO should sparc64 go here?
         .mips => V_MAGIC,
         .arm => E_MAGIC,
         .aarch64 => R_MAGIC,

src/target.zig

@@ -138,7 +138,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
         .riscv64,
         .sparc,
         .sparc64,
-        .sparcel,
         .s390x,
         .thumb,
         .thumbeb,
@@ -408,7 +407,7 @@ pub fn defaultFunctionAlignment(target: std.Target) Alignment {
     return switch (target.cpu.arch) {
         .arm, .armeb => .@"4",
         .aarch64, .aarch64_be => .@"4",
-        .sparc, .sparcel, .sparc64 => .@"4",
+        .sparc, .sparc64 => .@"4",
         .riscv64 => .@"2",
         else => .@"1",
     };
@@ -423,7 +422,6 @@ pub fn minFunctionAlignment(target: std.Target) Alignment {
         .riscv32,
         .riscv64,
         .sparc,
-        .sparcel,
         .sparc64,
         => .@"2",
         else => .@"1",

test/behavior/align.zig

@@ -95,7 +95,6 @@ test "alignment and size of structs with 128-bit fields" {
         .amdgcn,
         .riscv32,
         .sparc,
-        .sparcel,
         .s390x,
         .lanai,
         .wasm32,

test/llvm_targets.zig

@@ -87,8 +87,6 @@ const targets = [_]std.Target.Query{
     .{ .cpu_arch = .sparc, .os_tag = .freestanding, .abi = .none },
     .{ .cpu_arch = .sparc, .os_tag = .linux, .abi = .gnu },
     .{ .cpu_arch = .sparc, .os_tag = .linux, .abi = .none },
-    .{ .cpu_arch = .sparcel, .os_tag = .freestanding, .abi = .none },
-    .{ .cpu_arch = .sparcel, .os_tag = .linux, .abi = .gnu },
     .{ .cpu_arch = .sparc64, .os_tag = .freestanding, .abi = .none },
     .{ .cpu_arch = .sparc64, .os_tag = .linux, .abi = .gnu },
     //.{ .cpu_arch = .spirv32, .os_tag = .opencl, .abi = .none },