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1311e997d4
This excludes all headers in /usr/include/dev because that directory is bonkers huge (18M). We can add these on an as-needed basis.
226 lines
No EOL
7.4 KiB
C
Vendored
226 lines
No EOL
7.4 KiB
C
Vendored
/* $OpenBSD: intr.h,v 1.25 2025/06/30 14:19:20 kettenis Exp $ */
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/*
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* Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef _MACHINE_INTR_H_
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#define _MACHINE_INTR_H_
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/*
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* The interrupt level ipl is a logical level; per-platform interrupt
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* code will turn it into the appropriate hardware interrupt masks
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* values.
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*
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* Interrupt sources on the CPU are kept enabled regardless of the
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* current ipl value; individual hardware sources interrupting while
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* logically masked are masked on the fly, remembered as pending, and
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* unmasked at the first splx() opportunity.
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*/
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#ifdef _KERNEL
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/* Interrupt priority `levels'; not mutually exclusive. */
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#define IPL_NONE 0 /* nothing */
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#define IPL_SOFTCLOCK 2 /* soft clock interrupts */
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#define IPL_SOFTNET 3 /* soft network interrupts */
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#define IPL_SOFTTTY 4 /* soft terminal interrupts */
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#define IPL_BIO 5 /* block I/O */
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#define IPL_NET 6 /* network */
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#define IPL_TTY 7 /* terminal */
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#define IPL_VM 8 /* memory allocation */
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#define IPL_AUDIO 9 /* audio */
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#define IPL_CLOCK 10 /* clock */
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#define IPL_SCHED IPL_CLOCK
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#define IPL_STATCLOCK IPL_CLOCK
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#define IPL_HIGH 11 /* everything */
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#define IPL_IPI 12 /* interprocessor interrupt */
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#define NIPL 13 /* number of levels */
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#define IPL_MPFLOOR IPL_TTY
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/* Interrupt priority 'flags'. */
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#define IPL_IRQMASK 0xf /* priority only */
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#define IPL_FLAGMASK 0xf00 /* flags only*/
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#define IPL_MPSAFE 0x100 /* 'mpsafe' interrupt, no kernel lock */
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#define IPL_WAKEUP 0x200 /* 'wakeup' interrupt */
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/* Interrupt sharing types. */
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#define IST_NONE 0 /* none */
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#define IST_PULSE 1 /* pulsed */
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#define IST_EDGE 2 /* edge-triggered */
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#define IST_LEVEL 3 /* level-triggered */
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#define IST_LEVEL_LOW IST_LEVEL
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#define IST_LEVEL_HIGH 4
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#define IST_EDGE_FALLING IST_EDGE
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#define IST_EDGE_RISING 5
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#define IST_EDGE_BOTH 6
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#define __USE_MI_SOFTINTR
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#include <sys/softintr.h>
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#ifndef _LOCORE
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#include <sys/queue.h>
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void softintr(int);
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int splraise(int);
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int spllower(int);
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void splx(int);
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void arm_do_pending_intr(int);
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void arm_set_intr_handler(int (*)(int), int (*)(int), void (*)(int),
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void (*)(int), void (*)(void *), void (*)(void *),
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void (*)(void), void (*)(void));
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struct machine_intr_handle {
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struct interrupt_controller *ih_ic;
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void *ih_ih;
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};
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struct arm_intr_func {
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int (*raise)(int);
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int (*lower)(int);
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void (*x)(int);
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void (*setipl)(int);
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void (*enable_wakeup)(void);
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void (*disable_wakeup)(void);
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};
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extern struct arm_intr_func arm_intr_func;
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#define splraise(cpl) (arm_intr_func.raise(cpl))
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#define _splraise(cpl) (arm_intr_func.raise(cpl))
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#define spllower(cpl) (arm_intr_func.lower(cpl))
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#define splx(cpl) (arm_intr_func.x(cpl))
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#define splsoftclock() splraise(IPL_SOFTCLOCK)
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#define splsoftnet() splraise(IPL_SOFTNET)
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#define splsofttty() splraise(IPL_SOFTTTY)
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#define splbio() splraise(IPL_BIO)
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#define splnet() splraise(IPL_NET)
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#define spltty() splraise(IPL_TTY)
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#define splvm() splraise(IPL_VM)
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#define splaudio() splraise(IPL_AUDIO)
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#define splclock() splraise(IPL_CLOCK)
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#define splsched() splraise(IPL_SCHED)
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#define splstatclock() splraise(IPL_STATCLOCK)
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#define splhigh() splraise(IPL_HIGH)
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#define spl0() spllower(IPL_NONE)
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void intr_barrier(void *);
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void intr_set_wakeup(void *);
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void intr_enable_wakeup(void);
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void intr_disable_wakeup(void);
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void arm_init_smask(void); /* XXX */
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extern uint32_t arm_smask[NIPL];
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/* XXX - this is probably the wrong location for this */
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void arm_clock_register(void (*)(void), void (*)(u_int), void (*)(int),
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void (*)(void));
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struct cpu_info;
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struct interrupt_controller {
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int ic_node;
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void *ic_cookie;
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void *(*ic_establish)(void *, int *, int, struct cpu_info *,
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int (*)(void *), void *, char *);
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void *(*ic_establish_msi)(void *, uint64_t *, uint64_t *, int,
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struct cpu_info *, int (*)(void *), void *, char *);
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void (*ic_disestablish)(void *);
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void (*ic_enable)(void *);
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void (*ic_disable)(void *);
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void (*ic_route)(void *, int, struct cpu_info *);
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void (*ic_cpu_enable)(void);
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void (*ic_barrier)(void *);
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void (*ic_set_wakeup)(void *);
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LIST_ENTRY(interrupt_controller) ic_list;
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uint32_t ic_phandle;
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uint32_t ic_cells;
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uint32_t ic_gic_its_id;
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};
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void arm_intr_init_fdt(void);
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void arm_intr_register_fdt(struct interrupt_controller *);
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void *arm_intr_establish_fdt(int, int, int (*)(void *),
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void *, char *);
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void *arm_intr_establish_fdt_cpu(int, int, struct cpu_info *,
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int (*)(void *), void *, char *);
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void *arm_intr_establish_fdt_idx(int, int, int, int (*)(void *),
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void *, char *);
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void *arm_intr_establish_fdt_idx_cpu(int, int, int, struct cpu_info *,
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int (*)(void *), void *, char *);
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void *arm_intr_establish_fdt_imap(int, int *, int, int, int (*)(void *),
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void *, char *);
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void *arm_intr_establish_fdt_imap_cpu(int, int *, int, int,
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struct cpu_info *, int (*)(void *), void *, char *);
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void *arm_intr_establish_fdt_msi(int, uint64_t *, uint64_t *, int,
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int (*)(void *), void *, char *);
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void *arm_intr_establish_fdt_msi_cpu(int, uint64_t *, uint64_t *, int,
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struct cpu_info *, int (*)(void *), void *, char *);
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void arm_intr_disestablish_fdt(void *);
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void arm_intr_enable(void *);
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void arm_intr_disable(void *);
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void arm_intr_route(void *, int, struct cpu_info *);
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void arm_intr_cpu_enable(void);
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void *arm_intr_parent_establish_fdt(void *, int *, int,
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struct cpu_info *ci, int (*)(void *), void *, char *);
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void arm_intr_parent_disestablish_fdt(void *);
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void arm_send_ipi(struct cpu_info *, int);
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extern void (*intr_send_ipi_func)(struct cpu_info *, int);
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#define ARM_IPI_NOP 0
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#define ARM_IPI_DDB 1
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#define ARM_IPI_HALT 2
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#ifdef DIAGNOSTIC
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/*
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* Although this function is implemented in MI code, it must be in this MD
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* header because we don't want this header to include MI includes.
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*/
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void splassert_fail(int, int, const char *);
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extern int splassert_ctl;
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void arm_splassert_check(int, const char *);
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#define splassert(__wantipl) do { \
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if (splassert_ctl > 0) { \
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arm_splassert_check(__wantipl, __func__); \
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} \
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} while (0)
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#define splsoftassert(wantipl) splassert(wantipl)
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#else
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#define splassert(wantipl) do { /* nothing */ } while (0)
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#define splsoftassert(wantipl) do { /* nothing */ } while (0)
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#endif
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#endif /* ! _LOCORE */
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#endif /* _KERNEL */
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#endif /* _MACHINE_INTR_H_ */ |