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libc: add openbsd 7.8 headers

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This excludes all headers in /usr/include/dev because that directory is bonkers
huge (18M). We can add these on an as-needed basis.
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Alex Rønne Petersen 2025-11-30 22:16:15 +01:00
parent 154ad83ea4
commit 1311e997d4
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96
lib/libc/include/aarch64-openbsd-none/arm64/_float.h vendored Normal file
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/* $OpenBSD: _float.h,v 1.1 2016/12/17 23:38:33 patrick Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE__FLOAT_H_
#define _MACHINE__FLOAT_H_
#define __FLT_RADIX 2 /* b */
#define __FLT_ROUNDS __flt_rounds()
#define __FLT_EVAL_METHOD 0 /* no promotions */
#define __FLT_MANT_DIG 24 /* p */
#define __FLT_EPSILON 1.19209290E-7F /* b**(1-p) */
#define __FLT_DIG 6 /* floor((p-1)*log10(b))+(b == 10) */
#define __FLT_MIN_EXP (-125) /* emin */
#define __FLT_MIN 1.17549435E-38F /* b**(emin-1) */
#define __FLT_MIN_10_EXP (-37) /* ceil(log10(b**(emin-1))) */
#define __FLT_MAX_EXP 128 /* emax */
#define __FLT_MAX 3.40282347E+38F /* (1-b**(-p))*b**emax */
#define __FLT_MAX_10_EXP 38 /* floor(log10((1-b**(-p))*b**emax)) */
#define __DBL_MANT_DIG 53
#define __DBL_EPSILON 2.2204460492503131E-16
#define __DBL_DIG 15
#define __DBL_MIN_EXP (-1021)
#define __DBL_MIN 2.2250738585072014E-308
#define __DBL_MIN_10_EXP (-307)
#define __DBL_MAX_EXP 1024
#define __DBL_MAX 1.7976931348623157E+308
#define __DBL_MAX_10_EXP 308
#ifdef __LDBL_MANT_DIG__
#define __LDBL_MANT_DIG __LDBL_MANT_DIG__
#define __LDBL_EPSILON __LDBL_EPSILON__
#define __LDBL_DIG __LDBL_DIG__
#define __LDBL_MIN_EXP __LDBL_MIN_EXP__
#define __LDBL_MIN __LDBL_MIN__
#define __LDBL_MIN_10_EXP __LDBL_MIN_10_EXP__
#define __LDBL_MAX_EXP __LDBL_MAX_EXP__
#define __LDBL_MAX __LDBL_MAX__
#define __LDBL_MAX_10_EXP __LDBL_MAX_10_EXP__
#else
#define __LDBL_MANT_DIG DBL_MANT_DIG
#define __LDBL_EPSILON DBL_EPSILON
#define __LDBL_DIG DBL_DIG
#define __LDBL_MIN_EXP DBL_MIN_EXP
#define __LDBL_MIN DBL_MIN
#define __LDBL_MIN_10_EXP DBL_MIN_10_EXP
#define __LDBL_MAX_EXP DBL_MAX_EXP
#define __LDBL_MAX DBL_MAX
#define __LDBL_MAX_10_EXP DBL_MAX_10_EXP
#endif
#define __DECIMAL_DIG 17
#endif /* _MACHINE__FLOAT_H_ */

145
lib/libc/include/aarch64-openbsd-none/arm64/_types.h vendored Normal file
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/* $OpenBSD: _types.h,v 1.6 2023/07/02 19:02:27 cheloha Exp $ */
/*-
* Copyright (c) 1990, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)types.h 8.3 (Berkeley) 1/5/94
* @(#)ansi.h 8.2 (Berkeley) 1/4/94
*/
#ifndef _MACHINE__TYPES_H_
#define _MACHINE__TYPES_H_
#if defined(_KERNEL)
typedef struct label_t {
long val[13];
} label_t;
#endif
/*
* _ALIGN(p) rounds p (pointer or byte index) up to a correctly-aligned
* value for all data types (int, long, ...). The result is an
* unsigned long and must be cast to any desired pointer type.
*
* _ALIGNED_POINTER is a boolean macro that checks whether an address
* is valid to fetch data elements of type t from on this architecture.
* This does not reflect the optimal alignment, just the possibility
* (within reasonable limits).
*/
#define _ALIGNBYTES (sizeof(long) - 1)
#define _STACKALIGNBYTES 15
#define _ALIGN(p) (((unsigned long)(p) + _ALIGNBYTES) & ~_ALIGNBYTES)
#define _ALIGNED_POINTER(p,t) ((((unsigned long)(p)) & (sizeof(t) - 1)) == 0)
#define _MAX_PAGE_SHIFT 12 /* same as PAGE_SHIFT */
/* 7.18.1.1 Exact-width integer types */
typedef signed char __int8_t;
typedef unsigned char __uint8_t;
typedef short __int16_t;
typedef unsigned short __uint16_t;
typedef int __int32_t;
typedef unsigned int __uint32_t;
/* LONGLONG */
typedef long long __int64_t;
/* LONGLONG */
typedef unsigned long long __uint64_t;
/* 7.18.1.2 Minimum-width integer types */
typedef __int8_t __int_least8_t;
typedef __uint8_t __uint_least8_t;
typedef __int16_t __int_least16_t;
typedef __uint16_t __uint_least16_t;
typedef __int32_t __int_least32_t;
typedef __uint32_t __uint_least32_t;
typedef __int64_t __int_least64_t;
typedef __uint64_t __uint_least64_t;
/* 7.18.1.3 Fastest minimum-width integer types */
typedef __int32_t __int_fast8_t;
typedef __uint32_t __uint_fast8_t;
typedef __int32_t __int_fast16_t;
typedef __uint32_t __uint_fast16_t;
typedef __int32_t __int_fast32_t;
typedef __uint32_t __uint_fast32_t;
typedef __int64_t __int_fast64_t;
typedef __uint64_t __uint_fast64_t;
#define __INT_FAST8_MIN INT32_MIN
#define __INT_FAST16_MIN INT32_MIN
#define __INT_FAST32_MIN INT32_MIN
#define __INT_FAST64_MIN INT64_MIN
#define __INT_FAST8_MAX INT32_MAX
#define __INT_FAST16_MAX INT32_MAX
#define __INT_FAST32_MAX INT32_MAX
#define __INT_FAST64_MAX INT64_MAX
#define __UINT_FAST8_MAX UINT32_MAX
#define __UINT_FAST16_MAX UINT32_MAX
#define __UINT_FAST32_MAX UINT32_MAX
#define __UINT_FAST64_MAX UINT64_MAX
/* 7.18.1.4 Integer types capable of holding object pointers */
typedef long __intptr_t;
typedef unsigned long __uintptr_t;
/* 7.18.1.5 Greatest-width integer types */
typedef __int64_t __intmax_t;
typedef __uint64_t __uintmax_t;
/* Register size */
typedef long __register_t;
/* VM system types */
typedef unsigned long __vaddr_t;
typedef unsigned long __paddr_t;
typedef unsigned long __vsize_t;
typedef unsigned long __psize_t;
/* Standard system types */
typedef double __double_t;
typedef float __float_t;
typedef long __ptrdiff_t;
typedef unsigned long __size_t;
typedef long __ssize_t;
#if defined(__GNUC__) && __GNUC__ >= 3
typedef __builtin_va_list __va_list;
#else
typedef char * __va_list;
#endif
/* Wide character support types */
#ifndef __cplusplus
#ifdef __WCHAR_UNSIGNED__
typedef unsigned int __wchar_t;
#else
typedef int __wchar_t;
#endif
#endif
typedef int __wint_t;
typedef int __rune_t;
typedef void * __wctrans_t;
typedef void * __wctype_t;
#endif /* _MACHINE__TYPES_H_ */

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lib/libc/include/aarch64-openbsd-none/arm64/acpiapm.h vendored Normal file
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/* $OpenBSD: acpiapm.h,v 1.1 2019/01/23 09:57:36 phessler Exp $ */
/*
* Copyright (c) 2007 Ted Unangst <tedu@openbsd.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
extern int (*acpiapm_open)(dev_t, int, int, struct proc *);
extern int (*acpiapm_close)(dev_t, int, int, struct proc *);
extern int (*acpiapm_ioctl)(dev_t, u_long, caddr_t, int, struct proc *);
extern int (*acpiapm_kqfilter)(dev_t, struct knote *);

127
lib/libc/include/aarch64-openbsd-none/arm64/apmvar.h vendored Normal file
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/* $OpenBSD: apmvar.h,v 1.3 2023/01/22 13:14:21 kettenis Exp $ */
/*
* Copyright (c) 2001 Alexander Guy
* Copyright (c) 1995 John T. Kohl
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR `AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _MACHINE_APMVAR_H_
#define _MACHINE_APMVAR_H_
#include <sys/ioccom.h>
/* Advanced Power Management (v1.0 and v1.1 specification)
* functions/defines/etc.
*/
/* These definitions make up the heart of the user-land interface
* to the APM devices.
*/
#define APM_AC_OFF 0x00
#define APM_AC_ON 0x01
#define APM_AC_BACKUP 0x02
#define APM_AC_UNKNOWN 0xff
#define APM_BATT_HIGH 0x00
#define APM_BATT_LOW 0x01
#define APM_BATT_CRITICAL 0x02
#define APM_BATT_CHARGING 0x03
#define APM_BATT_UNKNOWN 0xff
#define APM_BATT_LIFE_UNKNOWN 0xff
#define APM_NOEVENT 0x0000
#define APM_STANDBY_REQ 0x0001
#define APM_SUSPEND_REQ 0x0002
#define APM_NORMAL_RESUME 0x0003
#define APM_CRIT_RESUME 0x0004 /* suspend/resume happened
without us */
#define APM_BATTERY_LOW 0x0005
#define APM_POWER_CHANGE 0x0006
#define APM_UPDATE_TIME 0x0007
#define APM_CRIT_SUSPEND_REQ 0x0008
#define APM_USER_STANDBY_REQ 0x0009
#define APM_USER_SUSPEND_REQ 0x000A
#define APM_SYS_STANDBY_RESUME 0x000B
#define APM_CAPABILITY_CHANGE 0x000C /* apm v1.2 */
#define APM_USER_HIBERNATE_REQ 0x000D
#define APM_EVENT_MASK 0xffff
#define APM_EVENT_COMPOSE(t,i) ((((i) & 0x7fff) << 16)|((t) & APM_EVENT_MASK))
#define APM_EVENT_TYPE(e) ((e) & APM_EVENT_MASK)
#define APM_EVENT_INDEX(e) ((e) >> 16)
/*
* LP (Laptop Package)
*
* Copyright (C) 1994 by HOSOKAWA Tatsumi <hosokawa@mt.cs.keio.ac.jp>
*
* This software may be used, modified, copied, and distributed, in
* both source and binary form provided that the above copyright and
* these terms are retained. Under no circumstances is the author
* responsible for the proper functioning of this software, nor does
* the author assume any responsibility for damages incurred with its
* use.
*
* Sep., 1994 Implemented on FreeBSD 1.1.5.1R (Toshiba AVS001WD)
*/
#define APM_BATTERY_ABSENT 4
struct apm_power_info {
u_char battery_state;
u_char ac_state;
u_char battery_life;
u_char spare1;
u_int minutes_left; /* estimate */
u_int spare2[6];
};
struct apm_ctl {
u_int dev;
u_int mode;
};
#define APM_IOC_REJECT _IOW('A', 0, struct apm_event_info) /* reject request # */
#define APM_IOC_STANDBY _IO('A', 1) /* put system into standby */
#define APM_IOC_SUSPEND _IO('A', 2) /* put system into suspend */
#define APM_IOC_GETPOWER _IOR('A', 3, struct apm_power_info) /* fetch battery state */
#define APM_IOC_DEV_CTL _IOW('A', 5, struct apm_ctl) /* put device into mode */
#define APM_IOC_PRN_CTL _IOW('A', 6, int ) /* driver power status msg */
#define APM_PRINT_ON 0 /* driver power status displayed */
#define APM_PRINT_OFF 1 /* driver power status not displayed */
#define APM_PRINT_PCT 2 /* driver power status only displayed
if the percentage changes */
#define APM_IOC_STANDBY_REQ _IO('A', 7) /* request standby */
#define APM_IOC_SUSPEND_REQ _IO('A', 8) /* request suspend */
#define APM_IOC_HIBERNATE _IO('A', 9) /* put system into hibernate */
#ifdef _KERNEL
void apm_setinfohook(int (*)(struct apm_power_info *));
int apm_record_event(u_int);
#endif
#endif /* _MACHINE_APMVAR_H_ */

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lib/libc/include/aarch64-openbsd-none/arm64/armreg.h vendored Normal file
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/* $OpenBSD: armreg.h,v 1.44 2025/07/22 09:20:41 kettenis Exp $ */
/*-
* Copyright (c) 2013, 2014 Andrew Turner
* Copyright (c) 2015 The FreeBSD Foundation
* All rights reserved.
*
* This software was developed by Andrew Turner under
* sponsorship from the FreeBSD Foundation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD: head/sys/arm64/include/armreg.h 309248 2016-11-28 14:24:07Z andrew $
*/
#ifndef _MACHINE_ARMREG_H_
#define _MACHINE_ARMREG_H_
#define INSN_SIZE 4
#define READ_SPECIALREG(reg) \
({ uint64_t val; \
__asm volatile("mrs %0, " __STRING(reg) : "=&r" (val)); \
val; \
})
#define WRITE_SPECIALREG(reg, val) \
__asm volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)val))
/* CCSIDR_EL1 - Current Cache Size ID Register */
#define CCSIDR_SETS_MASK 0x0fffe000
#define CCSIDR_SETS_SHIFT 13
#define CCSIDR_SETS(reg) \
((((reg) & CCSIDR_SETS_MASK) >> CCSIDR_SETS_SHIFT) + 1)
#define CCSIDR_WAYS_MASK 0x00001ff8
#define CCSIDR_WAYS_SHIFT 3
#define CCSIDR_WAYS(reg) \
((((reg) & CCSIDR_WAYS_MASK) >> CCSIDR_WAYS_SHIFT) + 1)
#define CCSIDR_LINE_MASK 0x00000007
#define CCSIDR_LINE_SIZE(reg) (1 << (((reg) & CCSIDR_LINE_MASK) + 4))
#define CCSIDR_CCIDX_SETS_MASK 0x00ffffff00000000ULL
#define CCSIDR_CCIDX_SETS_SHIFT 32
#define CCSIDR_CCIDX_SETS(reg) \
((((reg) & CCSIDR_CCIDX_SETS_MASK) >> CCSIDR_CCIDX_SETS_SHIFT) + 1)
#define CCSIDR_CCIDX_WAYS_MASK 0x0000000000fffff8ULL
#define CCSIDR_CCIDX_WAYS_SHIFT 3
#define CCSIDR_CCIDX_WAYS(reg) \
((((reg) & CCSIDR_CCIDX_WAYS_MASK) >> CCSIDR_CCIDX_WAYS_SHIFT) + 1)
#define CCSIDR_CCIDX_LINE_MASK 0x0000000000000007ULL
#define CCSIDR_CCIDX_LINE_SIZE(reg) \
(1 << (((reg) & CCSIDR_CCIDX_LINE_MASK) + 4))
/* CLIDR_EL1 - Cache Level ID Register */
#define CLIDR_CTYPE_MASK 0x7
#define CLIDR_CTYPE_INSN 0x1
#define CLIDR_CTYPE_DATA 0x2
#define CLIDR_CTYPE_UNIFIED 0x4
/* CNTHCTL_EL2 - Counter-timer Hypervisor Control Register */
#define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */
#define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */
#define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */
#define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */
#define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/
/* CNTKCTL_EL1 - Counter-timer Kernel Control Register */
#define CNTKCTL_EL0VCTEN (1 << 1) /* Allow EL0 virtual counter access */
/* CNTV_CTL_EL0 */
#define CNTV_CTL_ENABLE (1 << 0)
#define CNTV_CTL_IMASK (1 << 1)
#define CNTV_CTL_ISTATUS (1 << 2)
/* CPACR_EL1 */
#define CPACR_ZEN_MASK (0x3 << 16)
#define CPACR_ZEN_TRAP_ALL1 (0x0 << 16) /* Traps from EL0 and EL1 */
#define CPACR_ZEN_TRAP_EL0 (0x1 << 16) /* Traps from EL0 */
#define CPACR_ZEN_TRAP_ALL2 (0x2 << 16) /* Traps from EL0 and EL1 */
#define CPACR_ZEN_TRAP_NONE (0x3 << 16) /* No traps */
#define CPACR_FPEN_MASK (0x3 << 20)
#define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */
#define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */
#define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */
#define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */
#define CPACR_TTA (0x1 << 28)
/* CSSELR_EL1 - Cache Size Selection Register */
#define CSSELR_IND (1 << 0)
#define CSSELR_LEVEL_SHIFT 1
/* CTR_EL0 - Cache Type Register */
#define CTR_DLINE_SHIFT 16
#define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT)
#define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT)
#define CTR_IL1P_SHIFT 14
#define CTR_IL1P_MASK (0x3 << CTR_IL1P_SHIFT)
#define CTR_IL1P_AIVIVT (0x1 << CTR_IL1P_SHIFT)
#define CTR_IL1P_VIPT (0x2 << CTR_IL1P_SHIFT)
#define CTR_IL1P_PIPT (0x3 << CTR_IL1P_SHIFT)
#define CTR_ILINE_SHIFT 0
#define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT)
#define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT)
/* MPIDR_EL1 - Multiprocessor Affinity Register */
#define MPIDR_AFF3 (0xFFULL << 32)
#define MPIDR_AFF2 (0xFFULL << 16)
#define MPIDR_AFF1 (0xFFULL << 8)
#define MPIDR_AFF0 (0xFFULL << 0)
#define MPIDR_AFF (MPIDR_AFF3|MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0)
/* DCZID_EL0 - Data Cache Zero ID register */
#define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */
#define DCZID_BS_SHIFT 0
#define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT)
#define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT)
/* ESR_ELx */
#define ESR_ELx_ISS_MASK 0x00ffffff
#define ISS_INSN_FnV (0x01 << 10)
#define ISS_INSN_EA (0x01 << 9)
#define ISS_INSN_S1PTW (0x01 << 7)
#define ISS_INSN_IFSC_MASK (0x1f << 0)
#define ISS_DATA_ISV (0x01 << 24)
#define ISS_DATA_SAS_MASK (0x03 << 22)
#define ISS_DATA_SSE (0x01 << 21)
#define ISS_DATA_SRT_MASK (0x1f << 16)
#define ISS_DATA_SF (0x01 << 15)
#define ISS_DATA_AR (0x01 << 14)
#define ISS_DATA_FnV (0x01 << 10)
#define ISS_DATA_EA (0x01 << 9)
#define ISS_DATA_CM (0x01 << 8)
#define ISS_DATA_S1PTW (0x01 << 7)
#define ISS_DATA_WnR (0x01 << 6)
#define ISS_DATA_DFSC_MASK (0x3f << 0)
#define ISS_DATA_DFSC_ASF_L0 (0x00 << 0)
#define ISS_DATA_DFSC_ASF_L1 (0x01 << 0)
#define ISS_DATA_DFSC_ASF_L2 (0x02 << 0)
#define ISS_DATA_DFSC_ASF_L3 (0x03 << 0)
#define ISS_DATA_DFSC_TF_L0 (0x04 << 0)
#define ISS_DATA_DFSC_TF_L1 (0x05 << 0)
#define ISS_DATA_DFSC_TF_L2 (0x06 << 0)
#define ISS_DATA_DFSC_TF_L3 (0x07 << 0)
#define ISS_DATA_DFSC_AFF_L1 (0x09 << 0)
#define ISS_DATA_DFSC_AFF_L2 (0x0a << 0)
#define ISS_DATA_DFSC_AFF_L3 (0x0b << 0)
#define ISS_DATA_DFSC_PF_L1 (0x0d << 0)
#define ISS_DATA_DFSC_PF_L2 (0x0e << 0)
#define ISS_DATA_DFSC_PF_L3 (0x0f << 0)
#define ISS_DATA_DFSC_EXT (0x10 << 0)
#define ISS_DATA_DFSC_EXT_L0 (0x14 << 0)
#define ISS_DATA_DFSC_EXT_L1 (0x15 << 0)
#define ISS_DATA_DFSC_EXT_L2 (0x16 << 0)
#define ISS_DATA_DFSC_EXT_L3 (0x17 << 0)
#define ISS_DATA_DFSC_ECC (0x18 << 0)
#define ISS_DATA_DFSC_ECC_L0 (0x1c << 0)
#define ISS_DATA_DFSC_ECC_L1 (0x1d << 0)
#define ISS_DATA_DFSC_ECC_L2 (0x1e << 0)
#define ISS_DATA_DFSC_ECC_L3 (0x1f << 0)
#define ISS_DATA_DFSC_ALIGN (0x21 << 0)
#define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0)
#define ISS_MSR_DIR_SHIFT 0
#define ISS_MSR_DIR (0x01 << ISS_MSR_DIR_SHIFT)
#define ISS_MSR_Rt_SHIFT 5
#define ISS_MSR_Rt_MASK (0x1f << ISS_MSR_Rt_SHIFT)
#define ISS_MSR_Rt(x) (((x) & ISS_MSR_Rt_MASK) >> ISS_MSR_Rt_SHIFT)
#define ISS_MSR_CRm_SHIFT 1
#define ISS_MSR_CRm_MASK (0xf << ISS_MSR_CRm_SHIFT)
#define ISS_MSR_CRm(x) (((x) & ISS_MSR_CRm_MASK) >> ISS_MSR_CRm_SHIFT)
#define ISS_MSR_CRn_SHIFT 10
#define ISS_MSR_CRn_MASK (0xf << ISS_MSR_CRn_SHIFT)
#define ISS_MSR_CRn(x) (((x) & ISS_MSR_CRn_MASK) >> ISS_MSR_CRn_SHIFT)
#define ISS_MSR_OP1_SHIFT 14
#define ISS_MSR_OP1_MASK (0x7 << ISS_MSR_OP1_SHIFT)
#define ISS_MSR_OP1(x) (((x) & ISS_MSR_OP1_MASK) >> ISS_MSR_OP1_SHIFT)
#define ISS_MSR_OP2_SHIFT 17
#define ISS_MSR_OP2_MASK (0x7 << ISS_MSR_OP2_SHIFT)
#define ISS_MSR_OP2(x) (((x) & ISS_MSR_OP2_MASK) >> ISS_MSR_OP2_SHIFT)
#define ISS_MSR_OP0_SHIFT 20
#define ISS_MSR_OP0_MASK (0x3 << ISS_MSR_OP0_SHIFT)
#define ISS_MSR_OP0(x) (((x) & ISS_MSR_OP0_MASK) >> ISS_MSR_OP0_SHIFT)
#define ISS_BRK_COMMENT_MASK 0xffff
#define ESR_ELx_IL (0x01 << 25)
#define ESR_ELx_EC_SHIFT 26
#define ESR_ELx_EC_MASK (0x3f << 26)
#define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
#define EXCP_UNKNOWN 0x00 /* Unkwn exception */
#define EXCP_FP_SIMD 0x07 /* FP/SIMD trap */
#define EXCP_BRANCH_TGT 0x0d /* Branch target exception */
#define EXCP_ILL_STATE 0x0e /* Illegal execution state */
#define EXCP_SVC 0x15 /* SVC trap */
#define EXCP_MSR 0x18 /* MSR/MRS trap */
#define EXCP_SVE 0x19 /* SVE trap */
#define EXCP_FPAC 0x1c /* Faulting PAC trap */
#define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */
#define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */
#define EXCP_PC_ALIGN 0x22 /* PC alignment fault */
#define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */
#define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */
#define EXCP_SP_ALIGN 0x26 /* SP alignment fault */
#define EXCP_TRAP_FP 0x2c /* Trapped FP exception */
#define EXCP_SERROR 0x2f /* SError interrupt */
#define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */
#define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */
#define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */
#define EXCP_BRK 0x3c /* Breakpoint */
/* ICC_CTLR_EL1 */
#define ICC_CTLR_EL1_EOIMODE (1U << 1)
#define ICC_CTLR_EL1_PRIBITS_SHIFT 8
#define ICC_CTLR_EL1_PRIBITS_MASK (0x7UL << 8)
#define ICC_CTLR_EL1_PRIBITS(reg) \
(((reg) & ICC_CTLR_EL1_PRIBITS_MASK) >> ICC_CTLR_EL1_PRIBITS_SHIFT)
/* ICC_IAR1_EL1 */
#define ICC_IAR1_EL1_SPUR (0x03ff)
/* ICC_IGRPEN0_EL1 */
#define ICC_IGRPEN0_EL1_EN (1U << 0)
/* ICC_PMR_EL1 */
#define ICC_PMR_EL1_PRIO_MASK (0xFFUL)
/* ICC_SGI1R_EL1 */
#define ICC_SGI1R_EL1_TL_MASK 0xffffUL
#define ICC_SGI1R_EL1_AFF1_SHIFT 16
#define ICC_SGI1R_EL1_SGIID_SHIFT 24
#define ICC_SGI1R_EL1_AFF2_SHIFT 32
#define ICC_SGI1R_EL1_AFF3_SHIFT 48
#define ICC_SGI1R_EL1_SGIID_MASK 0xfUL
#define ICC_SGI1R_EL1_IRM (0x1UL << 40)
/* ICC_SRE_EL1 */
#define ICC_SRE_EL1_SRE (1U << 0)
/* ICC_SRE_EL2 */
#define ICC_SRE_EL2_SRE (1U << 0)
#define ICC_SRE_EL2_EN (1U << 3)
/* ID_AA64DFR0_EL1 */
#define ID_AA64DFR0_MASK 0x00000000f0f0ffffUL
#define ID_AA64DFR0_DEBUG_VER_SHIFT 0
#define ID_AA64DFR0_DEBUG_VER_MASK (0xfULL << ID_AA64DFR0_DEBUG_VER_SHIFT)
#define ID_AA64DFR0_DEBUG_VER(x) ((x) & ID_AA64DFR0_DEBUG_VER_MASK)
#define ID_AA64DFR0_DEBUG_VER_8 (0x6ULL << ID_AA64DFR0_DEBUG_VER_SHIFT)
#define ID_AA64DFR0_DEBUG_VER_8_VHE (0x7ULL << ID_AA64DFR0_DEBUG_VER_SHIFT)
#define ID_AA64DFR0_TRACE_VER_SHIFT 4
#define ID_AA64DFR0_TRACE_VER_MASK (0xfULL << ID_AA64DFR0_TRACE_VER_SHIFT)
#define ID_AA64DFR0_TRACE_VER(x) ((x) & ID_AA64DFR0_TRACE_VER_MASK)
#define ID_AA64DFR0_TRACE_VER_NONE (0x0ULL << ID_AA64DFR0_TRACE_VER_SHIFT)
#define ID_AA64DFR0_TRACE_VER_IMPL (0x1ULL << ID_AA64DFR0_TRACE_VER_SHIFT)
#define ID_AA64DFR0_PMU_VER_SHIFT 8
#define ID_AA64DFR0_PMU_VER_MASK (0xfULL << ID_AA64DFR0_PMU_VER_SHIFT)
#define ID_AA64DFR0_PMU_VER(x) ((x) & ID_AA64DFR0_PMU_VER_MASK)
#define ID_AA64DFR0_PMU_VER_NONE (0x0ULL << ID_AA64DFR0_PMU_VER_SHIFT)
#define ID_AA64DFR0_PMU_VER_3 (0x1ULL << ID_AA64DFR0_PMU_VER_SHIFT)
#define ID_AA64DFR0_PMU_VER_3_1 (0x4ULL << ID_AA64DFR0_PMU_VER_SHIFT)
#define ID_AA64DFR0_PMU_VER_IMPL (0xfULL << ID_AA64DFR0_PMU_VER_SHIFT)
#define ID_AA64DFR0_BRPS_SHIFT 12
#define ID_AA64DFR0_BRPS_MASK (0xfULL << ID_AA64DFR0_BRPS_SHIFT)
#define ID_AA64DFR0_BRPS(x) \
((((x) >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) + 1)
#define ID_AA64DFR0_WRPS_SHIFT 20
#define ID_AA64DFR0_WRPS_MASK (0xfULL << ID_AA64DFR0_WRPS_SHIFT)
#define ID_AA64DFR0_WRPS(x) \
((((x) >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) + 1)
#define ID_AA64DFR0_CTX_CMPS_SHIFT 28
#define ID_AA64DFR0_CTX_CMPS_MASK (0xfULL << ID_AA64DFR0_CTX_CMPS_SHIFT)
#define ID_AA64DFR0_CTX_CMPS(x) \
((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1)
/* ID_AA64ISAR0_EL1 */
#define ID_AA64ISAR0_MASK 0xfffffffff0fffff0ULL
#define ID_AA64ISAR0_AES_SHIFT 4
#define ID_AA64ISAR0_AES_MASK (0xfULL << ID_AA64ISAR0_AES_SHIFT)
#define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK)
#define ID_AA64ISAR0_AES_NONE (0x0ULL << ID_AA64ISAR0_AES_SHIFT)
#define ID_AA64ISAR0_AES_BASE (0x1ULL << ID_AA64ISAR0_AES_SHIFT)
#define ID_AA64ISAR0_AES_PMULL (0x2ULL << ID_AA64ISAR0_AES_SHIFT)
#define ID_AA64ISAR0_SHA1_SHIFT 8
#define ID_AA64ISAR0_SHA1_MASK (0xfULL << ID_AA64ISAR0_SHA1_SHIFT)
#define ID_AA64ISAR0_SHA1(x) ((x) & ID_AA64ISAR0_SHA1_MASK)
#define ID_AA64ISAR0_SHA1_NONE (0x0ULL << ID_AA64ISAR0_SHA1_SHIFT)
#define ID_AA64ISAR0_SHA1_BASE (0x1ULL << ID_AA64ISAR0_SHA1_SHIFT)
#define ID_AA64ISAR0_SHA2_SHIFT 12
#define ID_AA64ISAR0_SHA2_MASK (0xfULL << ID_AA64ISAR0_SHA2_SHIFT)
#define ID_AA64ISAR0_SHA2(x) ((x) & ID_AA64ISAR0_SHA2_MASK)
#define ID_AA64ISAR0_SHA2_NONE (0x0ULL << ID_AA64ISAR0_SHA2_SHIFT)
#define ID_AA64ISAR0_SHA2_BASE (0x1ULL << ID_AA64ISAR0_SHA2_SHIFT)
#define ID_AA64ISAR0_SHA2_512 (0x2ULL << ID_AA64ISAR0_SHA2_SHIFT)
#define ID_AA64ISAR0_CRC32_SHIFT 16
#define ID_AA64ISAR0_CRC32_MASK (0xfULL << ID_AA64ISAR0_CRC32_SHIFT)
#define ID_AA64ISAR0_CRC32(x) ((x) & ID_AA64ISAR0_CRC32_MASK)
#define ID_AA64ISAR0_CRC32_NONE (0x0ULL << ID_AA64ISAR0_CRC32_SHIFT)
#define ID_AA64ISAR0_CRC32_BASE (0x1ULL << ID_AA64ISAR0_CRC32_SHIFT)
#define ID_AA64ISAR0_ATOMIC_SHIFT 20
#define ID_AA64ISAR0_ATOMIC_MASK (0xfULL << ID_AA64ISAR0_ATOMIC_SHIFT)
#define ID_AA64ISAR0_ATOMIC(x) ((x) & ID_AA64ISAR0_ATOMIC_MASK)
#define ID_AA64ISAR0_ATOMIC_NONE (0x0ULL << ID_AA64ISAR0_ATOMIC_SHIFT)
#define ID_AA64ISAR0_ATOMIC_IMPL (0x2ULL << ID_AA64ISAR0_ATOMIC_SHIFT)
#define ID_AA64ISAR0_RDM_SHIFT 28
#define ID_AA64ISAR0_RDM_MASK (0xfULL << ID_AA64ISAR0_RDM_SHIFT)
#define ID_AA64ISAR0_RDM(x) ((x) & ID_AA64ISAR0_RDM_MASK)
#define ID_AA64ISAR0_RDM_NONE (0x0ULL << ID_AA64ISAR0_RDM_SHIFT)
#define ID_AA64ISAR0_RDM_IMPL (0x1ULL << ID_AA64ISAR0_RDM_SHIFT)
#define ID_AA64ISAR0_SHA3_SHIFT 32
#define ID_AA64ISAR0_SHA3_MASK (0xfULL << ID_AA64ISAR0_SHA3_SHIFT)
#define ID_AA64ISAR0_SHA3(x) ((x) & ID_AA64ISAR0_SHA3_MASK)
#define ID_AA64ISAR0_SHA3_NONE (0x0ULL << ID_AA64ISAR0_SHA3_SHIFT)
#define ID_AA64ISAR0_SHA3_IMPL (0x1ULL << ID_AA64ISAR0_SHA3_SHIFT)
#define ID_AA64ISAR0_SM3_SHIFT 36
#define ID_AA64ISAR0_SM3_MASK (0xfULL << ID_AA64ISAR0_SM3_SHIFT)
#define ID_AA64ISAR0_SM3(x) ((x) & ID_AA64ISAR0_SM3_MASK)
#define ID_AA64ISAR0_SM3_NONE (0x0ULL << ID_AA64ISAR0_SM3_SHIFT)
#define ID_AA64ISAR0_SM3_IMPL (0x1ULL << ID_AA64ISAR0_SM3_SHIFT)
#define ID_AA64ISAR0_SM4_SHIFT 40
#define ID_AA64ISAR0_SM4_MASK (0xfULL << ID_AA64ISAR0_SM4_SHIFT)
#define ID_AA64ISAR0_SM4(x) ((x) & ID_AA64ISAR0_SM4_MASK)
#define ID_AA64ISAR0_SM4_NONE (0x0ULL << ID_AA64ISAR0_SM4_SHIFT)
#define ID_AA64ISAR0_SM4_IMPL (0x1ULL << ID_AA64ISAR0_SM4_SHIFT)
#define ID_AA64ISAR0_DP_SHIFT 44
#define ID_AA64ISAR0_DP_MASK (0xfULL << ID_AA64ISAR0_DP_SHIFT)
#define ID_AA64ISAR0_DP(x) ((x) & ID_AA64ISAR0_DP_MASK)
#define ID_AA64ISAR0_DP_NONE (0x0ULL << ID_AA64ISAR0_DP_SHIFT)
#define ID_AA64ISAR0_DP_IMPL (0x1ULL << ID_AA64ISAR0_DP_SHIFT)
#define ID_AA64ISAR0_FHM_SHIFT 48
#define ID_AA64ISAR0_FHM_MASK (0xfULL << ID_AA64ISAR0_FHM_SHIFT)
#define ID_AA64ISAR0_FHM(x) ((x) & ID_AA64ISAR0_FHM_MASK)
#define ID_AA64ISAR0_FHM_NONE (0x0ULL << ID_AA64ISAR0_FHM_SHIFT)
#define ID_AA64ISAR0_FHM_IMPL (0x1ULL << ID_AA64ISAR0_FHM_SHIFT)
#define ID_AA64ISAR0_TS_SHIFT 52
#define ID_AA64ISAR0_TS_MASK (0xfULL << ID_AA64ISAR0_TS_SHIFT)
#define ID_AA64ISAR0_TS(x) ((x) & ID_AA64ISAR0_TS_MASK)
#define ID_AA64ISAR0_TS_NONE (0x0ULL << ID_AA64ISAR0_TS_SHIFT)
#define ID_AA64ISAR0_TS_BASE (0x1ULL << ID_AA64ISAR0_TS_SHIFT)
#define ID_AA64ISAR0_TS_AXFLAG (0x2ULL << ID_AA64ISAR0_TS_SHIFT)
#define ID_AA64ISAR0_TLB_SHIFT 56
#define ID_AA64ISAR0_TLB_MASK (0xfULL << ID_AA64ISAR0_TLB_SHIFT)
#define ID_AA64ISAR0_TLB(x) ((x) & ID_AA64ISAR0_TLB_MASK)
#define ID_AA64ISAR0_TLB_NONE (0x0ULL << ID_AA64ISAR0_TLB_SHIFT)
#define ID_AA64ISAR0_TLB_IOS (0x1ULL << ID_AA64ISAR0_TLB_SHIFT)
#define ID_AA64ISAR0_TLB_IRANGE (0x2ULL << ID_AA64ISAR0_TLB_SHIFT)
#define ID_AA64ISAR0_RNDR_SHIFT 60
#define ID_AA64ISAR0_RNDR_MASK (0xfULL << ID_AA64ISAR0_RNDR_SHIFT)
#define ID_AA64ISAR0_RNDR(x) ((x) & ID_AA64ISAR0_RNDR_MASK)
#define ID_AA64ISAR0_RNDR_NONE (0x0ULL << ID_AA64ISAR0_RNDR_SHIFT)
#define ID_AA64ISAR0_RNDR_IMPL (0x1ULL << ID_AA64ISAR0_RNDR_SHIFT)
/* ID_AA64ISAR1_EL1 */
#define ID_AA64ISAR1_MASK 0xffffffffffffffffULL
#define ID_AA64ISAR1_DPB_SHIFT 0
#define ID_AA64ISAR1_DPB_MASK (0xfULL << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_DPB(x) ((x) & ID_AA64ISAR1_DPB_MASK)
#define ID_AA64ISAR1_DPB_NONE (0x0ULL << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_DPB_IMPL (0x1ULL << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_DPB_DCCVADP (0x2ULL << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_APA_SHIFT 4
#define ID_AA64ISAR1_APA_MASK (0xfULL << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_APA(x) ((x) & ID_AA64ISAR1_APA_MASK)
#define ID_AA64ISAR1_APA_NONE (0x0ULL << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_APA_PAC (0x1ULL << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_APA_EPAC (0x2ULL << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_APA_EPAC2 (0x3ULL << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_APA_FPAC (0x4ULL << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_APA_FPAC_COMBINED (0x5ULL << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_API_SHIFT 8
#define ID_AA64ISAR1_API_MASK (0xfULL << ID_AA64ISAR1_API_SHIFT)
#define ID_AA64ISAR1_API(x) ((x) & ID_AA64ISAR1_API_MASK)
#define ID_AA64ISAR1_API_NONE (0x0ULL << ID_AA64ISAR1_API_SHIFT)
#define ID_AA64ISAR1_API_PAC (0x1ULL << ID_AA64ISAR1_API_SHIFT)
#define ID_AA64ISAR1_API_EPAC (0x2ULL << ID_AA64ISAR1_API_SHIFT)
#define ID_AA64ISAR1_API_EPAC2 (0x3ULL << ID_AA64ISAR1_API_SHIFT)
#define ID_AA64ISAR1_API_FPAC (0x4ULL << ID_AA64ISAR1_API_SHIFT)
#define ID_AA64ISAR1_API_FPAC_COMBINED (0x5ULL << ID_AA64ISAR1_API_SHIFT)
#define ID_AA64ISAR1_JSCVT_SHIFT 12
#define ID_AA64ISAR1_JSCVT_MASK (0xfULL << ID_AA64ISAR1_JSCVT_SHIFT)
#define ID_AA64ISAR1_JSCVT(x) ((x) & ID_AA64ISAR1_JSCVT_MASK)
#define ID_AA64ISAR1_JSCVT_NONE (0x0ULL << ID_AA64ISAR1_JSCVT_SHIFT)
#define ID_AA64ISAR1_JSCVT_IMPL (0x1ULL << ID_AA64ISAR1_JSCVT_SHIFT)
#define ID_AA64ISAR1_FCMA_SHIFT 16
#define ID_AA64ISAR1_FCMA_MASK (0xfULL << ID_AA64ISAR1_FCMA_SHIFT)
#define ID_AA64ISAR1_FCMA(x) ((x) & ID_AA64ISAR1_FCMA_MASK)
#define ID_AA64ISAR1_FCMA_NONE (0x0ULL << ID_AA64ISAR1_FCMA_SHIFT)
#define ID_AA64ISAR1_FCMA_IMPL (0x1ULL << ID_AA64ISAR1_FCMA_SHIFT)
#define ID_AA64ISAR1_LRCPC_SHIFT 20
#define ID_AA64ISAR1_LRCPC_MASK (0xfULL << ID_AA64ISAR1_LRCPC_SHIFT)
#define ID_AA64ISAR1_LRCPC(x) ((x) & ID_AA64ISAR1_LRCPC_MASK)
#define ID_AA64ISAR1_LRCPC_NONE (0x0ULL << ID_AA64ISAR1_LRCPC_SHIFT)
#define ID_AA64ISAR1_LRCPC_BASE (0x1ULL << ID_AA64ISAR1_LRCPC_SHIFT)
#define ID_AA64ISAR1_LRCPC_LDAPUR (0x2ULL << ID_AA64ISAR1_LRCPC_SHIFT)
#define ID_AA64ISAR1_GPA_SHIFT 24
#define ID_AA64ISAR1_GPA_MASK (0xfULL << ID_AA64ISAR1_GPA_SHIFT)
#define ID_AA64ISAR1_GPA(x) ((x) & ID_AA64ISAR1_GPA_MASK)
#define ID_AA64ISAR1_GPA_NONE (0x0ULL << ID_AA64ISAR1_GPA_SHIFT)
#define ID_AA64ISAR1_GPA_IMPL (0x1ULL << ID_AA64ISAR1_GPA_SHIFT)
#define ID_AA64ISAR1_GPI_SHIFT 28
#define ID_AA64ISAR1_GPI_MASK (0xfULL << ID_AA64ISAR1_GPI_SHIFT)
#define ID_AA64ISAR1_GPI(x) ((x) & ID_AA64ISAR1_GPI_MASK)
#define ID_AA64ISAR1_GPI_NONE (0x0ULL << ID_AA64ISAR1_GPI_SHIFT)
#define ID_AA64ISAR1_GPI_IMPL (0x1ULL << ID_AA64ISAR1_GPI_SHIFT)
#define ID_AA64ISAR1_FRINTTS_SHIFT 32
#define ID_AA64ISAR1_FRINTTS_MASK (0xfULL << ID_AA64ISAR1_FRINTTS_SHIFT)
#define ID_AA64ISAR1_FRINTTS(x) ((x) & ID_AA64ISAR1_FRINTTS_MASK)
#define ID_AA64ISAR1_FRINTTS_NONE (0x0ULL << ID_AA64ISAR1_FRINTTS_SHIFT)
#define ID_AA64ISAR1_FRINTTS_IMPL (0x1ULL << ID_AA64ISAR1_FRINTTS_SHIFT)
#define ID_AA64ISAR1_SB_SHIFT 36
#define ID_AA64ISAR1_SB_MASK (0xfULL << ID_AA64ISAR1_SB_SHIFT)
#define ID_AA64ISAR1_SB(x) ((x) & ID_AA64ISAR1_SB_MASK)
#define ID_AA64ISAR1_SB_NONE (0x0ULL << ID_AA64ISAR1_SB_SHIFT)
#define ID_AA64ISAR1_SB_IMPL (0x1ULL << ID_AA64ISAR1_SB_SHIFT)
#define ID_AA64ISAR1_SPECRES_SHIFT 40
#define ID_AA64ISAR1_SPECRES_MASK (0xfULL << ID_AA64ISAR1_SPECRES_SHIFT)
#define ID_AA64ISAR1_SPECRES(x) ((x) & ID_AA64ISAR1_SPECRES_MASK)
#define ID_AA64ISAR1_SPECRES_NONE (0x0ULL << ID_AA64ISAR1_SPECRES_SHIFT)
#define ID_AA64ISAR1_SPECRES_IMPL (0x1ULL << ID_AA64ISAR1_SPECRES_SHIFT)
#define ID_AA64ISAR1_BF16_SHIFT 44
#define ID_AA64ISAR1_BF16_MASK (0xfULL << ID_AA64ISAR1_BF16_SHIFT)
#define ID_AA64ISAR1_BF16(x) ((x) & ID_AA64ISAR1_BF16_MASK)
#define ID_AA64ISAR1_BF16_NONE (0x0ULL << ID_AA64ISAR1_BF16_SHIFT)
#define ID_AA64ISAR1_BF16_BASE (0x1ULL << ID_AA64ISAR1_BF16_SHIFT)
#define ID_AA64ISAR1_BF16_EBF (0x2ULL << ID_AA64ISAR1_BF16_SHIFT)
#define ID_AA64ISAR1_DGH_SHIFT 48
#define ID_AA64ISAR1_DGH_MASK (0xfULL << ID_AA64ISAR1_DGH_SHIFT)
#define ID_AA64ISAR1_DGH(x) ((x) & ID_AA64ISAR1_DGH_MASK)
#define ID_AA64ISAR1_DGH_NONE (0x0ULL << ID_AA64ISAR1_DGH_SHIFT)
#define ID_AA64ISAR1_DGH_IMPL (0x1ULL << ID_AA64ISAR1_DGH_SHIFT)
#define ID_AA64ISAR1_I8MM_SHIFT 52
#define ID_AA64ISAR1_I8MM_MASK (0xfULL << ID_AA64ISAR1_I8MM_SHIFT)
#define ID_AA64ISAR1_I8MM(x) ((x) & ID_AA64ISAR1_I8MM_MASK)
#define ID_AA64ISAR1_I8MM_NONE (0x0ULL << ID_AA64ISAR1_I8MM_SHIFT)
#define ID_AA64ISAR1_I8MM_IMPL (0x1ULL << ID_AA64ISAR1_I8MM_SHIFT)
#define ID_AA64ISAR1_XS_SHIFT 56
#define ID_AA64ISAR1_XS_MASK (0xfULL << ID_AA64ISAR1_XS_SHIFT)
#define ID_AA64ISAR1_XS(x) ((x) & ID_AA64ISAR1_XS_MASK)
#define ID_AA64ISAR1_XS_NONE (0x0ULL << ID_AA64ISAR1_XS_SHIFT)
#define ID_AA64ISAR1_XS_IMPL (0x1ULL << ID_AA64ISAR1_XS_SHIFT)
#define ID_AA64ISAR1_LS64_SHIFT 60
#define ID_AA64ISAR1_LS64_MASK (0xfULL << ID_AA64ISAR1_LS64_SHIFT)
#define ID_AA64ISAR1_LS64(x) ((x) & ID_AA64ISAR1_LS64_MASK)
#define ID_AA64ISAR1_LS64_NONE (0x0ULL << ID_AA64ISAR1_LS64_SHIFT)
#define ID_AA64ISAR1_LS64_BASE (0x1ULL << ID_AA64ISAR1_LS64_SHIFT)
#define ID_AA64ISAR1_LS64_V (0x2ULL << ID_AA64ISAR1_LS64_SHIFT)
#define ID_AA64ISAR1_LS64_ACCDATA (0x3ULL << ID_AA64ISAR1_LS64_SHIFT)
/* ID_AA64ISAR2_EL1 */
#define ID_AA64ISAR2_MASK 0x00ff0000f0ffffffULL
#define ID_AA64ISAR2_WFXT_SHIFT 0
#define ID_AA64ISAR2_WFXT_MASK (0xfULL << ID_AA64ISAR2_WFXT_SHIFT)
#define ID_AA64ISAR2_WFXT(x) ((x) & ID_AA64ISAR2_WFXT_MASK)
#define ID_AA64ISAR2_WFXT_NONE (0x0ULL << ID_AA64ISAR2_WFXT_SHIFT)
#define ID_AA64ISAR2_WFXT_IMPL (0x2ULL << ID_AA64ISAR2_WFXT_SHIFT)
#define ID_AA64ISAR2_RPRES_SHIFT 4
#define ID_AA64ISAR2_RPRES_MASK (0xfULL << ID_AA64ISAR2_RPRES_SHIFT)
#define ID_AA64ISAR2_RPRES(x) ((x) & ID_AA64ISAR2_RPRES_MASK)
#define ID_AA64ISAR2_RPRES_NONE (0x0ULL << ID_AA64ISAR2_RPRES_SHIFT)
#define ID_AA64ISAR2_RPRES_IMPL (0x1ULL << ID_AA64ISAR2_RPRES_SHIFT)
#define ID_AA64ISAR2_GPA3_SHIFT 8
#define ID_AA64ISAR2_GPA3_WIDTH 4
#define ID_AA64ISAR2_GPA3_MASK (0xfULL << ID_AA64ISAR2_GPA3_SHIFT)
#define ID_AA64ISAR2_GPA3(x) ((x) & ID_AA64ISAR2_GPA3_MASK)
#define ID_AA64ISAR2_GPA3_NONE (0x0ULL << ID_AA64ISAR2_GPA3_SHIFT)
#define ID_AA64ISAR2_GPA3_IMPL (0x1ULL << ID_AA64ISAR2_GPA3_SHIFT)
#define ID_AA64ISAR2_APA3_SHIFT 12
#define ID_AA64ISAR2_APA3_WIDTH 4
#define ID_AA64ISAR2_APA3_MASK (0xfULL << ID_AA64ISAR2_APA3_SHIFT)
#define ID_AA64ISAR2_APA3(x) ((x) & ID_AA64ISAR2_APA3_MASK)
#define ID_AA64ISAR2_APA3_NONE (0x0ULL << ID_AA64ISAR2_APA3_SHIFT)
#define ID_AA64ISAR2_APA3_PAC (0x1ULL << ID_AA64ISAR2_APA3_SHIFT)
#define ID_AA64ISAR2_APA3_EPAC (0x2ULL << ID_AA64ISAR2_APA3_SHIFT)
#define ID_AA64ISAR2_APA3_EPAC2 (0x3ULL << ID_AA64ISAR2_APA3_SHIFT)
#define ID_AA64ISAR2_APA3_FPAC (0x4ULL << ID_AA64ISAR2_APA3_SHIFT)
#define ID_AA64ISAR2_APA3_FPAC_COMBINED (0x5ULL << ID_AA64ISAR2_APA3_SHIFT)
#define ID_AA64ISAR2_MOPS_SHIFT 16
#define ID_AA64ISAR2_MOPS_MASK (0xfULL << ID_AA64ISAR2_MOPS_SHIFT)
#define ID_AA64ISAR2_MOPS(x) ((x) & ID_AA64ISAR2_MOPS_MASK)
#define ID_AA64ISAR2_MOPS_NONE (0x0ULL << ID_AA64ISAR2_MOPS_SHIFT)
#define ID_AA64ISAR2_MOPS_IMPL (0x1ULL << ID_AA64ISAR2_MOPS_SHIFT)
#define ID_AA64ISAR2_BC_SHIFT 20
#define ID_AA64ISAR2_BC_MASK (0xfULL << ID_AA64ISAR2_BC_SHIFT)
#define ID_AA64ISAR2_BC(x) ((x) & ID_AA64ISAR2_BC_MASK)
#define ID_AA64ISAR2_BC_NONE (0x0ULL << ID_AA64ISAR2_BC_SHIFT)
#define ID_AA64ISAR2_BC_IMPL (0x1ULL << ID_AA64ISAR2_BC_SHIFT)
#define ID_AA64ISAR2_CLRBHB_SHIFT 28
#define ID_AA64ISAR2_CLRBHB_MASK (0xfULL << ID_AA64ISAR2_CLRBHB_SHIFT)
#define ID_AA64ISAR2_CLRBHB(x) ((x) & ID_AA64ISAR2_CLRBHB_MASK)
#define ID_AA64ISAR2_CLRBHB_NONE (0x0ULL << ID_AA64ISAR2_CLRBHB_SHIFT)
#define ID_AA64ISAR2_CLRBHB_IMPL (0x1ULL << ID_AA64ISAR2_CLRBHB_SHIFT)
#define ID_AA64ISAR2_RPRFM_SHIFT 48
#define ID_AA64ISAR2_RPRFM_MASK (0xfULL << ID_AA64ISAR2_RPRFM_SHIFT)
#define ID_AA64ISAR2_RPRFM(x) ((x) & ID_AA64ISAR2_RPRFM_MASK)
#define ID_AA64ISAR2_RPRFM_NONE (0x0ULL << ID_AA64ISAR2_RPRFM_SHIFT)
#define ID_AA64ISAR2_RPRFM_IMPL (0x1ULL << ID_AA64ISAR2_RPRFM_SHIFT)
#define ID_AA64ISAR2_CSSC_SHIFT 52
#define ID_AA64ISAR2_CSSC_MASK (0xfULL << ID_AA64ISAR2_CSSC_SHIFT)
#define ID_AA64ISAR2_CSSC(x) ((x) & ID_AA64ISAR2_CSSC_MASK)
#define ID_AA64ISAR2_CSSC_NONE (0x0ULL << ID_AA64ISAR2_CSSC_SHIFT)
#define ID_AA64ISAR2_CSSC_IMPL (0x1ULL << ID_AA64ISAR2_CSSC_SHIFT)
/* ID_AA64MMFR0_EL1 */
#define ID_AA64MMFR0_MASK 0xf0000000ffffffffULL
#define ID_AA64MMFR0_PA_RANGE_SHIFT 0
#define ID_AA64MMFR0_PA_RANGE_MASK (0xfULL << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_PA_RANGE(x) ((x) & ID_AA64MMFR0_PA_RANGE_MASK)
#define ID_AA64MMFR0_PA_RANGE_4G (0x0ULL << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_PA_RANGE_64G (0x1ULL << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_PA_RANGE_1T (0x2ULL << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_PA_RANGE_4T (0x3ULL << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_PA_RANGE_16T (0x4ULL << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_PA_RANGE_256T (0x5ULL << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_ASID_BITS_SHIFT 4
#define ID_AA64MMFR0_ASID_BITS_MASK (0xfULL << ID_AA64MMFR0_ASID_BITS_SHIFT)
#define ID_AA64MMFR0_ASID_BITS(x) ((x) & ID_AA64MMFR0_ASID_BITS_MASK)
#define ID_AA64MMFR0_ASID_BITS_8 (0x0ULL << ID_AA64MMFR0_ASID_BITS_SHIFT)
#define ID_AA64MMFR0_ASID_BITS_16 (0x2ULL << ID_AA64MMFR0_ASID_BITS_SHIFT)
#define ID_AA64MMFR0_BIGEND_SHIFT 8
#define ID_AA64MMFR0_BIGEND_MASK (0xfULL << ID_AA64MMFR0_BIGEND_SHIFT)
#define ID_AA64MMFR0_BIGEND(x) ((x) & ID_AA64MMFR0_BIGEND_MASK)
#define ID_AA64MMFR0_BIGEND_FIXED (0x0ULL << ID_AA64MMFR0_BIGEND_SHIFT)
#define ID_AA64MMFR0_BIGEND_MIXED (0x1ULL << ID_AA64MMFR0_BIGEND_SHIFT)
#define ID_AA64MMFR0_S_NS_MEM_SHIFT 12
#define ID_AA64MMFR0_S_NS_MEM_MASK (0xfULL << ID_AA64MMFR0_S_NS_MEM_SHIFT)
#define ID_AA64MMFR0_S_NS_MEM(x) ((x) & ID_AA64MMFR0_S_NS_MEM_MASK)
#define ID_AA64MMFR0_S_NS_MEM_NONE (0x0ULL << ID_AA64MMFR0_S_NS_MEM_SHIFT)
#define ID_AA64MMFR0_S_NS_MEM_DISTINCT (0x1ULL << ID_AA64MMFR0_S_NS_MEM_SHIFT)
#define ID_AA64MMFR0_BIGEND_EL0_SHIFT 16
#define ID_AA64MMFR0_BIGEND_EL0_MASK (0xfULL << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
#define ID_AA64MMFR0_BIGEND_EL0(x) ((x) & ID_AA64MMFR0_BIGEND_EL0_MASK)
#define ID_AA64MMFR0_BIGEND_EL0_FIXED (0x0ULL << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
#define ID_AA64MMFR0_BIGEND_EL0_MIXED (0x1ULL << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
#define ID_AA64MMFR0_TGRAN16_SHIFT 20
#define ID_AA64MMFR0_TGRAN16_MASK (0xfULL << ID_AA64MMFR0_TGRAN16_SHIFT)
#define ID_AA64MMFR0_TGRAN16(x) ((x) & ID_AA64MMFR0_TGRAN16_MASK)
#define ID_AA64MMFR0_TGRAN16_NONE (0x0ULL << ID_AA64MMFR0_TGRAN16_SHIFT)
#define ID_AA64MMFR0_TGRAN16_IMPL (0x1ULL << ID_AA64MMFR0_TGRAN16_SHIFT)
#define ID_AA64MMFR0_TGRAN64_SHIFT 24
#define ID_AA64MMFR0_TGRAN64_MASK (0xfULL << ID_AA64MMFR0_TGRAN64_SHIFT)
#define ID_AA64MMFR0_TGRAN64(x) ((x) & ID_AA64MMFR0_TGRAN64_MASK)
#define ID_AA64MMFR0_TGRAN64_IMPL (0x0ULL << ID_AA64MMFR0_TGRAN64_SHIFT)
#define ID_AA64MMFR0_TGRAN64_NONE (0xfULL << ID_AA64MMFR0_TGRAN64_SHIFT)
#define ID_AA64MMFR0_TGRAN4_SHIFT 28
#define ID_AA64MMFR0_TGRAN4_MASK (0xfULL << ID_AA64MMFR0_TGRAN4_SHIFT)
#define ID_AA64MMFR0_TGRAN4(x) ((x) & ID_AA64MMFR0_TGRAN4_MASK)
#define ID_AA64MMFR0_TGRAN4_IMPL (0x0ULL << ID_AA64MMFR0_TGRAN4_SHIFT)
#define ID_AA64MMFR0_TGRAN4_NONE (0xfULL << ID_AA64MMFR0_TGRAN4_SHIFT)
#define ID_AA64MMFR0_ECV_SHIFT 60
#define ID_AA64MMFR0_ECV_MASK (0xfULL << ID_AA64MMFR0_ECV_SHIFT)
#define ID_AA64MMFR0_ECV(x) ((x) & ID_AA64MMFR0_ECV_MASK)
#define ID_AA64MMFR0_ECV_NONE (0x0ULL << ID_AA64MMFR0_ECV_SHIFT)
#define ID_AA64MMFR0_ECV_IMPL (0x1ULL << ID_AA64MMFR0_ECV_SHIFT)
#define ID_AA64MMFR0_ECV_CNTHCTL (0x2ULL << ID_AA64MMFR0_ECV_SHIFT)
/* ID_AA64MMFR1_EL1 */
#define ID_AA64MMFR1_MASK 0xf000f000ffffffffULL
#define ID_AA64MMFR1_HAFDBS_SHIFT 0
#define ID_AA64MMFR1_HAFDBS_MASK (0xfULL << ID_AA64MMFR1_HAFDBS_SHIFT)
#define ID_AA64MMFR1_HAFDBS(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK)
#define ID_AA64MMFR1_HAFDBS_NONE (0x0ULL << ID_AA64MMFR1_HAFDBS_SHIFT)
#define ID_AA64MMFR1_HAFDBS_AF (0x1ULL << ID_AA64MMFR1_HAFDBS_SHIFT)
#define ID_AA64MMFR1_HAFDBS_AF_DBS (0x2ULL << ID_AA64MMFR1_HAFDBS_SHIFT)
#define ID_AA64MMFR1_VMIDBITS_SHIFT 4
#define ID_AA64MMFR1_VMIDBITS_MASK (0xfULL << ID_AA64MMFR1_VMIDBITS_SHIFT)
#define ID_AA64MMFR1_VMIDBITS(x) ((x) & ID_AA64MMFR1_VMIDBITS_MASK)
#define ID_AA64MMFR1_VMIDBITS_8 (0x0ULL << ID_AA64MMFR1_VMIDBITS_SHIFT)
#define ID_AA64MMFR1_VMIDBITS_16 (0x2ULL << ID_AA64MMFR1_VMIDBITS_SHIFT)
#define ID_AA64MMFR1_VH_SHIFT 8
#define ID_AA64MMFR1_VH_MASK (0xfULL << ID_AA64MMFR1_VH_SHIFT)
#define ID_AA64MMFR1_VH(x) ((x) & ID_AA64MMFR1_VH_MASK)
#define ID_AA64MMFR1_VH_NONE (0x0ULL << ID_AA64MMFR1_VH_SHIFT)
#define ID_AA64MMFR1_VH_IMPL (0x1ULL << ID_AA64MMFR1_VH_SHIFT)
#define ID_AA64MMFR1_HPDS_SHIFT 12
#define ID_AA64MMFR1_HPDS_MASK (0xfULL << ID_AA64MMFR1_HPDS_SHIFT)
#define ID_AA64MMFR1_HPDS(x) ((x) & ID_AA64MMFR1_HPDS_MASK)
#define ID_AA64MMFR1_HPDS_NONE (0x0ULL << ID_AA64MMFR1_HPDS_SHIFT)
#define ID_AA64MMFR1_HPDS_IMPL (0x1ULL << ID_AA64MMFR1_HPDS_SHIFT)
#define ID_AA64MMFR1_LO_SHIFT 16
#define ID_AA64MMFR1_LO_MASK (0xfULL << ID_AA64MMFR1_LO_SHIFT)
#define ID_AA64MMFR1_LO(x) ((x) & ID_AA64MMFR1_LO_MASK)
#define ID_AA64MMFR1_LO_NONE (0x0ULL << ID_AA64MMFR1_LO_SHIFT)
#define ID_AA64MMFR1_LO_IMPL (0x1ULL << ID_AA64MMFR1_LO_SHIFT)
#define ID_AA64MMFR1_PAN_SHIFT 20
#define ID_AA64MMFR1_PAN_MASK (0xfULL << ID_AA64MMFR1_PAN_SHIFT)
#define ID_AA64MMFR1_PAN(x) ((x) & ID_AA64MMFR1_PAN_MASK)
#define ID_AA64MMFR1_PAN_NONE (0x0ULL << ID_AA64MMFR1_PAN_SHIFT)
#define ID_AA64MMFR1_PAN_IMPL (0x1ULL << ID_AA64MMFR1_PAN_SHIFT)
#define ID_AA64MMFR1_PAN_ATS1E1 (0x2ULL << ID_AA64MMFR1_PAN_SHIFT)
#define ID_AA64MMFR1_PAN_EPAN (0x3ULL << ID_AA64MMFR1_PAN_SHIFT)
#define ID_AA64MMFR1_SPECSEI_SHIFT 24
#define ID_AA64MMFR1_SPECSEI_MASK (0xfULL << ID_AA64MMFR1_SPECSEI_SHIFT)
#define ID_AA64MMFR1_SPECSEI(x) ((x) & ID_AA64MMFR1_SPECSEI_MASK)
#define ID_AA64MMFR1_SPECSEI_NONE (0x0ULL << ID_AA64MMFR1_SPECSEI_SHIFT)
#define ID_AA64MMFR1_SPECSEI_IMPL (0x1ULL << ID_AA64MMFR1_SPECSEI_SHIFT)
#define ID_AA64MMFR1_XNX_SHIFT 28
#define ID_AA64MMFR1_XNX_MASK (0xfULL << ID_AA64MMFR1_XNX_SHIFT)
#define ID_AA64MMFR1_XNX(x) ((x) & ID_AA64MMFR1_XNX_MASK)
#define ID_AA64MMFR1_XNX_NONE (0x0ULL << ID_AA64MMFR1_XNX_SHIFT)
#define ID_AA64MMFR1_XNX_IMPL (0x1ULL << ID_AA64MMFR1_XNX_SHIFT)
#define ID_AA64MMFR1_AFP_SHIFT 44
#define ID_AA64MMFR1_AFP_MASK (0xfULL << ID_AA64MMFR1_AFP_SHIFT)
#define ID_AA64MMFR1_AFP(x) ((x) & ID_AA64MMFR1_AFP_MASK)
#define ID_AA64MMFR1_AFP_NONE (0x0ULL << ID_AA64MMFR1_AFP_SHIFT)
#define ID_AA64MMFR1_AFP_IMPL (0x1ULL << ID_AA64MMFR1_AFP_SHIFT)
#define ID_AA64MMFR1_ECBHB_SHIFT 60
#define ID_AA64MMFR1_ECBHB_MASK (0xfULL << ID_AA64MMFR1_ECBHB_SHIFT)
#define ID_AA64MMFR1_ECBHB(x) ((x) & ID_AA64MMFR1_ECBHB_MASK)
#define ID_AA64MMFR1_ECBHB_NONE (0x0ULL << ID_AA64MMFR1_ECBHB_SHIFT)
#define ID_AA64MMFR1_ECBHB_IMPL (0x1ULL << ID_AA64MMFR1_ECBHB_SHIFT)
/* ID_AA64MMFR2_EL1 */
#define ID_AA64MMFR2_MASK 0xffff0fffffffffffULL
#define ID_AA64MMFR2_CCIDX_SHIFT 20
#define ID_AA64MMFR2_CCIDX_MASK (0xfULL << ID_AA64MMFR2_CCIDX_SHIFT)
#define ID_AA64MMFR2_CCIDX(x) ((x) & ID_AA64MMFR2_CCIDX_MASK)
#define ID_AA64MMFR2_CCIDX_IMPL (0x1ULL << ID_AA64MMFR2_CCIDX_SHIFT)
#define ID_AA64MMFR2_AT_SHIFT 32
#define ID_AA64MMFR2_AT_MASK (0xfULL << ID_AA64MMFR2_AT_SHIFT)
#define ID_AA64MMFR2_AT(x) ((x) & ID_AA64MMFR2_AT_MASK)
#define ID_AA64MMFR2_AT_NONE (0x0ULL << ID_AA64MMFR2_AT_SHIFT)
#define ID_AA64MMFR2_AT_IMPL (0x1ULL << ID_AA64MMFR2_AT_SHIFT)
#define ID_AA64MMFR2_IDS_SHIFT 36
#define ID_AA64MMFR2_IDS_MASK (0xfULL << ID_AA64MMFR2_IDS_SHIFT)
#define ID_AA64MMFR2_IDS(x) ((x) & ID_AA64MMFR2_IDS_MASK)
#define ID_AA64MMFR2_IDS_NONE (0x0ULL << ID_AA64MMFR2_IDS_SHIFT)
#define ID_AA64MMFR2_IDS_IMPL (0x1ULL << ID_AA64MMFR2_IDS_SHIFT)
/* ID_AA64PFR0_EL1 */
#define ID_AA64PFR0_MASK 0xff0fffffffffffffULL
#define ID_AA64PFR0_EL0_SHIFT 0
#define ID_AA64PFR0_EL0_MASK (0xfULL << ID_AA64PFR0_EL0_SHIFT)
#define ID_AA64PFR0_EL0(x) ((x) & ID_AA64PFR0_EL0_MASK)
#define ID_AA64PFR0_EL0_64 (0x1ULL << ID_AA64PFR0_EL0_SHIFT)
#define ID_AA64PFR0_EL0_64_32 (0x2ULL << ID_AA64PFR0_EL0_SHIFT)
#define ID_AA64PFR0_EL1_SHIFT 4
#define ID_AA64PFR0_EL1_MASK (0xfULL << ID_AA64PFR0_EL1_SHIFT)
#define ID_AA64PFR0_EL1(x) ((x) & ID_AA64PFR0_EL1_MASK)
#define ID_AA64PFR0_EL1_64 (0x1ULL << ID_AA64PFR0_EL1_SHIFT)
#define ID_AA64PFR0_EL1_64_32 (0x2ULL << ID_AA64PFR0_EL1_SHIFT)
#define ID_AA64PFR0_EL2_SHIFT 8
#define ID_AA64PFR0_EL2_MASK (0xfULL << ID_AA64PFR0_EL2_SHIFT)
#define ID_AA64PFR0_EL2(x) ((x) & ID_AA64PFR0_EL2_MASK)
#define ID_AA64PFR0_EL2_NONE (0x0ULL << ID_AA64PFR0_EL2_SHIFT)
#define ID_AA64PFR0_EL2_64 (0x1ULL << ID_AA64PFR0_EL2_SHIFT)
#define ID_AA64PFR0_EL2_64_32 (0x2ULL << ID_AA64PFR0_EL2_SHIFT)
#define ID_AA64PFR0_EL3_SHIFT 12
#define ID_AA64PFR0_EL3_MASK (0xfULL << ID_AA64PFR0_EL3_SHIFT)
#define ID_AA64PFR0_EL3(x) ((x) & ID_AA64PFR0_EL3_MASK)
#define ID_AA64PFR0_EL3_NONE (0x0ULL << ID_AA64PFR0_EL3_SHIFT)
#define ID_AA64PFR0_EL3_64 (0x1ULL << ID_AA64PFR0_EL3_SHIFT)
#define ID_AA64PFR0_EL3_64_32 (0x2ULL << ID_AA64PFR0_EL3_SHIFT)
#define ID_AA64PFR0_FP_SHIFT 16
#define ID_AA64PFR0_FP_MASK (0xfULL << ID_AA64PFR0_FP_SHIFT)
#define ID_AA64PFR0_FP(x) ((x) & ID_AA64PFR0_FP_MASK)
#define ID_AA64PFR0_FP_IMPL (0x0ULL << ID_AA64PFR0_FP_SHIFT)
#define ID_AA64PFR0_FP_HP (0x1ULL << ID_AA64PFR0_FP_SHIFT)
#define ID_AA64PFR0_FP_NONE (0xfULL << ID_AA64PFR0_FP_SHIFT)
#define ID_AA64PFR0_ADV_SIMD_SHIFT 20
#define ID_AA64PFR0_ADV_SIMD_MASK (0xfULL << ID_AA64PFR0_ADV_SIMD_SHIFT)
#define ID_AA64PFR0_ADV_SIMD(x) ((x) & ID_AA64PFR0_ADV_SIMD_MASK)
#define ID_AA64PFR0_ADV_SIMD_IMPL (0x0ULL << ID_AA64PFR0_ADV_SIMD_SHIFT)
#define ID_AA64PFR0_ADV_SIMD_HP (0x1ULL << ID_AA64PFR0_ADV_SIMD_SHIFT)
#define ID_AA64PFR0_ADV_SIMD_NONE (0xfULL << ID_AA64PFR0_ADV_SIMD_SHIFT)
#define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */
#define ID_AA64PFR0_GIC_SHIFT 24
#define ID_AA64PFR0_GIC_MASK (0xfULL << ID_AA64PFR0_GIC_SHIFT)
#define ID_AA64PFR0_GIC(x) ((x) & ID_AA64PFR0_GIC_MASK)
#define ID_AA64PFR0_GIC_CPUIF_NONE (0x0ULL << ID_AA64PFR0_GIC_SHIFT)
#define ID_AA64PFR0_GIC_CPUIF_EN (0x1ULL << ID_AA64PFR0_GIC_SHIFT)
#define ID_AA64PFR0_RAS_SHIFT 28
#define ID_AA64PFR0_RAS_MASK (0xfULL << ID_AA64PFR0_RAS_SHIFT)
#define ID_AA64PFR0_RAS(x) ((x) & ID_AA64PFR0_RAS_MASK)
#define ID_AA64PFR0_RAS_NONE (0x0ULL << ID_AA64PFR0_RAS_SHIFT)
#define ID_AA64PFR0_RAS_IMPL (0x1ULL << ID_AA64PFR0_RAS_SHIFT)
#define ID_AA64PFR0_RAS_IMPL_V1P1 (0x2ULL << ID_AA64PFR0_RAS_SHIFT)
#define ID_AA64PFR0_SVE_SHIFT 32
#define ID_AA64PFR0_SVE_MASK (0xfULL << ID_AA64PFR0_SVE_SHIFT)
#define ID_AA64PFR0_SVE(x) ((x) & ID_AA64PFR0_SVE_MASK)
#define ID_AA64PFR0_SVE_NONE (0x0ULL << ID_AA64PFR0_SVE_SHIFT)
#define ID_AA64PFR0_SVE_IMPL (0x1ULL << ID_AA64PFR0_SVE_SHIFT)
#define ID_AA64PFR0_SEL2_SHIFT 36
#define ID_AA64PFR0_SEL2_MASK (0xfULL << ID_AA64PFR0_SEL2_SHIFT)
#define ID_AA64PFR0_SEL2(x) ((x) & ID_AA64PFR0_SEL2_MASK)
#define ID_AA64PFR0_SEL2_NONE (0x0ULL << ID_AA64PFR0_SEL2_SHIFT)
#define ID_AA64PFR0_SEL2_IMPL (0x1ULL << ID_AA64PFR0_SEL2_SHIFT)
#define ID_AA64PFR0_MPAM_SHIFT 40
#define ID_AA64PFR0_MPAM_MASK (0xfULL << ID_AA64PFR0_MPAM_SHIFT)
#define ID_AA64PFR0_MPAM(x) ((x) & ID_AA64PFR0_MPAM_MASK)
#define ID_AA64PFR0_MPAM_NONE (0x0ULL << ID_AA64PFR0_MPAM_SHIFT)
#define ID_AA64PFR0_MPAM_IMPL (0x1ULL << ID_AA64PFR0_MPAM_SHIFT)
#define ID_AA64PFR0_AMU_SHIFT 44
#define ID_AA64PFR0_AMU_MASK (0xfULL << ID_AA64PFR0_AMU_SHIFT)
#define ID_AA64PFR0_AMU(x) ((x) & ID_AA64PFR0_AMU_MASK)
#define ID_AA64PFR0_AMU_NONE (0x0ULL << ID_AA64PFR0_AMU_SHIFT)
#define ID_AA64PFR0_AMU_IMPL (0x1ULL << ID_AA64PFR0_AMU_SHIFT)
#define ID_AA64PFR0_AMU_IMPL_V1P1 (0x2ULL << ID_AA64PFR0_AMU_SHIFT)
#define ID_AA64PFR0_DIT_SHIFT 48
#define ID_AA64PFR0_DIT_MASK (0xfULL << ID_AA64PFR0_DIT_SHIFT)
#define ID_AA64PFR0_DIT(x) ((x) & ID_AA64PFR0_DIT_MASK)
#define ID_AA64PFR0_DIT_UNKNOWN (0x0ULL << ID_AA64PFR0_DIT_SHIFT)
#define ID_AA64PFR0_DIT_IMPL (0x1ULL << ID_AA64PFR0_DIT_SHIFT)
#define ID_AA64PFR0_CSV2_SHIFT 56
#define ID_AA64PFR0_CSV2_MASK (0xfULL << ID_AA64PFR0_CSV2_SHIFT)
#define ID_AA64PFR0_CSV2(x) ((x) & ID_AA64PFR0_CSV2_MASK)
#define ID_AA64PFR0_CSV2_UNKNOWN (0x0ULL << ID_AA64PFR0_CSV2_SHIFT)
#define ID_AA64PFR0_CSV2_IMPL (0x1ULL << ID_AA64PFR0_CSV2_SHIFT)
#define ID_AA64PFR0_CSV2_SCXT (0x2ULL << ID_AA64PFR0_CSV2_SHIFT)
#define ID_AA64PFR0_CSV2_HCXT (0x3ULL << ID_AA64PFR0_CSV2_SHIFT)
#define ID_AA64PFR0_CSV3_SHIFT 60
#define ID_AA64PFR0_CSV3_MASK (0xfULL << ID_AA64PFR0_CSV3_SHIFT)
#define ID_AA64PFR0_CSV3(x) ((x) & ID_AA64PFR0_CSV3_MASK)
#define ID_AA64PFR0_CSV3_UNKNOWN (0x0ULL << ID_AA64PFR0_CSV3_SHIFT)
#define ID_AA64PFR0_CSV3_IMPL (0x1ULL << ID_AA64PFR0_CSV3_SHIFT)
/* ID_AA64PFR1_EL1 */
#define ID_AA64PFR1_MASK 0x000000000000ffffULL
#define ID_AA64PFR1_BT_SHIFT 0
#define ID_AA64PFR1_BT_MASK (0xfULL << ID_AA64PFR1_BT_SHIFT)
#define ID_AA64PFR1_BT(x) ((x) & ID_AA64PFR1_BT_MASK)
#define ID_AA64PFR1_BT_NONE (0x0ULL << ID_AA64PFR1_BT_SHIFT)
#define ID_AA64PFR1_BT_IMPL (0x1ULL << ID_AA64PFR1_BT_SHIFT)
#define ID_AA64PFR1_SSBS_SHIFT 4
#define ID_AA64PFR1_SSBS_MASK (0xfULL << ID_AA64PFR1_SSBS_SHIFT)
#define ID_AA64PFR1_SSBS(x) ((x) & ID_AA64PFR1_SSBS_MASK)
#define ID_AA64PFR1_SSBS_NONE (0x0ULL << ID_AA64PFR1_SSBS_SHIFT)
#define ID_AA64PFR1_SSBS_PSTATE (0x1ULL << ID_AA64PFR1_SSBS_SHIFT)
#define ID_AA64PFR1_SSBS_PSTATE_MSR (0x2ULL << ID_AA64PFR1_SSBS_SHIFT)
#define ID_AA64PFR1_MTE_SHIFT 8
#define ID_AA64PFR1_MTE_MASK (0xfULL << ID_AA64PFR1_MTE_SHIFT)
#define ID_AA64PFR1_MTE(x) ((x) & ID_AA64PFR1_MTE_MASK)
#define ID_AA64PFR1_MTE_NONE (0x0ULL << ID_AA64PFR1_MTE_SHIFT)
#define ID_AA64PFR1_MTE_IMPL (0x1ULL << ID_AA64PFR1_MTE_SHIFT)
#define ID_AA64PFR1_RAS_FRAC_SHIFT 12
#define ID_AA64PFR1_RAS_FRAC_MASK (0xfULL << ID_AA64PFR1_RAS_FRAC_SHIFT)
#define ID_AA64PFR1_RAS_FRAC(x) ((x) & ID_AA64PFR1_RAS_FRAC_MASK)
#define ID_AA64PFR1_RAS_FRAC_NONE (0x0ULL << ID_AA64PFR1_RAS_FRAC_SHIFT)
#define ID_AA64PFR1_RAS_FRAC_IMPL (0x1ULL << ID_AA64PFR1_RAS_FRAC_SHIFT)
/* ID_AA64ZFR0_EL1 */
#define ID_AA64ZFR0_MASK 0x0ff0ff0f00ff00ffULL
#define ID_AA64ZFR0_SVEVER_SHIFT 0
#define ID_AA64ZFR0_SVEVER_MASK (0xfULL << ID_AA64ZFR0_SVEVER_SHIFT)
#define ID_AA64ZFR0_SVEVER(x) ((x) & ID_AA64ZFR0_SVEVER_MASK)
#define ID_AA64ZFR0_SVEVER_SVE1 (0x0ULL << ID_AA64ZFR0_SVEVER_SHIFT)
#define ID_AA64ZFR0_SVEVER_SVE2 (0x1ULL << ID_AA64ZFR0_SVEVER_SHIFT)
#define ID_AA64ZFR0_SVEVER_SVE2P1 (0x2ULL << ID_AA64ZFR0_SVEVER_SHIFT)
#define ID_AA64ZFR0_AES_SHIFT 4
#define ID_AA64ZFR0_AES_MASK (0xfULL << ID_AA64ZFR0_AES_SHIFT)
#define ID_AA64ZFR0_AES(x) ((x) & ID_AA64ZFR0_AES_MASK)
#define ID_AA64ZFR0_AES_NONE (0x0ULL << ID_AA64ZFR0_AES_SHIFT)
#define ID_AA64ZFR0_AES_BASE (0x1ULL << ID_AA64ZFR0_AES_SHIFT)
#define ID_AA64ZFR0_AES_PMULL (0x2ULL << ID_AA64ZFR0_AES_SHIFT)
#define ID_AA64ZFR0_BITPERM_SHIFT 16
#define ID_AA64ZFR0_BITPERM_MASK (0xfULL << ID_AA64ZFR0_BITPERM_SHIFT)
#define ID_AA64ZFR0_BITPERM(x) ((x) & ID_AA64ZFR0_BITPERM_MASK)
#define ID_AA64ZFR0_BITPERM_NONE (0x0ULL << ID_AA64ZFR0_BITPERM_SHIFT)
#define ID_AA64ZFR0_BITPERM_IMPL (0x1ULL << ID_AA64ZFR0_BITPERM_SHIFT)
#define ID_AA64ZFR0_BF16_SHIFT 20
#define ID_AA64ZFR0_BF16_MASK (0xfULL << ID_AA64ZFR0_BF16_SHIFT)
#define ID_AA64ZFR0_BF16(x) ((x) & ID_AA64ZFR0_BF16_MASK)
#define ID_AA64ZFR0_BF16_NONE (0x0ULL << ID_AA64ZFR0_BF16_SHIFT)
#define ID_AA64ZFR0_BF16_BASE (0x1ULL << ID_AA64ZFR0_BF16_SHIFT)
#define ID_AA64ZFR0_BF16_EBF (0x2ULL << ID_AA64ZFR0_BF16_SHIFT)
#define ID_AA64ZFR0_SHA3_SHIFT 32
#define ID_AA64ZFR0_SHA3_MASK (0xfULL << ID_AA64ZFR0_SHA3_SHIFT)
#define ID_AA64ZFR0_SHA3(x) ((x) & ID_AA64ZFR0_SHA3_MASK)
#define ID_AA64ZFR0_SHA3_NONE (0x0ULL << ID_AA64ZFR0_SHA3_SHIFT)
#define ID_AA64ZFR0_SHA3_IMPL (0x1ULL << ID_AA64ZFR0_SHA3_SHIFT)
#define ID_AA64ZFR0_SM4_SHIFT 40
#define ID_AA64ZFR0_SM4_MASK (0xfULL << ID_AA64ZFR0_SM4_SHIFT)
#define ID_AA64ZFR0_SM4(x) ((x) & ID_AA64ZFR0_SM4_MASK)
#define ID_AA64ZFR0_SM4_NONE (0x0ULL << ID_AA64ZFR0_SM4_SHIFT)
#define ID_AA64ZFR0_SM4_IMPL (0x1ULL << ID_AA64ZFR0_SM4_SHIFT)
#define ID_AA64ZFR0_I8MM_SHIFT 44
#define ID_AA64ZFR0_I8MM_MASK (0xfULL << ID_AA64ZFR0_I8MM_SHIFT)
#define ID_AA64ZFR0_I8MM(x) ((x) & ID_AA64ZFR0_I8MM_MASK)
#define ID_AA64ZFR0_I8MM_NONE (0x0ULL << ID_AA64ZFR0_I8MM_SHIFT)
#define ID_AA64ZFR0_I8MM_IMPL (0x1ULL << ID_AA64ZFR0_I8MM_SHIFT)
#define ID_AA64ZFR0_F32MM_SHIFT 52
#define ID_AA64ZFR0_F32MM_MASK (0xfULL << ID_AA64ZFR0_F32MM_SHIFT)
#define ID_AA64ZFR0_F32MM(x) ((x) & ID_AA64ZFR0_F32MM_MASK)
#define ID_AA64ZFR0_F32MM_NONE (0x0ULL << ID_AA64ZFR0_F32MM_SHIFT)
#define ID_AA64ZFR0_F32MM_IMPL (0x1ULL << ID_AA64ZFR0_F32MM_SHIFT)
#define ID_AA64ZFR0_F64MM_SHIFT 56
#define ID_AA64ZFR0_F64MM_MASK (0xfULL << ID_AA64ZFR0_F64MM_SHIFT)
#define ID_AA64ZFR0_F64MM(x) ((x) & ID_AA64ZFR0_F64MM_MASK)
#define ID_AA64ZFR0_F64MM_NONE (0x0ULL << ID_AA64ZFR0_F64MM_SHIFT)
#define ID_AA64ZFR0_F64MM_IMPL (0x1ULL << ID_AA64ZFR0_F64MM_SHIFT)
/* MAIR_EL1 - Memory Attribute Indirection Register */
#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8))
#define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
#define MAIR_DEVICE_nGnRnE 0x00
#define MAIR_NORMAL_NC 0x44
#define MAIR_NORMAL_WT 0x88
#define MAIR_NORMAL_WB 0xff
/* PAR_EL1 - Physical Address Register */
#define PAR_F_SHIFT 0
#define PAR_F (0x1 << PAR_F_SHIFT)
#define PAR_SUCCESS(x) (((x) & PAR_F) == 0)
/* When PAR_F == 0 (success) */
#define PAR_SH_SHIFT 7
#define PAR_SH_MASK (0x3 << PAR_SH_SHIFT)
#define PAR_NS_SHIFT 9
#define PAR_NS_MASK (0x3 << PAR_NS_SHIFT)
#define PAR_PA_SHIFT 12
#define PAR_PA_MASK 0x0000fffffffff000
#define PAR_ATTR_SHIFT 56
#define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT)
/* When PAR_F == 1 (aborted) */
#define PAR_FST_SHIFT 1
#define PAR_FST_MASK (0x3f << PAR_FST_SHIFT)
#define PAR_PTW_SHIFT 8
#define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT)
#define PAR_S_SHIFT 9
#define PAR_S_MASK (0x1 << PAR_S_SHIFT)
/* SCTLR_EL1 - System Control Register */
#define SCTLR_RES0 0xffffffffc8222400 /* Reserved, write 0 */
#define SCTLR_RES1 0x0000000030d00800 /* Reserved, write 1 */
#define SCTLR_M 0x0000000000000001
#define SCTLR_A 0x0000000000000002
#define SCTLR_C 0x0000000000000004
#define SCTLR_SA 0x0000000000000008
#define SCTLR_SA0 0x0000000000000010
#define SCTLR_CP15BEN 0x0000000000000020
#define SCTLR_THEE 0x0000000000000040
#define SCTLR_ITD 0x0000000000000080
#define SCTLR_SED 0x0000000000000100
#define SCTLR_UMA 0x0000000000000200
#define SCTLR_I 0x0000000000001000
#define SCTLR_EnDB 0x0000000000002000
#define SCTLR_DZE 0x0000000000004000
#define SCTLR_UCT 0x0000000000008000
#define SCTLR_nTWI 0x0000000000010000
#define SCTLR_nTWE 0x0000000000040000
#define SCTLR_WXN 0x0000000000080000
#define SCTLR_SPAN 0x0000000000800000
#define SCTLR_EOE 0x0000000001000000
#define SCTLR_EE 0x0000000002000000
#define SCTLR_UCI 0x0000000004000000
#define SCTLR_EnDA 0x0000000008000000
#define SCTLR_EnIB 0x0000000040000000
#define SCTLR_EnIA 0x0000000080000000
#define SCTLR_BT0 0x0000000800000000
#define SCTLR_BT1 0x0000001000000000
#define SCTLR_EPAN 0x0200000000000000
/* SPSR_EL1 */
/*
* When the exception is taken in AArch64:
* M[4] is 0 for AArch64 mode
* M[3:2] is the exception level
* M[1] is unused
* M[0] is the SP select:
* 0: always SP0
* 1: current ELs SP
*/
#define PSR_M_EL0t 0x00000000
#define PSR_M_EL1t 0x00000004
#define PSR_M_EL1h 0x00000005
#define PSR_M_EL2t 0x00000008
#define PSR_M_EL2h 0x00000009
#define PSR_M_MASK 0x0000001f
#define PSR_F 0x00000040
#define PSR_I 0x00000080
#define PSR_A 0x00000100
#define PSR_D 0x00000200
#define PSR_BTYPE 0x00000c00
#define PSR_SSBS 0x00001000
#define PSR_IL 0x00100000
#define PSR_SS 0x00200000
#define PSR_PAN 0x00400000
#define PSR_UAO 0x00800000
#define PSR_DIT 0x01000000
#define PSR_TCO 0x02000000
#define PSR_V 0x10000000
#define PSR_C 0x20000000
#define PSR_Z 0x40000000
#define PSR_N 0x80000000
/* TCR_EL1 - Translation Control Register */
#define TCR_AS (1UL << 36)
#define TCR_IPS_SHIFT 32
#define TCR_IPS_32BIT (0UL << TCR_IPS_SHIFT)
#define TCR_IPS_36BIT (1UL << TCR_IPS_SHIFT)
#define TCR_IPS_40BIT (2UL << TCR_IPS_SHIFT)
#define TCR_IPS_42BIT (3UL << TCR_IPS_SHIFT)
#define TCR_IPS_44BIT (4UL << TCR_IPS_SHIFT)
#define TCR_IPS_48BIT (5UL << TCR_IPS_SHIFT)
#define TCR_TG1_SHIFT 30
#define TCR_TG1_16K (1UL << TCR_TG1_SHIFT)
#define TCR_TG1_4K (2UL << TCR_TG1_SHIFT)
#define TCR_TG1_64K (3UL << TCR_TG1_SHIFT)
#define TCR_SH1_SHIFT 28
#define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT)
#define TCR_ORGN1_SHIFT 26
#define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT)
#define TCR_IRGN1_SHIFT 24
#define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT)
#define TCR_A1 (1UL << 22)
#define TCR_TG0_SHIFT 14
#define TCR_TG0_4K (0UL << TCR_TG0_SHIFT)
#define TCR_TG0_64K (1UL << TCR_TG0_SHIFT)
#define TCR_TG0_16K (2UL << TCR_TG0_SHIFT)
#define TCR_SH0_SHIFT 12
#define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT)
#define TCR_ORGN0_SHIFT 10
#define TCR_ORGN0_WBWA (0x1UL << TCR_ORGN0_SHIFT)
#define TCR_IRGN0_SHIFT 8
#define TCR_IRGN0_WBWA (0x1UL << TCR_IRGN0_SHIFT)
#define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\
(TCR_ORGN0_WBWA | TCR_ORGN1_WBWA))
#define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS)
#define TCR_T1SZ_SHIFT 16
#define TCR_T0SZ_SHIFT 0
#define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT)
#define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT)
#define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x))
/* Monitor Debug System Control Register */
#define DBG_MDSCR_SS (0x1 << 0)
#define DBG_MDSCR_TDCC (0x1 << 12)
#define DBG_MDSCR_KDE (0x1 << 13)
#define DBG_MDSCR_MDE (0x1 << 15)
/* Performance Monitoring Counters */
#define PMCR_E (1 << 0) /* Enable all counters */
#define PMCR_P (1 << 1) /* Reset all counters */
#define PMCR_C (1 << 2) /* Clock counter reset */
#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */
#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */
#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
#define PMCR_LC (1 << 6) /* Long cycle count enable */
#define PMCR_IMP_SHIFT 24 /* Implementer code */
#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT)
#define PMCR_IDCODE_SHIFT 16 /* Identification code */
#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT)
#define PMCR_IDCODE_CORTEX_A57 0x01
#define PMCR_IDCODE_CORTEX_A72 0x02
#define PMCR_IDCODE_CORTEX_A53 0x03
#define PMCR_N_SHIFT 11 /* Number of counters implemented */
#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT)
#define I_bit (1 << 7) /* IRQ disable */
#define F_bit 0 /* FIQ disable - not actually used */
#endif /* !_MACHINE_ARMREG_H_ */

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/* $OpenBSD: asm.h,v 1.12 2023/03/27 19:02:48 kettenis Exp $ */
/* $NetBSD: asm.h,v 1.4 2001/07/16 05:43:32 matt Exp $ */
/*
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* William Jolitz.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)asm.h 5.5 (Berkeley) 5/7/91
*/
#ifndef _MACHINE_ASM_H_
#define _MACHINE_ASM_H_
#define _C_LABEL(x) x
#define _ASM_LABEL(x) x
#ifdef __STDC__
# define __CONCAT(x,y) x ## y
# define __STRING(x) #x
#else
# define __CONCAT(x,y) x/**/y
# define __STRING(x) "x"
#endif
#ifndef _ALIGN_TEXT
# define _ALIGN_TEXT .align 0
#endif
/*
* gas/arm uses @ as a single comment character and thus cannot be used here
* Instead it recognised the # instead of an @ symbols in .type directives
* We define a couple of macros so that assembly code will not be dependant
* on one or the other.
*/
#define _ASM_TYPE_FUNCTION #function
#define _ASM_TYPE_OBJECT #object
/* NB == No Binding: use .globl or .weak as necessary */
#define _ENTRY_NB(x) \
.text; _ALIGN_TEXT; .type x,_ASM_TYPE_FUNCTION; x:
#define _ENTRY(x) .globl x; _ENTRY_NB(x)
#if defined(PROF) || defined(GPROF)
# define _PROF_PROLOGUE \
stp x29, x30, [sp, #-16]!; \
mov fp, sp; \
bl __mcount; \
ldp x29, x30, [sp], #16;
#else
# define _PROF_PROLOGUE
#endif
#if defined(_RET_PROTECTOR)
# define RETGUARD_CALC_COOKIE(reg) \
eor reg, reg, x30
# define RETGUARD_LOAD_RANDOM(x, reg) \
adrp reg, __CONCAT(__retguard_, x); \
ldr reg, [reg, :lo12:__CONCAT(__retguard_, x)]
# define RETGUARD_SETUP(x, reg) \
RETGUARD_SYMBOL(x); \
RETGUARD_LOAD_RANDOM(x, reg); \
RETGUARD_CALC_COOKIE(reg)
# define RETGUARD_CHECK(x, reg) \
RETGUARD_CALC_COOKIE(reg); \
RETGUARD_LOAD_RANDOM(x, x9); \
subs reg, reg, x9; \
cbz reg, 66f; \
brk #0x1; \
66:
# define RETGUARD_PUSH(reg) \
str reg, [sp, #-16]!
# define RETGUARD_POP(reg) \
ldr reg, [sp, #16]!
# define RETGUARD_SYMBOL(x) \
.ifndef __CONCAT(__retguard_, x); \
.hidden __CONCAT(__retguard_, x); \
.type __CONCAT(__retguard_, x),@object; \
.pushsection .openbsd.randomdata.retguard,"aw",@progbits; \
.weak __CONCAT(__retguard_, x); \
.p2align 3; \
__CONCAT(__retguard_, x): ; \
.xword 0; \
.size __CONCAT(__retguard_, x), 8; \
.popsection; \
.endif
#else
# define RETGUARD_CALC_COOKIE(reg)
# define RETGUARD_LOAD_RANDOM(x, reg)
# define RETGUARD_SETUP(x, reg)
# define RETGUARD_CHECK(x, reg)
# define RETGUARD_PUSH(reg)
# define RETGUARD_POP(reg)
# define RETGUARD_SYMBOL(x)
#endif
#define ENTRY(y) _ENTRY(y); bti c; _PROF_PROLOGUE
#define ENTRY_NP(y) _ENTRY(y); bti c
#define ENTRY_NB(y) _ENTRY_NB(y); bti c; _PROF_PROLOGUE
#define ASENTRY(y) _ENTRY(y); bti c; _PROF_PROLOGUE
#define ASENTRY_NP(y) _ENTRY(y); bti c
#define END(y) .size y, . - y
#define EENTRY(sym) .globl sym; sym:
#define EEND(sym)
#ifdef __PIC__
#define PIC_SYM(x,y) x(y)
#else
#define PIC_SYM(x,y) x
#endif
#define STRONG_ALIAS(alias,sym) \
.global alias; \
alias = sym
#define WEAK_ALIAS(alias,sym) \
.weak alias; \
alias = sym
#endif /* !_MACHINE_ASM_H_ */

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lib/libc/include/aarch64-openbsd-none/arm64/atomic.h vendored Normal file
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/* $OpenBSD: atomic.h,v 1.4 2022/08/29 02:01:18 jsg Exp $ */
/* Public Domain */
#ifndef _MACHINE_ATOMIC_H_
#define _MACHINE_ATOMIC_H_
#define __membar(_f) do { __asm volatile(_f ::: "memory"); } while (0)
#define membar_enter() __membar("dmb sy")
#define membar_exit() __membar("dmb sy")
#define membar_producer() __membar("dmb st")
#define membar_consumer() __membar("dmb ld")
#define membar_sync() __membar("dmb sy")
#if defined(_KERNEL)
/* virtio needs MP membars even on SP kernels */
#define virtio_membar_producer() __membar("dmb st")
#define virtio_membar_consumer() __membar("dmb ld")
#define virtio_membar_sync() __membar("dmb sy")
/*
* Set bits
* *p = *p | v
*/
static inline void
atomic_setbits_int(volatile unsigned int *p, unsigned int v)
{
unsigned int modified, tmp;
__asm volatile (
"1: ldxr %w0, [%x3] \n\t"
" orr %w0, %w0, %w2 \n\t"
" stxr %w1, %w0, [%x3] \n\t"
" cbnz %w1, 1b \n\t"
: "=&r" (tmp), "=&r" (modified)
: "r" (v), "r" (p)
: "memory", "cc"
);
}
/*
* Clear bits
* *p = *p & (~v)
*/
static inline void
atomic_clearbits_int(volatile unsigned int *p, unsigned int v)
{
unsigned int modified, tmp;
__asm volatile (
"1: ldxr %w0, [%x3] \n\t"
" bic %w0, %w0, %w2 \n\t"
" stxr %w1, %w0, [%x3] \n\t"
" cbnz %w1, 1b \n\t"
: "=&r" (tmp), "=&r" (modified)
: "r" (v), "r" (p)
: "memory", "cc"
);
}
#endif /* defined(_KERNEL) */
#endif /* _MACHINE_ATOMIC_H_ */

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/* $OpenBSD: bootconfig.h,v 1.4 2023/12/05 05:27:26 jsg Exp $ */
/* $NetBSD: bootconfig.h,v 1.2 2001/06/21 22:08:28 chris Exp $ */
/*-
* Copyright (c) 2013 Andrew Turner <andrew@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD: head/sys/arm64/include/machdep.h 281494 2015-04-13 14:43:10Z andrew $
*/
#ifndef _MACHINE_BOOTCONFIG_H_
#define _MACHINE_BOOTCONFIG_H_
struct arm64_bootparams {
vaddr_t modulep;
vaddr_t kern_l1pt; /* L1 page table for the kernel */
uint64_t kern_delta;
vaddr_t kern_stack;
void *arg0; // passed to kernel in R0
void *arg1; // passed to kernel in R1
void *arg2; // passed to kernel in R2
};
void initarm(struct arm64_bootparams *);
#endif /* _MACHINE_BOOTCONFIG_H_ */

536
lib/libc/include/aarch64-openbsd-none/arm64/bus.h vendored Normal file
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@ -0,0 +1,536 @@
/* $OpenBSD: bus.h,v 1.11 2024/11/18 05:32:39 jsg Exp $ */
/*
* Copyright (c) 2003-2004 Opsycon AB Sweden. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _MACHINE_BUS_H_
#define _MACHINE_BUS_H_
#ifdef __STDC__
#define CAT(a,b) a##b
#define CAT3(a,b,c) a##b##c
#else
#define CAT(a,b) a/**/b
#define CAT3(a,b,c) a/**/b/**/c
#endif
/*
* Bus access types.
*/
struct bus_space;
typedef u_long bus_addr_t;
typedef u_long bus_size_t;
typedef u_long bus_space_handle_t;
typedef struct bus_space *bus_space_tag_t;
typedef struct bus_space bus_space_t;
struct bus_space {
bus_addr_t bus_base;
void *bus_private;
u_int8_t (*_space_read_1)(bus_space_tag_t , bus_space_handle_t,
bus_size_t);
void (*_space_write_1)(bus_space_tag_t , bus_space_handle_t,
bus_size_t, u_int8_t);
u_int16_t (*_space_read_2)(bus_space_tag_t , bus_space_handle_t,
bus_size_t);
void (*_space_write_2)(bus_space_tag_t , bus_space_handle_t,
bus_size_t, u_int16_t);
u_int32_t (*_space_read_4)(bus_space_tag_t , bus_space_handle_t,
bus_size_t);
void (*_space_write_4)(bus_space_tag_t , bus_space_handle_t,
bus_size_t, u_int32_t);
u_int64_t (*_space_read_8)(bus_space_tag_t , bus_space_handle_t,
bus_size_t);
void (*_space_write_8)(bus_space_tag_t , bus_space_handle_t,
bus_size_t, u_int64_t);
void (*_space_read_raw_2)(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, u_int8_t *, bus_size_t);
void (*_space_write_raw_2)(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, const u_int8_t *, bus_size_t);
void (*_space_read_raw_4)(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, u_int8_t *, bus_size_t);
void (*_space_write_raw_4)(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, const u_int8_t *, bus_size_t);
void (*_space_read_raw_8)(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, u_int8_t *, bus_size_t);
void (*_space_write_raw_8)(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, const u_int8_t *, bus_size_t);
int (*_space_map)(bus_space_tag_t , bus_addr_t,
bus_size_t, int, bus_space_handle_t *);
void (*_space_unmap)(bus_space_tag_t, bus_space_handle_t,
bus_size_t);
int (*_space_subregion)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, bus_size_t, bus_space_handle_t *);
void * (*_space_vaddr)(bus_space_tag_t, bus_space_handle_t);
paddr_t (*_space_mmap)(bus_space_tag_t, bus_addr_t, off_t,
int, int);
};
#define bus_space_read_1(t, h, o) (*(t)->_space_read_1)((t), (h), (o))
#define bus_space_read_2(t, h, o) (*(t)->_space_read_2)((t), (h), (o))
#define bus_space_read_4(t, h, o) (*(t)->_space_read_4)((t), (h), (o))
#define bus_space_read_8(t, h, o) (*(t)->_space_read_8)((t), (h), (o))
#define bus_space_write_1(t, h, o, v) (*(t)->_space_write_1)((t), (h), (o), (v))
#define bus_space_write_2(t, h, o, v) (*(t)->_space_write_2)((t), (h), (o), (v))
#define bus_space_write_4(t, h, o, v) (*(t)->_space_write_4)((t), (h), (o), (v))
#define bus_space_write_8(t, h, o, v) (*(t)->_space_write_8)((t), (h), (o), (v))
#define bus_space_read_raw_2(t, h, o) \
(*(t)->_space_read_2)((t), (h), (o))
#define bus_space_read_raw_4(t, h, o) \
(*(t)->_space_read_4)((t), (h), (o))
#define bus_space_read_raw_8(t, h, o) \
(*(t)->_space_read_8)((t), (h), (o))
#define bus_space_write_raw_2(t, h, o, v) \
(*(t)->_space_write_2)((t), (h), (o), (v))
#define bus_space_write_raw_4(t, h, o, v) \
(*(t)->_space_write_4)((t), (h), (o), (v))
#define bus_space_write_raw_8(t, h, o, v) \
(*(t)->_space_write_8)((t), (h), (o), (v))
#define bus_space_read_raw_multi_2(t, h, a, b, l) \
(*(t)->_space_read_raw_2)((t), (h), (a), (b), (l))
#define bus_space_read_raw_multi_4(t, h, a, b, l) \
(*(t)->_space_read_raw_4)((t), (h), (a), (b), (l))
#define bus_space_read_raw_multi_8(t, h, a, b, l) \
(*(t)->_space_read_raw_8)((t), (h), (a), (b), (l))
#define bus_space_write_raw_multi_2(t, h, a, b, l) \
(*(t)->_space_write_raw_2)((t), (h), (a), (b), (l))
#define bus_space_write_raw_multi_4(t, h, a, b, l) \
(*(t)->_space_write_raw_4)((t), (h), (a), (b), (l))
#define bus_space_write_raw_multi_8(t, h, a, b, l) \
(*(t)->_space_write_raw_8)((t), (h), (a), (b), (l))
#define bus_space_map(t, o, s, c, p) (*(t)->_space_map)((t), (o), (s), (c), (p))
#define bus_space_unmap(t, h, s) (*(t)->_space_unmap)((t), (h), (s))
#define bus_space_subregion(t, h, o, s, p) \
(*(t)->_space_subregion)((t), (h), (o), (s), (p))
#define BUS_SPACE_MAP_CACHEABLE 0x01
#define BUS_SPACE_MAP_POSTED 0x02
#define BUS_SPACE_MAP_LINEAR 0x04
#define BUS_SPACE_MAP_PREFETCHABLE 0x08
extern bus_space_t arm64_bs_tag;
#define bus_space_vaddr(t, h) (*(t)->_space_vaddr)((t), (h))
#define bus_space_mmap(t, a, o, p, f) \
(*(t)->_space_mmap)((t), (a), (o), (p), (f))
/*----------------------------------------------------------------------------*/
#define bus_space_read_multi(n,m) \
static __inline void \
CAT(bus_space_read_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
bus_size_t o, CAT3(u_int,m,_t) *x, size_t cnt) \
{ \
while (cnt--) \
*x++ = CAT(bus_space_read_,n)(bst, bsh, o); \
}
bus_space_read_multi(1,8)
bus_space_read_multi(2,16)
bus_space_read_multi(4,32)
bus_space_read_multi(8,64)
/*----------------------------------------------------------------------------*/
#define bus_space_read_region(n,m) \
static __inline void \
CAT(bus_space_read_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
bus_addr_t ba, CAT3(u_int,m,_t) *x, size_t cnt) \
{ \
while (cnt--) { \
*x++ = CAT(bus_space_read_,n)(bst, bsh, ba); \
ba += (n); \
} \
}
bus_space_read_region(1,8)
bus_space_read_region(2,16)
bus_space_read_region(4,32)
bus_space_read_region(8,64)
/*----------------------------------------------------------------------------*/
#define bus_space_read_raw_region(n,m) \
static __inline void \
CAT(bus_space_read_raw_region_,n)(bus_space_tag_t bst, \
bus_space_handle_t bsh, \
bus_addr_t ba, u_int8_t *x, size_t cnt) \
{ \
cnt >>= ((n) >> 1); \
while (cnt--) { \
CAT(bus_space_read_raw_multi_,n)(bst, bsh, ba, x, (n)); \
ba += (n); \
x += (n); \
} \
}
bus_space_read_raw_region(2,16)
bus_space_read_raw_region(4,32)
bus_space_read_raw_region(8,64)
/*----------------------------------------------------------------------------*/
#define bus_space_write_multi(n,m) \
static __inline void \
CAT(bus_space_write_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
bus_size_t o, const CAT3(u_int,m,_t) *x, size_t cnt) \
{ \
while (cnt--) \
CAT(bus_space_write_,n)(bst, bsh, o, *x++); \
}
bus_space_write_multi(1,8)
bus_space_write_multi(2,16)
bus_space_write_multi(4,32)
bus_space_write_multi(8,64)
/*----------------------------------------------------------------------------*/
#define bus_space_write_region(n,m) \
static __inline void \
CAT(bus_space_write_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
bus_addr_t ba, const CAT3(u_int,m,_t) *x, size_t cnt) \
{ \
while (cnt--) { \
CAT(bus_space_write_,n)(bst, bsh, ba, *x++); \
ba += (n); \
} \
}
bus_space_write_region(1,8)
bus_space_write_region(2,16)
bus_space_write_region(4,32)
bus_space_write_region(8,64)
/*----------------------------------------------------------------------------*/
#define bus_space_write_raw_region(n,m) \
static __inline void \
CAT(bus_space_write_raw_region_,n)(bus_space_tag_t bst, \
bus_space_handle_t bsh, \
bus_addr_t ba, const u_int8_t *x, size_t cnt) \
{ \
cnt >>= ((n) >> 1); \
while (cnt--) { \
CAT(bus_space_write_raw_multi_,n)(bst, bsh, ba, x, (n)); \
ba += (n); \
x += (n); \
} \
}
bus_space_write_raw_region(2,16)
bus_space_write_raw_region(4,32)
bus_space_write_raw_region(8,64)
/*----------------------------------------------------------------------------*/
#define bus_space_set_region(n,m) \
static __inline void \
CAT(bus_space_set_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
bus_addr_t ba, CAT3(u_int,m,_t) x, size_t cnt) \
{ \
while (cnt--) { \
CAT(bus_space_write_,n)(bst, bsh, ba, x); \
ba += (n); \
} \
}
bus_space_set_region(1,8)
bus_space_set_region(2,16)
bus_space_set_region(4,32)
bus_space_set_region(8,64)
/*----------------------------------------------------------------------------*/
static __inline void
bus_space_copy_1(void *v, bus_space_handle_t h1, bus_size_t o1,
bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
{
char *s = (char *)(h1 + o1);
char *d = (char *)(h2 + o2);
while (c--)
*d++ = *s++;
}
static __inline void
bus_space_copy_2(void *v, bus_space_handle_t h1, bus_size_t o1,
bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
{
short *s = (short *)(h1 + o1);
short *d = (short *)(h2 + o2);
while (c--)
*d++ = *s++;
}
static __inline void
bus_space_copy_4(void *v, bus_space_handle_t h1, bus_size_t o1,
bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
{
int *s = (int *)(h1 + o1);
int *d = (int *)(h2 + o2);
while (c--)
*d++ = *s++;
}
static __inline void
bus_space_copy_8(void *v, bus_space_handle_t h1, bus_size_t o1,
bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
{
int64_t *s = (int64_t *)(h1 + o1);
int64_t *d = (int64_t *)(h2 + o2);
while (c--)
*d++ = *s++;
}
/*----------------------------------------------------------------------------*/
/*
* Bus read/write barrier methods.
*
* void bus_space_barrier(bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset,
* bus_size_t len, int flags);
*
*/
static inline void
bus_space_barrier(bus_space_tag_t t, bus_space_handle_t h, bus_size_t offset,
bus_size_t length, int flags)
{
__asm__ volatile ("dsb sy" ::: "memory");
}
#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
#define BUS_DMA_WAITOK 0x0000
#define BUS_DMA_NOWAIT 0x0001
#define BUS_DMA_ALLOCNOW 0x0002
#define BUS_DMA_COHERENT 0x0008
#define BUS_DMA_BUS1 0x0010 /* placeholders for bus functions... */
#define BUS_DMA_BUS2 0x0020
#define BUS_DMA_BUS3 0x0040
#define BUS_DMA_BUS4 0x0080
#define BUS_DMA_READ 0x0100 /* mapping is device -> memory only */
#define BUS_DMA_WRITE 0x0200 /* mapping is memory -> device only */
#define BUS_DMA_STREAMING 0x0400 /* hint: sequential, unidirectional */
#define BUS_DMA_ZERO 0x0800 /* zero memory in dmamem_alloc */
#define BUS_DMA_NOCACHE 0x1000
#define BUS_DMA_64BIT 0x2000 /* device handles 64bit dva */
#define BUS_DMA_FIXED 0x4000 /* place mapping at specified dva */
/* Forwards needed by prototypes below. */
struct mbuf;
struct proc;
struct uio;
#define BUS_DMASYNC_POSTREAD 0x0001
#define BUS_DMASYNC_POSTWRITE 0x0002
#define BUS_DMASYNC_PREREAD 0x0004
#define BUS_DMASYNC_PREWRITE 0x0008
typedef struct machine_bus_dma_tag *bus_dma_tag_t;
typedef struct machine_bus_dmamap *bus_dmamap_t;
/*
* bus_dma_segment_t
*
* Describes a single contiguous DMA transaction. Values
* are suitable for programming into DMA registers.
*/
struct machine_bus_dma_segment {
bus_addr_t ds_addr; /* DMA address */
bus_size_t ds_len; /* length of transfer */
paddr_t _ds_paddr; /* CPU address */
vaddr_t _ds_vaddr; /* CPU address */
};
typedef struct machine_bus_dma_segment bus_dma_segment_t;
/*
* bus_dma_tag_t
*
* A machine-dependent opaque type describing the implementation of
* DMA for a given bus.
*/
struct machine_bus_dma_tag {
void *_cookie; /* cookie used in the guts */
int _flags; /* misc. flags */
/*
* DMA mapping methods.
*/
int (*_dmamap_create)(bus_dma_tag_t , bus_size_t, int,
bus_size_t, bus_size_t, int, bus_dmamap_t *);
void (*_dmamap_destroy)(bus_dma_tag_t , bus_dmamap_t);
int (*_dmamap_load)(bus_dma_tag_t , bus_dmamap_t, void *,
bus_size_t, struct proc *, int);
int (*_dmamap_load_mbuf)(bus_dma_tag_t , bus_dmamap_t,
struct mbuf *, int);
int (*_dmamap_load_uio)(bus_dma_tag_t , bus_dmamap_t,
struct uio *, int);
int (*_dmamap_load_raw)(bus_dma_tag_t , bus_dmamap_t,
bus_dma_segment_t *, int, bus_size_t, int);
int (*_dmamap_load_buffer)(bus_dma_tag_t, bus_dmamap_t, void *,
bus_size_t, struct proc *, int, paddr_t *, int *, int);
void (*_dmamap_unload)(bus_dma_tag_t , bus_dmamap_t);
void (*_dmamap_sync)(bus_dma_tag_t , bus_dmamap_t,
bus_addr_t, bus_size_t, int);
/*
* DMA memory utility functions.
*/
int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
bus_size_t, bus_dma_segment_t *, int, int *, int);
int (*_dmamem_alloc_range)(bus_dma_tag_t, bus_size_t, bus_size_t,
bus_size_t, bus_dma_segment_t *, int, int *, int,
bus_addr_t, bus_addr_t);
void (*_dmamem_free)(bus_dma_tag_t, bus_dma_segment_t *, int);
int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
int, size_t, caddr_t *, int);
void (*_dmamem_unmap)(bus_dma_tag_t, caddr_t, size_t);
paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
int, off_t, int, int);
/*
* internal memory address translation information.
*/
bus_addr_t _dma_mask;
};
#define bus_dmamap_create(t, s, n, m, b, f, p) \
(*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
#define bus_dmamap_destroy(t, p) \
(*(t)->_dmamap_destroy)((t), (p))
#define bus_dmamap_load(t, m, b, s, p, f) \
(*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
#define bus_dmamap_load_mbuf(t, m, b, f) \
(*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
#define bus_dmamap_load_uio(t, m, u, f) \
(*(t)->_dmamap_load_uio)((t), (m), (u), (f))
#define bus_dmamap_load_raw(t, m, sg, n, s, f) \
(*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
#define bus_dmamap_unload(t, p) \
(*(t)->_dmamap_unload)((t), (p))
#define bus_dmamap_sync(t, p, a, l, o) \
(void)((t)->_dmamap_sync ? \
(*(t)->_dmamap_sync)((t), (p), (a), (l), (o)) : (void)0)
#define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \
(*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f))
#define bus_dmamem_alloc_range(t, s, a, b, sg, n, r, f, l, h) \
(*(t)->_dmamem_alloc_range)((t), (s), (a), (b), (sg), \
(n), (r), (f), (l), (h))
#define bus_dmamem_free(t, sg, n) \
(*(t)->_dmamem_free)((t), (sg), (n))
#define bus_dmamem_map(t, sg, n, s, k, f) \
(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
#define bus_dmamem_unmap(t, k, s) \
(*(t)->_dmamem_unmap)((t), (k), (s))
#define bus_dmamem_mmap(t, sg, n, o, p, f) \
(*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f))
int _dmamap_create(bus_dma_tag_t, bus_size_t, int,
bus_size_t, bus_size_t, int, bus_dmamap_t *);
void _dmamap_destroy(bus_dma_tag_t, bus_dmamap_t);
int _dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *,
bus_size_t, struct proc *, int);
int _dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t, struct mbuf *, int);
int _dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t, struct uio *, int);
int _dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t,
bus_dma_segment_t *, int, bus_size_t, int);
int _dmamap_load_buffer(bus_dma_tag_t, bus_dmamap_t, void *,
bus_size_t, struct proc *, int, paddr_t *, int *, int);
void _dmamap_unload(bus_dma_tag_t, bus_dmamap_t);
void _dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
bus_size_t, int);
int _dmamem_alloc(bus_dma_tag_t, bus_size_t, bus_size_t,
bus_size_t, bus_dma_segment_t *, int, int *, int);
void _dmamem_free(bus_dma_tag_t, bus_dma_segment_t *, int);
int _dmamem_map(bus_dma_tag_t, bus_dma_segment_t *,
int, size_t, caddr_t *, int);
void _dmamem_unmap(bus_dma_tag_t, caddr_t, size_t);
paddr_t _dmamem_mmap(bus_dma_tag_t, bus_dma_segment_t *, int, off_t, int, int);
int _dmamem_alloc_range(bus_dma_tag_t, bus_size_t, bus_size_t, bus_size_t,
bus_dma_segment_t *, int, int *, int, paddr_t, paddr_t);
/*
* bus_dmamap_t
*
* Describes a DMA mapping.
*/
struct machine_bus_dmamap {
/*
* PRIVATE MEMBERS: not for use by machine-independent code.
*/
bus_size_t _dm_size; /* largest DMA transfer mappable */
int _dm_segcnt; /* number of segs this map can map */
bus_size_t _dm_maxsegsz; /* largest possible segment */
bus_size_t _dm_boundary; /* don't cross this */
int _dm_flags; /* misc. flags */
void *_dm_cookie; /* cookie for bus-specific functions */
/*
* PUBLIC MEMBERS: these are used by machine-independent code.
*/
bus_size_t dm_mapsize; /* size of the mapping */
int dm_nsegs; /* # valid segments in mapping */
bus_dma_segment_t dm_segs[1]; /* segments; variable length */
};
int generic_space_map(bus_space_tag_t, bus_addr_t, bus_size_t, int,
bus_space_handle_t *);
void generic_space_unmap(bus_space_tag_t, bus_space_handle_t, bus_size_t);
int generic_space_region(bus_space_tag_t, bus_space_handle_t, bus_size_t,
bus_size_t, bus_space_handle_t *);
void *generic_space_vaddr(bus_space_tag_t, bus_space_handle_t);
paddr_t generic_space_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int);
uint8_t generic_space_read_1(bus_space_tag_t, bus_space_handle_t, bus_size_t);
uint16_t generic_space_read_2(bus_space_tag_t, bus_space_handle_t, bus_size_t);
uint32_t generic_space_read_4(bus_space_tag_t, bus_space_handle_t, bus_size_t);
uint64_t generic_space_read_8(bus_space_tag_t, bus_space_handle_t, bus_size_t);
void generic_space_read_raw_2(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, uint8_t *, bus_size_t);
void generic_space_write_1(bus_space_tag_t, bus_space_handle_t, bus_size_t,
uint8_t);
void generic_space_write_2(bus_space_tag_t, bus_space_handle_t, bus_size_t,
uint16_t);
void generic_space_write_4(bus_space_tag_t, bus_space_handle_t, bus_size_t,
uint32_t);
void generic_space_write_8(bus_space_tag_t, bus_space_handle_t, bus_size_t,
uint64_t);
void generic_space_write_raw_2(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, const uint8_t *, bus_size_t);
void generic_space_read_raw_4(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, uint8_t *, bus_size_t);
void generic_space_write_raw_4(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, const uint8_t *, bus_size_t);
void generic_space_read_raw_8(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, uint8_t *, bus_size_t);
void generic_space_write_raw_8(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, const uint8_t *, bus_size_t);
#endif /* _MACHINE_BUS_H_ */

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/* $OpenBSD: cdefs.h,v 1.1 2016/12/17 23:38:33 patrick Exp $ */
#ifndef _MACHINE_CDEFS_H_
#define _MACHINE_CDEFS_H_
#define __strong_alias(alias,sym) \
__asm__(".global " __STRING(alias) " ; " __STRING(alias) \
" = " __STRING(sym))
#define __weak_alias(alias,sym) \
__asm__(".weak " __STRING(alias) " ; " __STRING(alias) \
" = " __STRING(sym))
#define __warn_references(sym,msg) \
__asm__(".section .gnu.warning." __STRING(sym) \
" ; .ascii \"" msg "\" ; .text")
#endif /* !_MACHINE_CDEFS_H_ */

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lib/libc/include/aarch64-openbsd-none/arm64/conf.h vendored Normal file
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/* $OpenBSD: conf.h,v 1.5 2024/06/12 02:50:25 jsg Exp $ */
/* $NetBSD: conf.h,v 1.2 1996/05/05 19:28:34 christos Exp $ */
/*
* Copyright (c) 1996 Christos Zoulas. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Christos Zoulas.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _MACHINE_CONF_H_
#define _MACHINE_CONF_H_
#include <sys/conf.h>
#define mmread mmrw
#define mmwrite mmrw
cdev_decl(mm);
/* open, close, ioctl */
#define cdev_openprom_init(c,n) { \
dev_init(c,n,open), dev_init(c,n,close), (dev_type_read((*))) enodev, \
(dev_type_write((*))) enodev, dev_init(c,n,ioctl), \
(dev_type_stop((*))) nullop, 0, \
(dev_type_mmap((*))) enodev }
cdev_decl(openprom);
/* open, close, write, ioctl, kqueue */
#define cdev_acpiapm_init(c,n) { \
dev_init(c,n,open), dev_init(c,n,close), (dev_type_read((*))) enodev, \
(dev_type_write((*))) enodev, dev_init(c,n,ioctl), \
(dev_type_stop((*))) enodev, 0, \
(dev_type_mmap((*))) enodev, 0, 0, dev_init(c,n,kqfilter) }
cdev_decl(apm);
cdev_decl(acpiapm);
#endif /* _MACHINE_CONF_H_ */

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/* $OpenBSD: cpu.h,v 1.51 2025/02/11 22:27:09 kettenis Exp $ */
/*
* Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_CPU_H_
#define _MACHINE_CPU_H_
/*
* User-visible definitions
*/
/*
* CTL_MACHDEP definitions.
*/
#define CPU_COMPATIBLE 1 /* compatible property */
#define CPU_ID_AA64ISAR0 2
#define CPU_ID_AA64ISAR1 3
#define CPU_ID_AA64ISAR2 4
#define CPU_ID_AA64MMFR0 5
#define CPU_ID_AA64MMFR1 6
#define CPU_ID_AA64MMFR2 7
#define CPU_ID_AA64PFR0 8
#define CPU_ID_AA64PFR1 9
#define CPU_ID_AA64SMFR0 10
#define CPU_ID_AA64ZFR0 11
#define CPU_LIDACTION 12
#define CPU_MAXID 13 /* number of valid machdep ids */
#define CTL_MACHDEP_NAMES { \
{ 0, 0 }, \
{ "compatible", CTLTYPE_STRING }, \
{ "id_aa64isar0", CTLTYPE_QUAD }, \
{ "id_aa64isar1", CTLTYPE_QUAD }, \
{ "id_aa64isar2", CTLTYPE_QUAD }, \
{ "id_aa64mmfr0", CTLTYPE_QUAD }, \
{ "id_aa64mmfr1", CTLTYPE_QUAD }, \
{ "id_aa64mmfr2", CTLTYPE_QUAD }, \
{ "id_aa64pfr0", CTLTYPE_QUAD }, \
{ "id_aa64pfr1", CTLTYPE_QUAD }, \
{ "id_aa64smfr0", CTLTYPE_QUAD }, \
{ "id_aa64zfr0", CTLTYPE_QUAD }, \
{ "lidaction", CTLTYPE_INT }, \
}
#ifdef _KERNEL
/*
* Kernel-only definitions
*/
extern uint64_t cpu_id_aa64isar0;
extern uint64_t cpu_id_aa64isar1;
extern uint64_t cpu_id_aa64isar2;
extern uint64_t cpu_id_aa64mmfr0;
extern uint64_t cpu_id_aa64mmfr1;
extern uint64_t cpu_id_aa64mmfr2;
extern uint64_t cpu_id_aa64pfr0;
extern uint64_t cpu_id_aa64pfr1;
extern uint64_t cpu_id_aa64zfr0;
void cpu_identify_cleanup(void);
#include <machine/intr.h>
#include <machine/frame.h>
#include <machine/armreg.h>
/* All the CLKF_* macros take a struct clockframe * as an argument. */
#define clockframe trapframe
/*
* CLKF_USERMODE: Return TRUE/FALSE (1/0) depending on whether the
* frame came from USR mode or not.
*/
#define CLKF_USERMODE(frame) ((frame->tf_elr & (1ul << 63)) == 0)
/*
* CLKF_INTR: True if we took the interrupt from inside another
* interrupt handler.
*/
#define CLKF_INTR(frame) (curcpu()->ci_idepth > 1)
/*
* CLKF_PC: Extract the program counter from a clockframe
*/
#define CLKF_PC(frame) (frame->tf_elr)
/*
* PROC_PC: Find out the program counter for the given process.
*/
#define PROC_PC(p) ((p)->p_addr->u_pcb.pcb_tf->tf_elr)
#define PROC_STACK(p) ((p)->p_addr->u_pcb.pcb_tf->tf_sp)
/*
* Per-CPU information. For now we assume one CPU.
*/
#include <sys/clockintr.h>
#include <sys/device.h>
#include <sys/sched.h>
#include <sys/srp.h>
#include <uvm/uvm_percpu.h>
struct cpu_info {
struct device *ci_dev; /* Device corresponding to this CPU */
struct cpu_info *ci_next;
struct schedstate_percpu ci_schedstate; /* scheduler state */
u_int32_t ci_cpuid;
uint64_t ci_mpidr;
uint64_t ci_midr;
u_int ci_acpi_proc_id;
int ci_node;
struct cpu_info *ci_self;
#define __HAVE_CPU_TOPOLOGY
u_int32_t ci_smt_id;
u_int32_t ci_core_id;
u_int32_t ci_pkg_id;
struct proc *ci_curproc;
struct pcb *ci_curpcb;
struct pmap *ci_curpm;
u_int32_t ci_randseed;
u_int32_t ci_ctrl; /* The CPU control register */
u_int64_t ci_trampoline_vectors;
uint32_t ci_cpl;
uint32_t ci_ipending;
uint32_t ci_idepth;
#ifdef DIAGNOSTIC
int ci_mutex_level;
#endif
int ci_want_resched;
void (*ci_flush_bp)(void);
void (*ci_serror)(void);
uint64_t ci_ttbr1;
vaddr_t ci_el1_stkend;
uint32_t ci_psci_idle_latency;
uint32_t ci_psci_idle_param;
uint32_t ci_psci_suspend_param;
struct opp_table *ci_opp_table;
volatile int ci_opp_idx;
volatile int ci_opp_max;
uint32_t ci_cpu_supply;
u_long ci_prev_sleep;
u_long ci_last_itime;
#ifdef MULTIPROCESSOR
struct srp_hazard ci_srp_hazards[SRP_HAZARD_NUM];
#define __HAVE_UVM_PERCPU
struct uvm_pmr_cache ci_uvm;
volatile int ci_flags;
volatile int ci_ddb_paused;
#define CI_DDB_RUNNING 0
#define CI_DDB_SHOULDSTOP 1
#define CI_DDB_STOPPED 2
#define CI_DDB_ENTERDDB 3
#define CI_DDB_INDDB 4
#endif
#ifdef GPROF
struct gmonparam *ci_gmon;
struct clockintr ci_gmonclock;
#endif
struct clockqueue ci_queue;
char ci_panicbuf[512];
};
#define CPUF_PRIMARY (1<<0)
#define CPUF_AP (1<<1)
#define CPUF_IDENTIFY (1<<2)
#define CPUF_IDENTIFIED (1<<3)
#define CPUF_PRESENT (1<<4)
#define CPUF_GO (1<<5)
#define CPUF_RUNNING (1<<6)
static inline struct cpu_info *
curcpu(void)
{
struct cpu_info *__ci = NULL;
__asm volatile("mrs %0, tpidr_el1" : "=r" (__ci));
return (__ci);
}
extern struct cpu_info cpu_info_primary;
extern struct cpu_info *cpu_info_list;
#ifndef MULTIPROCESSOR
#define cpu_number() 0
#define CPU_IS_PRIMARY(ci) 1
#define CPU_IS_RUNNING(ci) 1
#define CPU_INFO_ITERATOR int
#define CPU_INFO_FOREACH(cii, ci) \
for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL)
#define CPU_INFO_UNIT(ci) 0
#define MAXCPUS 1
#define cpu_unidle(ci)
#else
#define cpu_number() (curcpu()->ci_cpuid)
#define CPU_IS_PRIMARY(ci) ((ci) == &cpu_info_primary)
#define CPU_IS_RUNNING(ci) ((ci)->ci_flags & CPUF_RUNNING)
#define CPU_INFO_ITERATOR int
#define CPU_INFO_FOREACH(cii, ci) for (cii = 0, ci = cpu_info_list; \
ci != NULL; ci = ci->ci_next)
#define CPU_INFO_UNIT(ci) ((ci)->ci_dev ? (ci)->ci_dev->dv_unit : 0)
#define MAXCPUS 256
extern struct cpu_info *cpu_info[MAXCPUS];
void cpu_boot_secondary_processors(void);
#endif /* !MULTIPROCESSOR */
#define CPU_BUSY_CYCLE() __asm volatile("yield" : : : "memory")
#define curpcb curcpu()->ci_curpcb
static inline unsigned int
cpu_rnd_messybits(void)
{
uint64_t val, rval;
__asm volatile("mrs %0, CNTVCT_EL0; rbit %1, %0;"
: "=r" (val), "=r" (rval));
return (val ^ rval);
}
/*
* Scheduling glue
*/
#define aston(p) ((p)->p_md.md_astpending = 1)
#define setsoftast() aston(curcpu()->ci_curproc)
/*
* Notify the current process (p) that it has a signal pending,
* process as soon as possible.
*/
#ifdef MULTIPROCESSOR
void cpu_unidle(struct cpu_info *ci);
#define signotify(p) (aston(p), cpu_unidle((p)->p_cpu))
void cpu_kick(struct cpu_info *);
#else
#define cpu_kick(ci)
#define cpu_unidle(ci)
#define signotify(p) setsoftast()
#endif
/*
* Preempt the current process if in interrupt from user mode,
* or after the current trap/syscall if in system mode.
*/
void need_resched(struct cpu_info *);
#define clear_resched(ci) ((ci)->ci_want_resched = 0)
/*
* Give a profiling tick to the current process when the user profiling
* buffer pages are invalid. On the i386, request an ast to send us
* through trap(), marking the proc as needing a profiling tick.
*/
#define need_proftick(p) aston(p)
// asm code to start new kernel contexts.
void proc_trampoline(void);
/*
* Random cruft
*/
void dumpconf(void);
// syscall.c
void svc_handler (trapframe_t *);
// functions to manipulate interrupt state
static __inline void
restore_daif(uint32_t daif)
{
__asm volatile ("msr daif, %x0":: "r"(daif));
}
static __inline void
enable_irq_daif(void)
{
__asm volatile ("msr daifclr, #3");
}
static __inline void
disable_irq_daif(void)
{
__asm volatile ("msr daifset, #3");
}
static __inline uint32_t
disable_irq_daif_ret(void)
{
uint32_t daif;
__asm volatile ("mrs %x0, daif": "=r"(daif));
__asm volatile ("msr daifset, #3");
return daif;
}
static inline void
intr_enable(void)
{
enable_irq_daif();
}
static inline u_long
intr_disable(void)
{
return disable_irq_daif_ret();
}
static inline void
intr_restore(u_long daif)
{
restore_daif(daif);
}
void cpu_halt(void);
int cpu_suspend_primary(void);
void cpu_resume_secondary(struct cpu_info *);
extern void (*cpu_idle_cycle_fcn)(void);
extern void (*cpu_suspend_cycle_fcn)(void);
void cpu_wfi(void);
void delay (unsigned);
#define DELAY(x) delay(x)
#endif /* _KERNEL */
#ifdef MULTIPROCESSOR
#include <sys/mplock.h>
#endif /* MULTIPROCESSOR */
#endif /* !_MACHINE_CPU_H_ */

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/* $OpenBSD: cpufunc.h,v 1.4 2018/05/02 15:17:30 patrick Exp $ */
/*-
* Copyright (c) 2014 Andrew Turner
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD: head/sys/cpu/include/cpufunc.h 299683 2016-05-13 16:03:50Z andrew $
*/
#ifndef _MACHINE_CPUFUNC_H_
#define _MACHINE_CPUFUNC_H_
#ifdef _KERNEL
#include <machine/armreg.h>
extern int64_t dcache_line_size;
extern int64_t icache_line_size;
extern int64_t idcache_line_size;
extern int64_t dczva_line_size;
void cpu_setttb(int, paddr_t);
void cpu_tlb_flush(void);
void cpu_tlb_flush_asid(vaddr_t);
void cpu_tlb_flush_all_asid(vaddr_t);
void cpu_tlb_flush_asid_all(vaddr_t);
void cpu_icache_sync_range(vaddr_t, vsize_t);
void cpu_idcache_wbinv_range(vaddr_t, vsize_t);
void cpu_dcache_wbinv_range(vaddr_t, vsize_t);
void cpu_dcache_inv_range(vaddr_t, vsize_t);
void cpu_dcache_wb_range(vaddr_t, vsize_t);
register_t smc_call(register_t, register_t, register_t, register_t);
#endif /* _KERNEL */
#endif /* _MACHINE_CPUFUNC_H_ */

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lib/libc/include/aarch64-openbsd-none/arm64/db_machdep.h vendored Normal file
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/* $OpenBSD: db_machdep.h,v 1.8 2025/07/22 09:20:41 kettenis Exp $ */
/* $NetBSD: db_machdep.h,v 1.5 2001/11/22 18:00:00 thorpej Exp $ */
/*
* Copyright (c) 1996 Scott K Stevens
*
* Mach Operating System
* Copyright (c) 1991,1990 Carnegie Mellon University
* All Rights Reserved.
*
* Permission to use, copy, modify and distribute this software and its
* documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie Mellon
* the rights to redistribute these changes.
*/
#ifndef _MACHINE_DB_MACHDEP_H_
#define _MACHINE_DB_MACHDEP_H_
/*
* Machine-dependent defines for new kernel debugger.
*/
#include <sys/param.h>
#include <uvm/uvm_extern.h>
#include <machine/armreg.h>
#include <machine/frame.h>
/* end of mangling */
typedef long db_expr_t; /* expression - signed */
typedef trapframe_t db_regs_t;
extern db_regs_t ddb_regs; /* register state */
#define DDB_REGS (&ddb_regs)
#define PC_REGS(regs) ((vaddr_t)(regs)->tf_elr)
#define SET_PC_REGS(regs, value) (regs)->tf_elr = (register_t)(value)
#define BKPT_INST 0xd4200000 /* breakpoint instruction */
#define BKPT_SIZE (INSN_SIZE) /* size of breakpoint inst */
#define BKPT_SET(inst) (BKPT_INST)
#define db_clear_single_step(regs) ((regs)->tf_spsr &= ~PSR_SS)
#define db_set_single_step(regs) ((regs)->tf_spsr |= PSR_SS)
#define IS_BREAKPOINT_TRAP(type, code) ((type) == EXCP_BRK)
#define IS_WATCHPOINT_TRAP(type, code) ((type) == EXCP_WATCHPT_EL1)
// ALL BROKEN!!!
#define inst_trap_return(ins) ((ins) == 0 && (ins) == 1)
#define inst_return(ins) ((ins) == 0 && (ins) == 1)
#define inst_call(ins) ((ins) == 0 && (ins) == 1)
#define DB_MACHINE_COMMANDS
int db_ktrap(int, db_regs_t *);
void db_machine_init (void);
#define DDB_STATE_NOT_RUNNING 0
#define DDB_STATE_RUNNING 1
#define DDB_STATE_EXITING 2
#endif /* _MACHINE_DB_MACHDEP_H_ */

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lib/libc/include/aarch64-openbsd-none/arm64/disklabel.h vendored Normal file
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/* $OpenBSD: disklabel.h,v 1.1 2016/12/17 23:38:33 patrick Exp $ */
/*
* Copyright (c) 2014 Patrick Wildt <patrick@blueri.se>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_DISKLABEL_H_
#define _MACHINE_DISKLABEL_H_
#define LABELSECTOR 1 /* sector containing label */
#define LABELOFFSET 0 /* offset of label in sector */
#define MAXPARTITIONS 16 /* number of partitions */
#endif /* _MACHINE_DISKLABEL_H_ */

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/* $OpenBSD: efivar.h,v 1.2 2024/07/10 10:53:55 kettenis Exp $ */
/*
* Copyright (c) 2022 Mark Kettenis <kettenis@openbsd.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_EFIVAR_H_
#define _MACHINE_EFIVAR_H_
#include <dev/clock_subr.h>
struct efi_softc {
struct device sc_dev;
struct pmap *sc_pm;
EFI_RUNTIME_SERVICES *sc_rs;
EFI_SYSTEM_RESOURCE_TABLE *sc_esrt;
u_long sc_psw;
struct todr_chip_handle sc_todr;
};
extern EFI_GET_VARIABLE efi_get_variable;
extern EFI_SET_VARIABLE efi_set_variable;
extern EFI_GET_NEXT_VARIABLE_NAME efi_get_next_variable_name;
void efi_enter(struct efi_softc *);
void efi_leave(struct efi_softc *);
extern label_t efi_jmpbuf;
#define efi_enter_check(sc) (setjmp(&efi_jmpbuf) ? \
(efi_leave(sc), EFAULT) : (efi_enter(sc), 0))
#endif /* _MACHINE_EFIVAR_H_ */

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lib/libc/include/aarch64-openbsd-none/arm64/elf.h vendored Normal file
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/*-
* Copyright (c) 1996-1997 John D. Polstra.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE_ELF_H_
#define _MACHINE_ELF_H_
/*
* ELF definitions for the AArch64 architecture.
*/
#ifdef _KERNEL
# define __HAVE_CPU_HWCAP
# define __HAVE_CPU_HWCAP2
extern unsigned long hwcap, hwcap2;
#endif /* _KERNEL */
/* HWCAP */
#define HWCAP_FP 0x00000001
#define HWCAP_ASIMD 0x00000002
#define HWCAP_EVTSTRM 0x00000004
#define HWCAP_AES 0x00000008
#define HWCAP_PMULL 0x00000010
#define HWCAP_SHA1 0x00000020
#define HWCAP_SHA2 0x00000040
#define HWCAP_CRC32 0x00000080
#define HWCAP_ATOMICS 0x00000100
#define HWCAP_FPHP 0x00000200
#define HWCAP_ASIMDHP 0x00000400
#define HWCAP_CPUID 0x00000800
#define HWCAP_ASIMDRDM 0x00001000
#define HWCAP_JSCVT 0x00002000
#define HWCAP_FCMA 0x00004000
#define HWCAP_LRCPC 0x00008000
#define HWCAP_DCPOP 0x00010000
#define HWCAP_SHA3 0x00020000
#define HWCAP_SM3 0x00040000
#define HWCAP_SM4 0x00080000
#define HWCAP_ASIMDDP 0x00100000
#define HWCAP_SHA512 0x00200000
#define HWCAP_SVE 0x00400000
#define HWCAP_ASIMDFHM 0x00800000
#define HWCAP_DIT 0x01000000
#define HWCAP_USCAT 0x02000000
#define HWCAP_ILRCPC 0x04000000
#define HWCAP_FLAGM 0x08000000
#define HWCAP_SSBS 0x10000000
#define HWCAP_SB 0x20000000
#define HWCAP_PACA 0x40000000
#define HWCAP_PACG 0x80000000
/* HWCAP2 */
#define HWCAP2_DCPODP 0x0000000000000001ul
#define HWCAP2_SVE2 0x0000000000000002ul
#define HWCAP2_SVEAES 0x0000000000000004ul
#define HWCAP2_SVEPMULL 0x0000000000000008ul
#define HWCAP2_SVEBITPERM 0x0000000000000010ul
#define HWCAP2_SVESHA3 0x0000000000000020ul
#define HWCAP2_SVESM4 0x0000000000000040ul
#define HWCAP2_FLAGM2 0x0000000000000080ul
#define HWCAP2_FRINT 0x0000000000000100ul
#define HWCAP2_SVEI8MM 0x0000000000000200ul
#define HWCAP2_SVEF32MM 0x0000000000000400ul
#define HWCAP2_SVEF64MM 0x0000000000000800ul
#define HWCAP2_SVEBF16 0x0000000000001000ul
#define HWCAP2_I8MM 0x0000000000002000ul
#define HWCAP2_BF16 0x0000000000004000ul
#define HWCAP2_DGH 0x0000000000008000ul
#define HWCAP2_RNG 0x0000000000010000ul
#define HWCAP2_BTI 0x0000000000020000ul
#define HWCAP2_MTE 0x0000000000040000ul
#define HWCAP2_ECV 0x0000000000080000ul
#define HWCAP2_AFP 0x0000000000100000ul
#define HWCAP2_RPRES 0x0000000000200000ul
#define HWCAP2_MTE3 0x0000000000400000ul
#define HWCAP2_SME 0x0000000000800000ul
#define HWCAP2_SME_I16I64 0x0000000001000000ul
#define HWCAP2_SME_F64F64 0x0000000002000000ul
#define HWCAP2_SME_I8I32 0x0000000004000000ul
#define HWCAP2_SME_F16F32 0x0000000008000000ul
#define HWCAP2_SME_B16F32 0x0000000010000000ul
#define HWCAP2_SME_F32F32 0x0000000020000000ul
#define HWCAP2_SME_FA64 0x0000000040000000ul
#define HWCAP2_WFXT 0x0000000080000000ul
#define HWCAP2_EBF16 0x0000000100000000ul
#define HWCAP2_SVE_EBF16 0x0000000200000000ul
#define HWCAP2_CSSC 0x0000000400000000ul
#define HWCAP2_RPRFM 0x0000000800000000ul
#define HWCAP2_SVE2P1 0x0000001000000000ul
#define HWCAP2_SME2 0x0000002000000000ul
#define HWCAP2_SME2P1 0x0000004000000000ul
#define HWCAP2_SME_I16I32 0x0000008000000000ul
#define HWCAP2_SME_BI32I32 0x0000010000000000ul
#define HWCAP2_SME_B16B16 0x0000020000000000ul
#define HWCAP2_SME_F16F16 0x0000040000000000ul
#define HWCAP2_MOPS 0x0000080000000000ul
#define HWCAP2_HBC 0x0000100000000000ul
#endif /* !_MACHINE_ELF_H_ */

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/* $OpenBSD: endian.h,v 1.4 2024/05/07 14:26:48 naddy Exp $ */
/*
* Copyright (c) 2015 David Gwynne <dlg@openbsd.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_ENDIAN_H_
#define _MACHINE_ENDIAN_H_
#define _BYTE_ORDER _LITTLE_ENDIAN
#define __STRICT_ALIGNMENT
#ifndef __FROM_SYS__ENDIAN
#include <sys/endian.h>
#endif
#endif /* _MACHINE_ENDIAN_H_ */

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/* $OpenBSD: exec.h,v 1.3 2025/07/31 16:09:59 kettenis Exp $ */
/*
* Copyright (c) 2014 Patrick Wildt <patrick@blueri.se>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_EXEC_H_
#define _MACHINE_EXEC_H_
#define __LDPGSZ 4096
#define ARCH_ELFSIZE 64
#define ELF_TARG_CLASS ELFCLASS64
#define ELF_TARG_DATA ELFDATA2LSB
#define ELF_TARG_MACH EM_AARCH64
#ifdef _KERNEL
#define __HAVE_COREDUMP_NOTE_ELF_MD
#endif
#endif

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/* $OpenBSD: fdt.h,v 1.7 2020/07/14 15:34:14 patrick Exp $ */
/*
* Copyright (c) 2016 Patrick Wildt <patrick@blueri.se>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __ARM_FDT_H__
#define __ARM_FDT_H__
#define _ARM32_BUS_DMA_PRIVATE
#include <machine/bus.h>
struct fdt_attach_args {
const char *fa_name;
int fa_node;
bus_space_tag_t fa_iot;
bus_dma_tag_t fa_dmat;
struct fdt_reg *fa_reg;
int fa_nreg;
uint32_t *fa_intr;
int fa_nintr;
int fa_acells;
int fa_scells;
};
extern int stdout_node;
extern int stdout_speed;
extern bus_space_tag_t fdt_cons_bs_tag;
void *fdt_find_cons(const char *);
#define fdt_intr_enable arm_intr_enable
#define fdt_intr_establish arm_intr_establish_fdt
#define fdt_intr_establish_cpu arm_intr_establish_fdt_cpu
#define fdt_intr_establish_idx arm_intr_establish_fdt_idx
#define fdt_intr_establish_idx_cpu arm_intr_establish_fdt_idx_cpu
#define fdt_intr_establish_imap arm_intr_establish_fdt_imap
#define fdt_intr_establish_imap_cpu arm_intr_establish_fdt_imap_cpu
#define fdt_intr_establish_msi arm_intr_establish_fdt_msi
#define fdt_intr_establish_msi_cpu arm_intr_establish_fdt_msi_cpu
#define fdt_intr_disable arm_intr_disable
#define fdt_intr_disestablish arm_intr_disestablish_fdt
#define fdt_intr_get_parent arm_intr_get_parent
#define fdt_intr_parent_establish arm_intr_parent_establish_fdt
#define fdt_intr_parent_disestablish arm_intr_parent_disestablish_fdt
#define fdt_intr_register arm_intr_register_fdt
#endif /* __ARM_FDT_H__ */

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/* $OpenBSD: fenv.h,v 1.3 2019/03/12 22:14:50 patrick Exp $ */
/*
* Copyright (c) 2011 Martynas Venckus <martynas@openbsd.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_FENV_H_
#define _MACHINE_FENV_H_
/*
* Each symbol representing a floating point exception expands to an integer
* constant expression with values, such that bitwise-inclusive ORs of _all
* combinations_ of the constants result in distinct values.
*
* We use such values that allow direct bitwise operations on FPU registers.
*/
#define FE_INVALID 0x01
#define FE_DIVBYZERO 0x02
#define FE_OVERFLOW 0x04
#define FE_UNDERFLOW 0x08
#define FE_INEXACT 0x10
#define FE_DENORMAL 0x80
/*
* The following symbol is simply the bitwise-inclusive OR of all floating-point
* exception constants defined above.
*/
#define FE_ALL_EXCEPT (FE_INVALID | FE_DIVBYZERO | FE_OVERFLOW | \
FE_UNDERFLOW | FE_INEXACT | FE_DENORMAL)
/*
* Each symbol representing the rounding direction, expands to an integer
* constant expression whose value is distinct non-negative value.
*
* We use such values that allow direct bitwise operations on FPU registers.
*/
#define FE_TONEAREST 0x0
#define FE_UPWARD 0x1
#define FE_DOWNWARD 0x2
#define FE_TOWARDZERO 0x3
/*
* The following symbol is simply the bitwise-inclusive OR of all floating-point
* rounding direction constants defined above.
*/
#define _ROUND_MASK (FE_TONEAREST | FE_UPWARD | FE_DOWNWARD | \
FE_TOWARDZERO)
#define _ROUND_SHIFT 22
/*
* fenv_t represents the entire floating-point environment.
*/
typedef unsigned long long fenv_t;
/*
* The following constant represents the default floating-point environment
* (that is, the one installed at program startup) and has type pointer to
* const-qualified fenv_t.
*
* It can be used as an argument to the functions within the <fenv.h> header
* that manage the floating-point environment, namely fesetenv() and
* feupdateenv().
*/
__BEGIN_DECLS
extern fenv_t __fe_dfl_env;
__END_DECLS
#define FE_DFL_ENV ((const fenv_t *)&__fe_dfl_env)
/*
* fexcept_t represents the floating-point status flags collectively, including
* any status the implementation associates with the flags.
*
* A floating-point status flag is a system variable whose value is set (but
* never cleared) when a floating-point exception is raised, which occurs as a
* side effect of exceptional floating-point arithmetic to provide auxiliary
* information.
*
* A floating-point control mode is a system variable whose value may be set by
* the user to affect the subsequent behavior of floating-point arithmetic.
*/
typedef unsigned long long fexcept_t;
#endif /* !_MACHINE_FENV_H_ */

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/* $OpenBSD: fpu.h,v 1.2 2025/02/11 22:27:09 kettenis Exp $ */
/*
* Copyright (c) 2022 Mark Kettenis <kettenis@openbsd.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_FPU_H
#define _MACHINE_FPU_H
void fpu_save(struct proc *);
void fpu_load(struct proc *);
void sve_load(struct proc *);
void fpu_drop(void);
void fpu_kernel_enter(void);
void fpu_kernel_exit(void);
#endif /* !_MACHINE_FPU_H */

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/* $OpenBSD: frame.h,v 1.3 2018/06/30 15:23:37 deraadt Exp $ */
/*
* Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_FRAME_H_
#define _MACHINE_FRAME_H_
#ifndef _LOCORE
#include <sys/signal.h>
/*
* Exception/Trap Stack Frame
*/
#define clockframe trapframe
typedef struct trapframe {
register_t tf_sp;
register_t tf_lr;
register_t tf_elr;
register_t tf_spsr;
register_t tf_x[30];
} trapframe_t;
/*
* pushed on stack for signal delivery
*/
struct sigframe {
int sf_signum;
struct sigcontext sf_sc;
siginfo_t sf_si;
};
/*
* System stack frames.
*/
/*
* Stack frame inside cpu_switch()
*/
struct switchframe {
register_t sf_x19;
register_t sf_x20;
register_t sf_x21;
register_t sf_x22;
register_t sf_x23;
register_t sf_x24;
register_t sf_x25;
register_t sf_x26;
register_t sf_x27;
register_t sf_x28;
register_t sf_x29;
register_t sf_lr;
};
struct callframe {
struct callframe *f_frame;
register_t f_lr;
};
#endif /* !_LOCORE */
#endif /* _MACHINE_FRAME_H_ */

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/* $OpenBSD: hypervisor.h,v 1.5 2025/02/11 22:27:09 kettenis Exp $ */
/*-
* Copyright (c) 2013, 2014 Andrew Turner
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD: head/sys/arm64/include/hypervisor.h 281494 2015-04-13 14:43:10Z andrew $
*/
#ifndef _MACHINE_HYPERVISOR_H_
#define _MACHINE_HYPERVISOR_H_
/*
* These registers are only useful when in hypervisor context,
* e.g. specific to EL2, or controlling the hypervisor.
*/
/*
* Architecture feature trap register
*/
#define CPTR_RES0 0x7fefc800
#define CPTR_RES1 0x000032ff
#define CPTR_TFP 0x00000400
#define CPTR_TTA 0x00100000
#define CPTR_TCPAC 0x80000000
/*
* Hypervisor Config Register
*/
#define HCR_VM 0x0000000000000001
#define HCR_SWIO 0x0000000000000002
#define HCR_PTW 0x0000000000000004
#define HCR_FMO 0x0000000000000008
#define HCR_IMO 0x0000000000000010
#define HCR_AMO 0x0000000000000020
#define HCR_VF 0x0000000000000040
#define HCR_VI 0x0000000000000080
#define HCR_VSE 0x0000000000000100
#define HCR_FB 0x0000000000000200
#define HCR_BSU_MASK 0x0000000000000c00
#define HCR_DC 0x0000000000001000
#define HCR_TWI 0x0000000000002000
#define HCR_TWE 0x0000000000004000
#define HCR_TID0 0x0000000000008000
#define HCR_TID1 0x0000000000010000
#define HCR_TID2 0x0000000000020000
#define HCR_TID3 0x0000000000040000
#define HCR_TSC 0x0000000000080000
#define HCR_TIDCP 0x0000000000100000
#define HCR_TACR 0x0000000000200000
#define HCR_TSW 0x0000000000400000
#define HCR_TPC 0x0000000000800000
#define HCR_TPU 0x0000000001000000
#define HCR_TTLB 0x0000000002000000
#define HCR_TVM 0x0000000004000000
#define HCR_TGE 0x0000000008000000
#define HCR_TDZ 0x0000000010000000
#define HCR_HCD 0x0000000020000000
#define HCR_TRVM 0x0000000040000000
#define HCR_RW 0x0000000080000000
#define HCR_CD 0x0000000100000000
#define HCR_ID 0x0000000200000000
#define HCR_E2H 0x0000000400000000
#define HCR_APK 0x0000010000000000
#define HCR_API 0x0000020000000000
#endif

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/* $OpenBSD: ieee.h,v 1.3 2017/04/16 16:14:37 kettenis Exp $ */
/* $NetBSD: ieee.h,v 1.1 1996/09/30 16:34:25 ws Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)ieee.h 8.1 (Berkeley) 6/11/93
*/
/*
* ieee.h defines the machine-dependent layout of the machine's IEEE
* floating point. It does *not* define (yet?) any of the rounding
* mode bits, exceptions, and so forth.
*/
/*
* Define the number of bits in each fraction and exponent.
*
* k k+1
* Note that 1.0 x 2 == 0.1 x 2 and that denorms are represented
*
* (-exp_bias+1)
* as fractions that look like 0.fffff x 2 . This means that
*
* -126
* the number 0.10000 x 2 , for instance, is the same as the normalized
*
* -127 -128
* float 1.0 x 2 . Thus, to represent 2 , we need one leading zero
*
* -129
* in the fraction; to represent 2 , we need two, and so on. This
*
* (-exp_bias-fracbits+1)
* implies that the smallest denormalized number is 2
*
* for whichever format we are talking about: for single precision, for
*
* -126 -149
* instance, we get .00000000000000000000001 x 2 , or 1.0 x 2 , and
*
* -149 == -127 - 23 + 1.
*/
#define SNG_EXPBITS 8
#define SNG_FRACBITS 23
#define DBL_EXPBITS 11
#define DBL_FRACHBITS 20
#define DBL_FRACLBITS 32
#define DBL_FRACBITS 52
#define EXT_EXPBITS 15
#define EXT_FRACHBITS 16
#define EXT_FRACHMBITS 32
#define EXT_FRACLMBITS 32
#define EXT_FRACLBITS 32
#define EXT_FRACBITS 112
#define EXT_IMPLICIT_NBIT
#define EXT_TO_ARRAY32(p, a) do { \
(a)[0] = (uint32_t)(p)->ext_fracl; \
(a)[1] = (uint32_t)(p)->ext_fraclm; \
(a)[2] = (uint32_t)(p)->ext_frachm; \
(a)[3] = (uint32_t)(p)->ext_frach; \
} while(0)
struct ieee_single {
u_int sng_frac:23;
u_int sng_exp:8;
u_int sng_sign:1;
};
struct ieee_double {
u_int dbl_fracl;
u_int dbl_frach:20;
u_int dbl_exp:11;
u_int dbl_sign:1;
};
struct ieee_ext {
u_int ext_fracl;
u_int ext_fraclm;
u_int ext_frachm;
u_int ext_frach:16;
u_int ext_exp:15;
u_int ext_sign:1;
};
/*
* Floats whose exponent is in [1..INFNAN) (of whatever type) are
* `normal'. Floats whose exponent is INFNAN are either Inf or NaN.
* Floats whose exponent is zero are either zero (iff all fraction
* bits are zero) or subnormal values.
*
* A NaN is a `signalling NaN' if its QUIETNAN bit is clear in its
* high fraction; if the bit is set, it is a `quiet NaN'.
*/
#define SNG_EXP_INFNAN 255
#define DBL_EXP_INFNAN 2047
#define EXT_EXP_INFNAN 32767
#if 0
#define SNG_QUIETNAN (1 << 22)
#define DBL_QUIETNAN (1 << 19)
#define EXT_QUIETNAN (1 << 15)
#endif
/*
* Exponent biases.
*/
#define SNG_EXP_BIAS 127
#define DBL_EXP_BIAS 1023
#define EXT_EXP_BIAS 16383

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/* $OpenBSD: ieeefp.h,v 1.2 2021/05/01 20:07:01 kettenis Exp $ */
/*
* Based on ieeefp.h written by J.T. Conklin, Apr 28, 1995
* Public domain.
*/
#ifndef _MACHINE_IEEEFP_H_
#define _MACHINE_IEEEFP_H_
typedef int fp_except;
#define FP_X_INV 0x01 /* invalid operation exception */
#define FP_X_DZ 0x02 /* divide-by-zero exception */
#define FP_X_OFL 0x04 /* overflow exception */
#define FP_X_UFL 0x08 /* underflow exception */
#define FP_X_IMP 0x10 /* imprecise (loss of precision) */
typedef enum {
FP_RN=0, /* round to nearest representable number */
FP_RP=1, /* round toward positive infinity */
FP_RM=2, /* round toward negative infinity */
FP_RZ=3 /* round to zero (truncate) */
} fp_rnd;
#endif /* _MACHINE_IEEEFP_H_ */

226
lib/libc/include/aarch64-openbsd-none/arm64/intr.h vendored Normal file
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/* $OpenBSD: intr.h,v 1.25 2025/06/30 14:19:20 kettenis Exp $ */
/*
* Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#ifndef _MACHINE_INTR_H_
#define _MACHINE_INTR_H_
/*
* The interrupt level ipl is a logical level; per-platform interrupt
* code will turn it into the appropriate hardware interrupt masks
* values.
*
* Interrupt sources on the CPU are kept enabled regardless of the
* current ipl value; individual hardware sources interrupting while
* logically masked are masked on the fly, remembered as pending, and
* unmasked at the first splx() opportunity.
*/
#ifdef _KERNEL
/* Interrupt priority `levels'; not mutually exclusive. */
#define IPL_NONE 0 /* nothing */
#define IPL_SOFTCLOCK 2 /* soft clock interrupts */
#define IPL_SOFTNET 3 /* soft network interrupts */
#define IPL_SOFTTTY 4 /* soft terminal interrupts */
#define IPL_BIO 5 /* block I/O */
#define IPL_NET 6 /* network */
#define IPL_TTY 7 /* terminal */
#define IPL_VM 8 /* memory allocation */
#define IPL_AUDIO 9 /* audio */
#define IPL_CLOCK 10 /* clock */
#define IPL_SCHED IPL_CLOCK
#define IPL_STATCLOCK IPL_CLOCK
#define IPL_HIGH 11 /* everything */
#define IPL_IPI 12 /* interprocessor interrupt */
#define NIPL 13 /* number of levels */
#define IPL_MPFLOOR IPL_TTY
/* Interrupt priority 'flags'. */
#define IPL_IRQMASK 0xf /* priority only */
#define IPL_FLAGMASK 0xf00 /* flags only*/
#define IPL_MPSAFE 0x100 /* 'mpsafe' interrupt, no kernel lock */
#define IPL_WAKEUP 0x200 /* 'wakeup' interrupt */
/* Interrupt sharing types. */
#define IST_NONE 0 /* none */
#define IST_PULSE 1 /* pulsed */
#define IST_EDGE 2 /* edge-triggered */
#define IST_LEVEL 3 /* level-triggered */
#define IST_LEVEL_LOW IST_LEVEL
#define IST_LEVEL_HIGH 4
#define IST_EDGE_FALLING IST_EDGE
#define IST_EDGE_RISING 5
#define IST_EDGE_BOTH 6
#define __USE_MI_SOFTINTR
#include <sys/softintr.h>
#ifndef _LOCORE
#include <sys/queue.h>
void softintr(int);
int splraise(int);
int spllower(int);
void splx(int);
void arm_do_pending_intr(int);
void arm_set_intr_handler(int (*)(int), int (*)(int), void (*)(int),
void (*)(int), void (*)(void *), void (*)(void *),
void (*)(void), void (*)(void));
struct machine_intr_handle {
struct interrupt_controller *ih_ic;
void *ih_ih;
};
struct arm_intr_func {
int (*raise)(int);
int (*lower)(int);
void (*x)(int);
void (*setipl)(int);
void (*enable_wakeup)(void);
void (*disable_wakeup)(void);
};
extern struct arm_intr_func arm_intr_func;
#define splraise(cpl) (arm_intr_func.raise(cpl))
#define _splraise(cpl) (arm_intr_func.raise(cpl))
#define spllower(cpl) (arm_intr_func.lower(cpl))
#define splx(cpl) (arm_intr_func.x(cpl))
#define splsoftclock() splraise(IPL_SOFTCLOCK)
#define splsoftnet() splraise(IPL_SOFTNET)
#define splsofttty() splraise(IPL_SOFTTTY)
#define splbio() splraise(IPL_BIO)
#define splnet() splraise(IPL_NET)
#define spltty() splraise(IPL_TTY)
#define splvm() splraise(IPL_VM)
#define splaudio() splraise(IPL_AUDIO)
#define splclock() splraise(IPL_CLOCK)
#define splsched() splraise(IPL_SCHED)
#define splstatclock() splraise(IPL_STATCLOCK)
#define splhigh() splraise(IPL_HIGH)
#define spl0() spllower(IPL_NONE)
void intr_barrier(void *);
void intr_set_wakeup(void *);
void intr_enable_wakeup(void);
void intr_disable_wakeup(void);
void arm_init_smask(void); /* XXX */
extern uint32_t arm_smask[NIPL];
/* XXX - this is probably the wrong location for this */
void arm_clock_register(void (*)(void), void (*)(u_int), void (*)(int),
void (*)(void));
struct cpu_info;
struct interrupt_controller {
int ic_node;
void *ic_cookie;
void *(*ic_establish)(void *, int *, int, struct cpu_info *,
int (*)(void *), void *, char *);
void *(*ic_establish_msi)(void *, uint64_t *, uint64_t *, int,
struct cpu_info *, int (*)(void *), void *, char *);
void (*ic_disestablish)(void *);
void (*ic_enable)(void *);
void (*ic_disable)(void *);
void (*ic_route)(void *, int, struct cpu_info *);
void (*ic_cpu_enable)(void);
void (*ic_barrier)(void *);
void (*ic_set_wakeup)(void *);
LIST_ENTRY(interrupt_controller) ic_list;
uint32_t ic_phandle;
uint32_t ic_cells;
uint32_t ic_gic_its_id;
};
void arm_intr_init_fdt(void);
void arm_intr_register_fdt(struct interrupt_controller *);
void *arm_intr_establish_fdt(int, int, int (*)(void *),
void *, char *);
void *arm_intr_establish_fdt_cpu(int, int, struct cpu_info *,
int (*)(void *), void *, char *);
void *arm_intr_establish_fdt_idx(int, int, int, int (*)(void *),
void *, char *);
void *arm_intr_establish_fdt_idx_cpu(int, int, int, struct cpu_info *,
int (*)(void *), void *, char *);
void *arm_intr_establish_fdt_imap(int, int *, int, int, int (*)(void *),
void *, char *);
void *arm_intr_establish_fdt_imap_cpu(int, int *, int, int,
struct cpu_info *, int (*)(void *), void *, char *);
void *arm_intr_establish_fdt_msi(int, uint64_t *, uint64_t *, int,
int (*)(void *), void *, char *);
void *arm_intr_establish_fdt_msi_cpu(int, uint64_t *, uint64_t *, int,
struct cpu_info *, int (*)(void *), void *, char *);
void arm_intr_disestablish_fdt(void *);
void arm_intr_enable(void *);
void arm_intr_disable(void *);
void arm_intr_route(void *, int, struct cpu_info *);
void arm_intr_cpu_enable(void);
void *arm_intr_parent_establish_fdt(void *, int *, int,
struct cpu_info *ci, int (*)(void *), void *, char *);
void arm_intr_parent_disestablish_fdt(void *);
void arm_send_ipi(struct cpu_info *, int);
extern void (*intr_send_ipi_func)(struct cpu_info *, int);
#define ARM_IPI_NOP 0
#define ARM_IPI_DDB 1
#define ARM_IPI_HALT 2
#ifdef DIAGNOSTIC
/*
* Although this function is implemented in MI code, it must be in this MD
* header because we don't want this header to include MI includes.
*/
void splassert_fail(int, int, const char *);
extern int splassert_ctl;
void arm_splassert_check(int, const char *);
#define splassert(__wantipl) do { \
if (splassert_ctl > 0) { \
arm_splassert_check(__wantipl, __func__); \
} \
} while (0)
#define splsoftassert(wantipl) splassert(wantipl)
#else
#define splassert(wantipl) do { /* nothing */ } while (0)
#define splsoftassert(wantipl) do { /* nothing */ } while (0)
#endif
#endif /* ! _LOCORE */
#endif /* _KERNEL */
#endif /* _MACHINE_INTR_H_ */

15
lib/libc/include/aarch64-openbsd-none/arm64/kcore.h vendored Normal file
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/* $OpenBSD: kcore.h,v 1.1 2016/12/17 23:38:33 patrick Exp $ */
/* public domain */
/* Make sure this is larger than DRAM_BLOCKS on all arm-based platforms */
#define NPHYS_RAM_SEGS 8
typedef struct cpu_kcore_hdr {
u_int64_t kernelbase; /* value of KERNEL_BASE */
u_int64_t kerneloffs; /* offset of kernel in RAM */
u_int64_t staticsize; /* size of contiguous mapping */
u_int64_t pmap_kernel_l1; /* pmap_kernel()->pm_l1 */
u_int64_t pmap_kernel_l2; /* pmap_kernel()->pm_l2 */
u_int64_t reserved[11];
phys_ram_seg_t ram_segs[NPHYS_RAM_SEGS];
} cpu_kcore_hdr_t;

56
lib/libc/include/aarch64-openbsd-none/arm64/limits.h vendored Normal file
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/* $OpenBSD: limits.h,v 1.1 2016/12/17 23:38:33 patrick Exp $ */
/* $NetBSD: limits.h,v 1.4 2003/04/28 23:16:18 bjh21 Exp $ */
/*
* Copyright (c) 1988 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)limits.h 7.2 (Berkeley) 6/28/90
*/
#ifndef _MACHINE_LIMITS_H_
#define _MACHINE_LIMITS_H_
#include <sys/cdefs.h>
#if __POSIX_VISIBLE || __XPG_VISIBLE
#ifndef SIZE_MAX
#define SIZE_MAX ULONG_MAX /* max value for a size_t */
#endif
#define SSIZE_MAX LONG_MAX /* max value for a ssize_t */
#endif
#if __BSD_VISIBLE
#define SIZE_T_MAX ULONG_MAX /* max value for a size_t (historic) */
#define UQUAD_MAX 0xffffffffffffffffULL /* max unsigned quad */
#define QUAD_MAX 0x7fffffffffffffffLL /* max signed quad */
#define QUAD_MIN (-0x7fffffffffffffffLL-1) /* min signed quad */
#endif /* __BSD_VISIBLE */
#endif /* _MACHINE_LIMITS_H_ */

53
lib/libc/include/aarch64-openbsd-none/arm64/loadfile_machdep.h vendored Normal file
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/* $OpenBSD: loadfile_machdep.h,v 1.2 2019/04/10 04:17:34 deraadt Exp $ */
/* $NetBSD: loadfile_machdep.h,v 1.1 1999/04/29 03:17:12 tsubai Exp $ */
/*-
* Copyright (c) 1999 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Christos Zoulas.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#define BOOT_ELF
#define ELFSIZE 64
#define LOAD_KERNEL (LOAD_ALL & ~LOAD_TEXTA)
#define COUNT_KERNEL (COUNT_ALL & ~COUNT_TEXTA)
extern u_long efi_loadaddr;
#define LOADADDR(a) (((((u_long)(a)) + offset)&0x7fffffffff) + \
efi_loadaddr)
#define ALIGNENTRY(a) ((u_long)(a))
#define READ(f, b, c) read((f), (void *)LOADADDR(b), (c))
#define BCOPY(s, d, c) memcpy((void *)LOADADDR(d), (void *)(s), (c))
#define BZERO(d, c) memset((void *)LOADADDR(d), 0, (c))
#define WARN(a) (void)(printf a, \
printf((errno ? ": %s\n" : "\n"), \
strerror(errno)))
#define PROGRESS(a) (void) printf a
#define ALLOC(a) alloc(a)
#define FREE(a, b) free(a, b)
void run_loadfile(uint64_t *, int);

10
lib/libc/include/aarch64-openbsd-none/arm64/mplock.h vendored Normal file
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/* $OpenBSD: mplock.h,v 1.3 2018/01/05 17:42:35 kettenis Exp $ */
/* public domain */
#ifndef _MACHINE_MPLOCK_H_
#define _MACHINE_MPLOCK_H_
#define __USE_MI_MPLOCK
#endif /* !_MACHINE_MPLOCK_H */

3
lib/libc/include/aarch64-openbsd-none/arm64/mutex.h vendored Normal file
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/* $OpenBSD: mutex.h,v 1.5 2018/01/25 15:06:29 mpi Exp $ */
#define __USE_MI_MUTEX

57
lib/libc/include/aarch64-openbsd-none/arm64/openpromio.h vendored Normal file
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/* $OpenBSD: openpromio.h,v 1.1 2017/01/23 12:34:06 kettenis Exp $ */
/* $NetBSD: openpromio.h,v 1.1.1.1 1998/06/20 04:58:52 eeh Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)openpromio.h 8.1 (Berkeley) 6/11/93
*/
struct opiocdesc {
int op_nodeid; /* passed or returned node id */
int op_namelen; /* length of op_name */
char *op_name; /* pointer to field name */
int op_buflen; /* length of op_buf (value-result) */
char *op_buf; /* pointer to field value */
};
#define OPIOCGET _IOWR('O', 1, struct opiocdesc) /* get openprom field */
#define OPIOCSET _IOW('O', 2, struct opiocdesc) /* set openprom field */
#define OPIOCNEXTPROP _IOWR('O', 3, struct opiocdesc) /* get next property */
#define OPIOCGETOPTNODE _IOR('O', 4, int) /* get openprom field */
#define OPIOCGETNEXT _IOWR('O', 5, int) /* get next node of node */
#define OPIOCGETCHILD _IOWR('O', 6, int) /* get first child of node */

81
lib/libc/include/aarch64-openbsd-none/arm64/param.h vendored Normal file
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/* $OpenBSD: param.h,v 1.8 2025/07/07 18:33:36 kettenis Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* William Jolitz.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE_PARAM_H_
#define _MACHINE_PARAM_H_
#ifdef _KERNEL
#ifndef _LOCORE
#include <machine/cpu.h>
#endif
#endif
#define _MACHINE arm64
#define MACHINE "arm64"
#define _MACHINE_ARCH aarch64
#define MACHINE_ARCH "aarch64"
#define MID_MACHINE MID_ARM64
#define PAGE_SHIFT 12
#define PAGE_SIZE (1 << PAGE_SHIFT)
#define PAGE_MASK (PAGE_SIZE - 1)
#define KERNBASE 0xffffff8000000000ULL /* start of kernel virtual space */
#ifdef _KERNEL
#define NBPG PAGE_SIZE /* bytes/page */
#define PGSHIFT PAGE_SHIFT /* LOG2(PAGE_SIZE) */
#define PGOFSET PAGE_MASK /* byte offset into page */
#define UPAGES 6 /* pages of u-area */
#define USPACE (UPAGES * PAGE_SIZE) /* total size of u-area */
#define USPACE_ALIGN 0 /* u-area alignment 0-none */
#define __HAVE_USPACE_GUARD
#define NMBCLUSTERS (64 * 1024) /* max cluster allocation */
#ifndef MSGBUFSIZE
#define MSGBUFSIZE (16 * PAGE_SIZE) /* default message buffer size */
#endif
#define STACKALIGNBYTES (16 - 1)
#define STACKALIGN(p) ((u_long)(p) &~ STACKALIGNBYTES)
#define __HAVE_ACPI
#define __HAVE_FDT
#endif /* _KERNEL */
#endif /* _MACHINE_PARAM_H_ */

45
lib/libc/include/aarch64-openbsd-none/arm64/pcb.h vendored Normal file
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/* $OpenBSD: pcb.h,v 1.8 2025/02/24 13:18:01 jsg Exp $ */
/*
* Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_PCB_H_
#define _MACHINE_PCB_H_
#include <machine/frame.h>
#include <machine/reg.h>
struct trapframe;
/*
* Warning certain fields must be within 256 bytes of the beginning
* of this structure.
*/
struct pcb {
u_int pcb_flags;
#define PCB_FPU 0x00000001 /* Process had FPU initialized */
#define PCB_SINGLESTEP 0x00000002 /* Single step process */
#define PCB_SVE 0x00000004 /* Process had SVE initialized */
struct trapframe *pcb_tf;
register_t pcb_sp; /* stack pointer of switchframe */
caddr_t pcb_onfault; /* On fault handler */
struct fpreg pcb_fpstate; /* Floating Point state */
__uint16_t pcb_sve_p[16]; /* SVE predicate registers */
__uint16_t pcb_sve_ffr; /* SVE first fault register */
void *pcb_tcb;
};
#endif /* _MACHINE_PCB_H_ */

145
lib/libc/include/aarch64-openbsd-none/arm64/pci_machdep.h vendored Normal file
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/* $OpenBSD: pci_machdep.h,v 1.13 2025/01/23 11:24:34 kettenis Exp $ */
/*
* Copyright (c) 2003-2004 Opsycon AB (www.opsycon.se / www.opsycon.com)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
typedef struct machine_pci_chipset *pci_chipset_tag_t;
typedef uint64_t pcitag_t;
#define PCITAG_NODE(x) ((x) >> 32)
#define PCITAG_OFFSET(x) ((x) & 0xffffffff)
/* Supported interrupt types. */
#define PCI_NONE 0
#define PCI_INTX 1
#define PCI_MSI 2
#define PCI_MSIX 3
typedef struct {
pci_chipset_tag_t ih_pc;
pcitag_t ih_tag;
int ih_intrpin;
int ih_type;
bus_dma_tag_t ih_dmat;
} pci_intr_handle_t;
struct pci_attach_args;
/*
* Machine-specific PCI structure and type definitions.
* NOT TO BE USED DIRECTLY BY MACHINE INDEPENDENT CODE.
*/
struct machine_pci_chipset {
void *pc_conf_v;
void (*pc_attach_hook)(struct device *,
struct device *, struct pcibus_attach_args *);
int (*pc_bus_maxdevs)(void *, int);
pcitag_t (*pc_make_tag)(void *, int, int, int);
void (*pc_decompose_tag)(void *, pcitag_t, int *,
int *, int *);
int (*pc_conf_size)(void *, pcitag_t);
pcireg_t (*pc_conf_read)(void *, pcitag_t, int);
void (*pc_conf_write)(void *, pcitag_t, int, pcireg_t);
int (*pc_probe_device_hook)(void *, struct pci_attach_args *);
void *pc_intr_v;
int (*pc_intr_map)(struct pci_attach_args *,
pci_intr_handle_t *);
int (*pc_intr_map_msi)(struct pci_attach_args *,
pci_intr_handle_t *);
int (*pc_intr_map_msivec)(struct pci_attach_args *,
int, pci_intr_handle_t *);
int (*pc_intr_map_msix)(struct pci_attach_args *,
int, pci_intr_handle_t *);
const char *(*pc_intr_string)(void *, pci_intr_handle_t);
void *(*pc_intr_establish)(void *, pci_intr_handle_t,
int, struct cpu_info *, int (*)(void *), void *,
char *);
void (*pc_intr_disestablish)(void *, void *);
};
/*
* Functions provided to machine-independent PCI code.
*/
#define pci_attach_hook(p, s, pba) \
(*(pba)->pba_pc->pc_attach_hook)((p), (s), (pba))
#define pci_bus_maxdevs(c, b) \
(*(c)->pc_bus_maxdevs)((c)->pc_conf_v, (b))
#define pci_make_tag(c, b, d, f) \
(*(c)->pc_make_tag)((c)->pc_conf_v, (b), (d), (f))
#define pci_decompose_tag(c, t, bp, dp, fp) \
(*(c)->pc_decompose_tag)((c)->pc_conf_v, (t), (bp), (dp), (fp))
#define pci_conf_size(c, t) \
(*(c)->pc_conf_size)((c)->pc_conf_v, (t))
#define pci_conf_read(c, t, r) \
(*(c)->pc_conf_read)((c)->pc_conf_v, (t), (r))
#define pci_conf_write(c, t, r, v) \
(*(c)->pc_conf_write)((c)->pc_conf_v, (t), (r), (v))
#define pci_probe_device_hook(c, a) \
(*(c)->pc_probe_device_hook)((c)->pc_conf_v, (a))
#define pci_intr_map(c, ihp) \
(*(c)->pa_pc->pc_intr_map)((c), (ihp))
#define pci_intr_map_msi(c, ihp) \
(*(c)->pa_pc->pc_intr_map_msi)((c), (ihp))
#define pci_intr_map_msivec(c, vec, ihp) \
(*(c)->pa_pc->pc_intr_map_msivec)((c), (vec), (ihp))
#define pci_intr_map_msix(c, vec, ihp) \
(*(c)->pa_pc->pc_intr_map_msix)((c), (vec), (ihp))
#define pci_intr_string(c, ih) \
(*(c)->pc_intr_string)((c)->pc_intr_v, (ih))
#define pci_intr_establish(c, ih, l, h, a, nm) \
(*(c)->pc_intr_establish)((c)->pc_intr_v, (ih), (l), NULL, (h), (a),\
(nm))
#define pci_intr_establish_cpu(c, ih, l, ci, h, a, nm) \
(*(c)->pc_intr_establish)((c)->pc_intr_v, (ih), (l), (ci), (h), (a),\
(nm))
#define pci_intr_disestablish(c, iv) \
(*(c)->pc_intr_disestablish)((c)->pc_intr_v, (iv))
#define pci_min_powerstate(c, t) (PCI_PMCSR_STATE_D3)
#define pci_set_powerstate_md(c, t, s, p)
#define pci_dev_postattach(a, b)
void pci_mcfg_init(bus_space_tag_t, bus_addr_t, int, int, int);
pci_chipset_tag_t pci_lookup_segment(int, int);
int pci_intr_enable_msivec(struct pci_attach_args *, int);
void pci_msi_enable(pci_chipset_tag_t, pcitag_t, bus_addr_t, uint32_t);
void pci_msix_enable(pci_chipset_tag_t, pcitag_t, bus_space_tag_t,
int, bus_addr_t, uint32_t);
int _pci_intr_map_msi(struct pci_attach_args *, pci_intr_handle_t *);
int _pci_intr_map_msivec(struct pci_attach_args *, int,
pci_intr_handle_t *);
int _pci_intr_map_msix(struct pci_attach_args *, int, pci_intr_handle_t *);
#define __HAVE_PCI_MSIX
int pci_msix_table_map(pci_chipset_tag_t, pcitag_t,
bus_space_tag_t, bus_space_handle_t *);
void pci_msix_table_unmap(pci_chipset_tag_t, pcitag_t,
bus_space_tag_t, bus_space_handle_t);

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lib/libc/include/aarch64-openbsd-none/arm64/pmap.h vendored Normal file
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/* $OpenBSD: pmap.h,v 1.29 2025/05/21 09:42:59 kettenis Exp $ */
/*
* Copyright (c) 2008,2009,2014 Dale Rahn <drahn@dalerahn.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ARM64_PMAP_H_
#define _ARM64_PMAP_H_
#ifndef _LOCORE
#include <sys/mutex.h>
#include <sys/queue.h>
#include <machine/pte.h>
#endif
/* V->P mapping data */
#define VP_IDX0_CNT 512
#define VP_IDX0_MASK (VP_IDX0_CNT-1)
#define VP_IDX0_POS 39
#define VP_IDX1_CNT 512
#define VP_IDX1_MASK (VP_IDX1_CNT-1)
#define VP_IDX1_POS 30
#define VP_IDX2_CNT 512
#define VP_IDX2_MASK (VP_IDX2_CNT-1)
#define VP_IDX2_POS 21
#define VP_IDX3_CNT 512
#define VP_IDX3_MASK (VP_IDX3_CNT-1)
#define VP_IDX3_POS 12
/* cache flags */
#define PMAP_CACHE_CI (PMAP_MD0) /* cache inhibit */
#define PMAP_CACHE_WT (PMAP_MD1) /* writethru */
#define PMAP_CACHE_WB (PMAP_MD1|PMAP_MD0) /* writeback */
#define PMAP_CACHE_DEV_NGNRNE (PMAP_MD2) /* device nGnRnE */
#define PMAP_CACHE_DEV_NGNRE (PMAP_MD2|PMAP_MD0) /* device nGnRE */
#define PMAP_CACHE_BITS (PMAP_MD0|PMAP_MD1|PMAP_MD2)
#define PTED_VA_MANAGED_M (PMAP_MD3)
#define PTED_VA_WIRED_M (PMAP_MD3 << 1)
#if defined(_KERNEL) && !defined(_LOCORE)
/*
* Pmap stuff
*/
typedef struct pmap *pmap_t;
struct pmap {
struct mutex pm_mtx;
union {
struct pmapvp0 *l0; /* virtual to physical table 4 lvl */
struct pmapvp1 *l1; /* virtual to physical table 3 lvl */
} pm_vp;
uint64_t pm_pt0pa;
uint64_t pm_asid;
uint64_t pm_guarded;
int have_4_level_pt;
int pm_privileged;
volatile int pm_active;
int pm_refs; /* ref count */
struct pmap_statistics pm_stats; /* pmap statistics */
uint64_t pm_apiakey[2];
uint64_t pm_apdakey[2];
uint64_t pm_apibkey[2];
uint64_t pm_apdbkey[2];
uint64_t pm_apgakey[2];
};
#define PMAP_PA_MASK ~((paddr_t)PAGE_MASK) /* to remove the flags */
#define PMAP_NOCACHE 0x1 /* non-cacheable memory */
#define PMAP_DEVICE 0x2 /* device memory */
#define PMAP_WC PMAP_DEVICE
#define PG_PMAP_MOD PG_PMAP0
#define PG_PMAP_REF PG_PMAP1
#define PG_PMAP_EXE PG_PMAP2
// [NCPUS]
extern paddr_t zero_page;
extern paddr_t copy_src_page;
extern paddr_t copy_dst_page;
void pagezero_cache(vaddr_t);
extern struct pmap kernel_pmap_;
#define pmap_kernel() (&kernel_pmap_)
#define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count)
#define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count)
vaddr_t pmap_bootstrap(long kvo, paddr_t lpt1, long kernelstart,
long kernelend, long ram_start, long ram_end);
void pmap_postinit(void);
void pmap_init_percpu(void);
void pmap_kenter_cache(vaddr_t va, paddr_t pa, vm_prot_t prot, int cacheable);
void pmap_page_ro(pmap_t pm, vaddr_t va, vm_prot_t prot);
void pmap_page_rw(pmap_t pm, vaddr_t va);
void pmap_setpauthkeys(struct pmap *);
paddr_t pmap_steal_avail(size_t size, int align, void **kva);
void pmap_avail_fixup(void);
void pmap_physload_avail(void);
#define PMAP_GROWKERNEL
struct pv_entry;
/* investigate */
#define pmap_unuse_final(p) do { /* nothing */ } while (0)
int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t);
#define __HAVE_PMAP_MPSAFE_ENTER_COW
#define __HAVE_PMAP_POPULATE
#define __HAVE_PMAP_PURGE
#endif /* _KERNEL && !_LOCORE */
#ifndef _LOCORE
struct vm_page_md {
struct mutex pv_mtx;
LIST_HEAD(,pte_desc) pv_list;
};
#define VM_MDPAGE_INIT(pg) do { \
mtx_init(&(pg)->mdpage.pv_mtx, IPL_VM); \
LIST_INIT(&((pg)->mdpage.pv_list)); \
} while (0)
#endif /* _LOCORE */
#endif /* _ARM64_PMAP_H_ */

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/* $OpenBSD: proc.h,v 1.2 2017/04/13 03:52:25 guenther Exp $ */
/* $NetBSD: proc.h,v 1.1 2003/04/26 18:39:46 fvdl Exp $ */
/*
* Copyright (c) 1991 Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)proc.h 7.1 (Berkeley) 5/15/91
*/
#ifndef _MACHINE_PROC_H_
#define _MACHINE_PROC_H_
/*
* Machine-dependent part of the proc structure for arm64.
*/
struct mdproc {
volatile int md_astpending;
};
#endif /* _MACHINE_PROC_H_ */

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/* $OpenBSD: profile.h,v 1.2 2021/02/17 12:11:45 kettenis Exp $ */
/*
* Copyright (c) 2015 Dale Rahn <drahn@dalerahn.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#define _MCOUNT_DECL void _mcount
#define MCOUNT_ASM_NAME "__mcount"
#ifdef __PIC__
#define PLTSYM "" /* XXX -aarch64 defaults to PLT? */
#else
#define PLTSYM ""
#endif
#define MCOUNT \
__asm__ (".text;" \
".align 3;" \
".globl " MCOUNT_ASM_NAME ";" \
".type " MCOUNT_ASM_NAME ",@function;" \
MCOUNT_ASM_NAME ":;" \
" stp x0, x1, [sp, #-160]!;" \
" stp x2, x3, [sp, #16];" \
" stp x4, x5, [sp, #32];" \
" stp x6, x7, [sp, #48];" \
" stp x8, x9, [sp, #64];" \
" stp x10,x11,[sp, #80];" \
" stp x12,x13,[sp, #96];" \
" stp x14,x15,[sp, #112];" \
" stp x16,x17,[sp, #128];" \
" stp x29,lr, [sp, #144];" \
/* load from pc at 8 off frame pointer */ \
" ldr x0, [x29, #8];" \
" mov x1, lr;" \
" bl " __STRING(_mcount) PLTSYM ";" \
/* restore argument registers */ \
" ldp x2, x3, [sp, #16];" \
" ldp x4, x5, [sp, #32];" \
" ldp x6, x7, [sp, #48];" \
" ldp x8, x9, [sp, #64];" \
" ldp x10,x11,[sp, #80];" \
" ldp x12,x13,[sp, #96];" \
" ldp x14,x15,[sp, #112];" \
" ldp x16,x17,[sp, #128];" \
" ldp x29,lr, [sp, #144];" \
" ldp x0, x1, [sp], #160;" \
" ret;");
#ifdef _KERNEL
// Change this to dair read/set, then restore.
#define MCOUNT_ENTER \
__asm__ ("mrs %x0, daif; msr daifset, #0x3": "=r"(s));
#define MCOUNT_EXIT \
__asm__ ("msr daif, %x0":: "r"(s));
#endif // _KERNEL

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/* $OpenBSD: pte.h,v 1.10 2024/10/14 12:02:16 jsg Exp $ */
/*
* Copyright (c) 2014 Dale Rahn <drahn@dalerahn.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ARM_PTE_H_
#define _ARM_PTE_H_
/* level X descriptor */
#define Lx_TYPE_MASK (0x00000003) /* mask of type bits */
#define Lx_TYPE_S (0x00000001)
#define Lx_TYPE_PT (0x00000003)
// XXX need to investigate use of these
#define Lx_PT_NS (1ULL<<63)
#define Lx_PT_AP00 (0ULL<<61)
#define Lx_PT_AP01 (1ULL<<61)
#define Lx_PT_AP10 (2ULL<<61)
#define Lx_PT_AP11 (3ULL<<61)
#define Lx_PT_XN (1ULL<<60)
#define Lx_PT_PXN (1ULL<<59)
#define Lx_TABLE_ALIGN (4096)
/* Block and Page attributes */
/* TODO: Add the upper attributes */
#define ATTR_MASK_H (0xfff0000000000000ULL)
#define ATTR_MASK_L (0x0000000000000fffULL)
#define ATTR_MASK (ATTR_MASK_H | ATTR_MASK_L)
/* Bits 58:55 are reserved for software */
#define ATTR_SW_MANAGED (1UL << 56)
#define ATTR_SW_WIRED (1UL << 55)
#define ATTR_UXN (1UL << 54)
#define ATTR_PXN (1UL << 53)
#define ATTR_GP (1UL << 50)
#define ATTR_nG (1 << 11)
#define ATTR_AF (1 << 10)
#define ATTR_SH(x) ((x) << 8)
#define ATTR_AP_RW_BIT (1 << 7)
#define ATTR_AP(x) ((x) << 6)
#define ATTR_AP_MASK ATTR_AP(3)
#define ATTR_NS (1 << 5)
#define ATTR_IDX(x) ((x) << 2)
#define ATTR_IDX_MASK (7 << 2)
#define PTE_ATTR_DEV_NGNRNE 0
#define PTE_ATTR_DEV_NGNRE 1
#define PTE_ATTR_CI 2
#define PTE_ATTR_WB 3
#define PTE_ATTR_WT 4
#define PTE_MEMATTR_DEV_NGNRNE 0x0
#define PTE_MEMATTR_DEV_NGNRE 0x1
#define PTE_MEMATTR_CI 0x5
#define PTE_MEMATTR_WB 0xf
#define PTE_MEMATTR_WT 0xa
#define SH_INNER 3
#define SH_OUTER 2
#define SH_NONE 0
/* Level 0 table, 512GiB per entry */
#define L0_SHIFT 39
#define L0_INVAL 0x0 /* An invalid address */
#define L0_BLOCK 0x1 /* A block */
/* 0x2 also marks an invalid address */
#define L0_TABLE 0x3 /* A next-level table */
/* Level 1 table, 1GiB per entry */
#define L1_SHIFT 30
#define L1_SIZE (1 << L1_SHIFT)
#define L1_OFFSET (L1_SIZE - 1)
#define L1_INVAL L0_INVAL
#define L1_BLOCK L0_BLOCK
#define L1_TABLE L0_TABLE
/* Level 2 table, 2MiB per entry */
#define L2_SHIFT 21
#define L2_SIZE (1 << L2_SHIFT)
#define L2_OFFSET (L2_SIZE - 1)
#define L2_INVAL L0_INVAL
#define L2_BLOCK L0_BLOCK
#define L2_TABLE L0_TABLE
/* page mapping */
#define L3_P 0x3
#define Ln_ENTRIES (1 << 9)
#define Ln_ADDR_MASK (Ln_ENTRIES - 1)
#define Ln_TABLE_MASK ((1 << 12) - 1)
/* physical page mask */
#define PTE_RPGN (((1ULL << 48) - 1) & ~PAGE_MASK)
#endif /* _ARM_PTE_H_ */

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/* $OpenBSD: ptrace.h,v 1.2 2023/06/10 19:30:48 kettenis Exp $ */
/*
* Copyright (c) 2014 Patrick Wildt <patrick@blueri.se>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#define PT_STEP (PT_FIRSTMACH + 0)
#define PT_GETREGS (PT_FIRSTMACH + 1)
#define PT_SETREGS (PT_FIRSTMACH + 2)
#define PT_GETFPREGS (PT_FIRSTMACH + 3)
#define PT_SETFPREGS (PT_FIRSTMACH + 4)
#define PT_PACMASK (PT_FIRSTMACH + 5)
#ifdef _KERNEL
register_t process_get_pacmask(struct proc *p);
#endif

36
lib/libc/include/aarch64-openbsd-none/arm64/reg.h vendored Normal file
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/* $OpenBSD: reg.h,v 1.3 2017/04/11 06:52:13 kettenis Exp $ */
/*
* Copyright (c) 2014 Patrick Wildt <patrick@blueri.se>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_REG_H_
#define _MACHINE_REG_H_
struct reg {
uint64_t r_reg[30];
uint64_t r_lr;
uint64_t r_sp;
uint64_t r_pc;
uint64_t r_spsr;
uint64_t r_tpidr;
};
struct fpreg {
__uint128_t fp_reg[32];
uint32_t fp_sr;
uint32_t fp_cr;
};
#endif /* !_MACHINE_REG_H_ */

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lib/libc/include/aarch64-openbsd-none/arm64/reloc.h vendored Normal file
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/* $OpenBSD: reloc.h,v 1.2 2017/10/24 20:35:54 guenther Exp $ */
/*
* AArch64 static relocation types.
*/
/* Miscellaneous. */
#define R_ARM_NONE 0
#define R_AARCH64_TPOFF64 1 /// COMPLETELY WRONG - stub
#define R_AARCH64_NONE 0
/* Data. */
#define R_AARCH64_ABS64 257
#define R_AARCH64_ABS32 258
#define R_AARCH64_ABS16 259
#define R_AARCH64_PREL64 260
#define R_AARCH64_PREL32 261
#define R_AARCH64_PREL16 262
/* Instructions. */
#define R_AARCH64_MOVW_UABS_G0 263
#define R_AARCH64_MOVW_UABS_G0_NC 264
#define R_AARCH64_MOVW_UABS_G1 265
#define R_AARCH64_MOVW_UABS_G1_NC 266
#define R_AARCH64_MOVW_UABS_G2 267
#define R_AARCH64_MOVW_UABS_G2_NC 268
#define R_AARCH64_MOVW_UABS_G3 269
#define R_AARCH64_MOVW_SABS_G0 270
#define R_AARCH64_MOVW_SABS_G1 271
#define R_AARCH64_MOVW_SABS_G2 272
#define R_AARCH64_LD_PREL_LO19 273
#define R_AARCH64_ADR_PREL_LO21 274
#define R_AARCH64_ADR_PREL_PG_HI21 275
#define R_AARCH64_ADR_PREL_PG_HI21_NC 276
#define R_AARCH64_ADD_ABS_LO12_NC 277
#define R_AARCH64_LDST8_ABS_LO12_NC 278
#define R_AARCH64_TSTBR14 279
#define R_AARCH64_CONDBR19 280
#define R_AARCH64_JUMP26 282
#define R_AARCH64_CALL26 283
#define R_AARCH64_LDST16_ABS_LO12_NC 284
#define R_AARCH64_LDST32_ABS_LO12_NC 285
#define R_AARCH64_LDST64_ABS_LO12_NC 286
#define R_AARCH64_LDST128_ABS_LO12_NC 299
#define R_AARCH64_MOVW_PREL_G0 287
#define R_AARCH64_MOVW_PREL_G0_NC 288
#define R_AARCH64_MOVW_PREL_G1 289
#define R_AARCH64_MOVW_PREL_G1_NC 290
#define R_AARCH64_MOVW_PREL_G2 291
#define R_AARCH64_MOVW_PREL_G2_NC 292
#define R_AARCH64_MOVW_PREL_G3 293
#define R_AARCH64_COPY 1024
#define R_AARCH64_GLOB_DAT 1025 // S + A
#define R_AARCH64_JUMP_SLOT 1026 // S + A
#define R_AARCH64_RELATIVE 1027 // Delta(S) + A
#define R_AARCH64_TLS_DTPREL64 1028 // DTPREL(S+A)
#define R_AARCH64_TLS_DTPMOD64 1029 // LDM(S)
#define R_AARCH64_TLS_TPREL64 1030 // TPREL(S+A)
#define R_AARCH64_TLSDESC 1031 // TLSDESC(S+A) TLS descriptor to be filled
#define R_AARCH64_IRELATIVE 1032 // Indirect(Delta(S) + A)
// old arm32 defines.
/* Processor specific relocation types */
#define R_ARM_NONE 0
#define R_ARM_PC24 1
#define R_ARM_ABS32 2
#define R_ARM_REL32 3
#define R_ARM_PC13 4
#define R_ARM_ABS16 5
#define R_ARM_ABS12 6
#define R_ARM_THM_ABS5 7
#define R_ARM_ABS8 8
#define R_ARM_SBREL32 9
#define R_ARM_THM_PC22 10
#define R_ARM_THM_PC8 11
#define R_ARM_AMP_VCALL9 12
#define R_ARM_SWI24 13
#define R_ARM_THM_SWI8 14
#define R_ARM_XPC25 15
#define R_ARM_THM_XPC22 16
/* 17-31 are reserved for ARM Linux. */
#define R_ARM_TLS_DTPMOD32 17
#define R_ARM_TLS_DTPOFF32 18
#define R_ARM_TLS_TPOFF32 19
#define R_ARM_COPY 20
#define R_ARM_GLOB_DAT 21
#define R_ARM_JUMP_SLOT 22
#define R_ARM_RELATIVE 23
#define R_ARM_GOTOFF 24
#define R_ARM_GOTPC 25
#define R_ARM_GOT32 26
#define R_ARM_PLT32 27
#define R_ARM_ALU_PCREL_7_0 32
#define R_ARM_ALU_PCREL_15_8 33
#define R_ARM_ALU_PCREL_23_15 34
#define R_ARM_ALU_SBREL_11_0 35
#define R_ARM_ALU_SBREL_19_12 36
#define R_ARM_ALU_SBREL_27_20 37
/* 96-111 are reserved to G++. */
#define R_ARM_GNU_VTENTRY 100
#define R_ARM_GNU_VTINHERIT 101
#define R_ARM_THM_PC11 102
#define R_ARM_THM_PC9 103
/* 112-127 are reserved for private experiments. */
#define R_ARM_RXPC25 249
#define R_ARM_RSBREL32 250
#define R_ARM_THM_RPC22 251
#define R_ARM_RREL32 252
#define R_ARM_RABS32 253
#define R_ARM_RPC24 254
#define R_ARM_RBASE 255

83
lib/libc/include/aarch64-openbsd-none/arm64/setjmp.h vendored Normal file
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/* $OpenBSD: setjmp.h,v 1.2 2023/04/11 00:45:07 jsg Exp $ */
/* $NetBSD: setjmp.h,v 1.2 2001/08/25 14:45:59 bjh21 Exp $ */
/*
* machine/setjmp.h: machine dependent setjmp-related information.
*/
#define _JBLEN 64 /* size, in longs, of a jmp_buf */
/*
* NOTE: The internal structure of a jmp_buf is *PRIVATE*
* This information is provided as there is software
* that fiddles with this with obtain the stack pointer
* (yes really ! and it's commercial !).
*
* Description of the setjmp buffer
*
* word 0 magic number (dependant on creator)
* 1 - 3 f4 fp register 4
* 4 - 6 f5 fp register 5
* 7 - 9 f6 fp register 6
* 10 - 12 f7 fp register 7
* 13 fpsr fp status register
* 14 r4 register 4
* 15 r5 register 5
* 16 r6 register 6
* 17 r7 register 7
* 18 r8 register 8
* 19 r9 register 9
* 20 r10 register 10 (sl)
* 21 r11 register 11 (fp)
* 22 r12 register 12 (ip)
* 23 r13 register 13 (sp)
* 24 r14 register 14 (lr)
* 25 signal mask (dependant on magic)
* 26 (con't)
* 27 (con't)
* 28 (con't)
*
* The magic number identifies the jmp_buf and
* how the buffer was created as well as providing
* a sanity check.
*
* A side note I should mention - please do not tamper
* with the floating point fields. While they are
* always saved and restored at the moment this cannot
* be guaranteed especially if the compiler happens
* to be generating soft-float code so no fp
* registers will be used.
*
* Whilst this can be seen an encouraging people to
* use the setjmp buffer in this way I think that it
* is for the best then if changes occur compiles will
* break rather than just having new builds falling over
* mysteriously.
*/
#define _JB_MAGIC__SETJMP 0x4278f500
#define _JB_MAGIC_SETJMP 0x4278f501
/* Valid for all jmp_buf's */
#define _JB_MAGIC 0
#define _JB_REG_F4 1
#define _JB_REG_F5 4
#define _JB_REG_F6 7
#define _JB_REG_F7 10
#define _JB_REG_FPSR 13
#define _JB_REG_R4 14
#define _JB_REG_R5 15
#define _JB_REG_R6 16
#define _JB_REG_R7 17
#define _JB_REG_R8 18
#define _JB_REG_R9 19
#define _JB_REG_R10 20
#define _JB_REG_R11 21
#define _JB_REG_R12 22
#define _JB_REG_R13 23
#define _JB_REG_R14 24
/* Only valid with the _JB_MAGIC_SETJMP magic */
#define _JB_SIGMASK 25

64
lib/libc/include/aarch64-openbsd-none/arm64/signal.h vendored Normal file
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/* $OpenBSD: signal.h,v 1.2 2017/03/12 17:57:12 kettenis Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Ralph Campbell.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)signal.h 8.1 (Berkeley) 6/10/93
*/
#ifndef _MACHINE_SIGNAL_H_
#define _MACHINE_SIGNAL_H_
#include <sys/cdefs.h>
typedef int sig_atomic_t;
#if __BSD_VISIBLE || __XPG_VISIBLE >= 420
/*
* Information pushed on stack when a signal is delivered.
* This is used by the kernel to restore state following
* execution of the signal handler. It is also made available
* to the handler to allow it to restore state properly if
* a non-standard exit is performed.
*/
struct sigcontext {
int __sc_unused;
int sc_mask; /* signal mask to restore */
unsigned long sc_sp;
unsigned long sc_lr;
unsigned long sc_elr;
unsigned long sc_spsr;
unsigned long sc_x[30];
long sc_cookie;
};
#endif /* __BSD_VISIBLE || __XPG_VISIBLE >= 420 */
#endif /* !_MACHINE_SIGNAL_H_ */

37
lib/libc/include/aarch64-openbsd-none/arm64/simplebusvar.h vendored Normal file
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/* $OpenBSD: simplebusvar.h,v 1.1 2023/09/22 01:10:43 jsg Exp $ */
/*
* Copyright (c) 2016 Patrick Wildt <patrick@blueri.se>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
struct simplebus_softc {
struct device sc_dev;
int sc_node;
bus_space_tag_t sc_iot;
bus_dma_tag_t sc_dmat;
int sc_acells;
int sc_scells;
int sc_pacells;
int sc_pscells;
struct bus_space sc_bus;
struct machine_bus_dma_tag sc_dma;
int *sc_ranges;
int sc_rangeslen;
int *sc_dmaranges;
int sc_dmarangeslen;
int sc_early;
int sc_early_nodes[64];
};
extern void simplebus_attach(struct device *, struct device *, void *);

278
lib/libc/include/aarch64-openbsd-none/arm64/smbiosvar.h vendored Normal file
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/* $OpenBSD: smbiosvar.h,v 1.6 2025/07/15 01:09:32 jsg Exp $ */
/*
* Copyright (c) 2006 Gordon Willem Klok <gklok@cogeco.ca>
* Copyright (c) 2005 Jordan Hargrave
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE_SMBIOSVAR_
#define _MACHINE_SMBIOSVAR_
#define SMBIOS_UUID_NPRESENT 0x1
#define SMBIOS_UUID_NSET 0x2
/*
* Section 3.5 of "UUIDs and GUIDs" found at
* http://www.opengroup.org/dce/info/draft-leach-uuids-guids-01.txt
* specifies the string representation of a UUID.
*/
#define SMBIOS_UUID_REP "%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x"
#define SMBIOS_UUID_REPLEN 37 /* 16 zero padded values, 4 hyphens, 1 null */
struct smbios_entry {
uint8_t mjr;
uint8_t min;
uint8_t *addr;
uint16_t len;
uint16_t count;
};
struct smbhdr {
uint32_t sig; /* "_SM_" */
uint8_t checksum; /* Entry point checksum */
uint8_t len; /* Entry point structure length */
uint8_t majrev; /* Specification major revision */
uint8_t minrev; /* Specification minor revision */
uint16_t mss; /* Maximum Structure Size */
uint8_t epr; /* Entry Point Revision */
uint8_t fa[5]; /* value determined by EPR */
uint8_t sasig[5]; /* Secondary Anchor "_DMI_" */
uint8_t sachecksum; /* Secondary Checksum */
uint16_t size; /* Length of structure table in bytes */
uint32_t addr; /* Structure table address */
uint16_t count; /* Number of SMBIOS structures */
uint8_t rev; /* BCD revision */
} __packed;
struct smb3hdr {
uint8_t sig[5]; /* "_SM3_" */
uint8_t checksum; /* Entry point structure checksum */
uint8_t len; /* Entry point length */
uint8_t majrev; /* SMBIOS major version */
uint8_t minrev; /* SMBIOS minor version */
uint8_t docrev; /* SMBIOS docrev */
uint8_t epr; /* Entry point revision */
uint8_t reserved; /* Reserved */
uint32_t size; /* Structure table maximum size */
uint64_t addr; /* Structure table address */
} __packed;
struct smbtblhdr {
uint8_t type;
uint8_t size;
uint16_t handle;
} __packed;
struct smbtable {
struct smbtblhdr *hdr;
void *tblhdr;
uint32_t cookie;
};
#define SMBIOS_TYPE_BIOS 0
#define SMBIOS_TYPE_SYSTEM 1
#define SMBIOS_TYPE_BASEBOARD 2
#define SMBIOS_TYPE_ENCLOSURE 3
#define SMBIOS_TYPE_PROCESSOR 4
#define SMBIOS_TYPE_MEMCTRL 5
#define SMBIOS_TYPE_MEMMOD 6
#define SMBIOS_TYPE_CACHE 7
#define SMBIOS_TYPE_PORT 8
#define SMBIOS_TYPE_SLOTS 9
#define SMBIOS_TYPE_OBD 10
#define SMBIOS_TYPE_OEM 11
#define SMBIOS_TYPE_SYSCONFOPT 12
#define SMBIOS_TYPE_BIOSLANG 13
#define SMBIOS_TYPE_GROUPASSOC 14
#define SMBIOS_TYPE_SYSEVENTLOG 15
#define SMBIOS_TYPE_PHYMEM 16
#define SMBIOS_TYPE_MEMDEV 17
#define SMBIOS_TYPE_ECCINFO32 18
#define SMBIOS_TYPE_MEMMAPARRAYADDR 19
#define SMBIOS_TYPE_MEMMAPDEVADDR 20
#define SMBIOS_TYPE_INBUILTPOINT 21
#define SMBIOS_TYPE_PORTBATT 22
#define SMBIOS_TYPE_SYSRESET 23
#define SMBIOS_TYPE_HWSECUIRTY 24
#define SMBIOS_TYPE_PWRCTRL 25
#define SMBIOS_TYPE_VOLTPROBE 26
#define SMBIOS_TYPE_COOLING 27
#define SMBIOS_TYPE_TEMPPROBE 28
#define SMBIOS_TYPE_CURRENTPROBE 29
#define SMBIOS_TYPE_OOB_REMOTEACCESS 30
#define SMBIOS_TYPE_BIS 31
#define SMBIOS_TYPE_SBI 32
#define SMBIOS_TYPE_ECCINFO64 33
#define SMBIOS_TYPE_MGMTDEV 34
#define SMBIOS_TYPE_MGTDEVCOMP 35
#define SMBIOS_TYPE_MGTDEVTHRESH 36
#define SMBIOS_TYPE_MEMCHANNEL 37
#define SMBIOS_TYPE_IPMIDEV 38
#define SMBIOS_TYPE_SPS 39
#define SMBIOS_TYPE_INACTIVE 126
#define SMBIOS_TYPE_EOT 127
/*
* SMBIOS Structure Type 0 "BIOS Information"
* DMTF Specification DSP0134 Section: 3.3.1 p.g. 34
*/
struct smbios_struct_bios {
uint8_t vendor; /* string */
uint8_t version; /* string */
uint16_t startaddr;
uint8_t release; /* string */
uint8_t romsize;
uint64_t characteristics;
uint32_t charext;
uint8_t major_rel;
uint8_t minor_rel;
uint8_t ecf_mjr_rel; /* embedded controller firmware */
uint8_t ecf_min_rel; /* embedded controller firmware */
} __packed;
/*
* SMBIOS Structure Type 1 "System Information"
* DMTF Specification DSP0134 Section 3.3.2 p.g. 35
*/
struct smbios_sys {
/* SMBIOS spec 2.0+ */
uint8_t vendor; /* string */
uint8_t product; /* string */
uint8_t version; /* string */
uint8_t serial; /* string */
/* SMBIOS spec 2.1+ */
uint8_t uuid[16];
uint8_t wakeup;
/* SMBIOS spec 2.4+ */
uint8_t sku; /* string */
uint8_t family; /* string */
} __packed;
/*
* SMBIOS Structure Type 2 "Base Board (Module) Information"
* DMTF Specification DSP0134 Section 3.3.3 p.g. 37
*/
struct smbios_board {
uint8_t vendor; /* string */
uint8_t product; /* string */
uint8_t version; /* string */
uint8_t serial; /* string */
uint8_t asset; /* string */
uint8_t feature; /* feature flags */
uint8_t location; /* location in chassis */
uint16_t handle; /* chassis handle */
uint8_t type; /* board type */
uint8_t noc; /* number of contained objects */
} __packed;
/*
* SMBIOS Structure Type 3 "System Enclosure or Chassis"
* DMTF Specification DSP0134
*/
struct smbios_enclosure {
/* SMBIOS spec 2.0+ */
uint8_t vendor; /* string */
uint8_t type;
uint8_t version; /* string */
uint8_t serial; /* string */
uint8_t asset_tag; /* string */
/* SMBIOS spec 2.1+ */
uint8_t boot_state;
uint8_t psu_state;
uint8_t thermal_state;
uint8_t security_status;
/* SMBIOS spec 2.3+ */
uint16_t oem_defined;
uint8_t height;
uint8_t no_power_cords;
uint8_t no_contained_element;
uint8_t reclen_contained_element;
uint8_t contained_elements;
/* SMBIOS spec 2.7+ */
uint8_t sku; /* string */
} __packed;
/*
* SMBIOS Structure Type 4 "processor Information"
* DMTF Specification DSP0134 v2.5 Section 3.3.5 p.g. 24
*/
struct smbios_cpu {
uint8_t cpu_socket_designation; /* string */
uint8_t cpu_type;
uint8_t cpu_family;
uint8_t cpu_mfg; /* string */
uint32_t cpu_id_eax;
uint32_t cpu_id_edx;
uint8_t cpu_version; /* string */
uint8_t cpu_voltage;
uint16_t cpu_clock;
uint16_t cpu_max_speed;
uint16_t cpu_current_speed;
uint8_t cpu_status;
#define SMBIOS_CPUST_POPULATED (1<<6)
#define SMBIOS_CPUST_STATUSMASK (0x07)
uint8_t cpu_upgrade;
uint16_t cpu_l1_handle;
uint16_t cpu_l2_handle;
uint16_t cpu_l3_handle;
uint8_t cpu_serial; /* string */
uint8_t cpu_asset_tag; /* string */
uint8_t cpu_part_nr; /* string */
/* following fields were added in smbios 2.5 */
uint8_t cpu_core_count;
uint8_t cpu_core_enabled;
uint8_t cpu_thread_count;
uint16_t cpu_characteristics;
} __packed;
/*
* SMBIOS Structure Type 38 "IPMI Information"
* DMTF Specification DSP0134 Section 3.3.39 p.g. 91
*/
struct smbios_ipmi {
uint8_t smipmi_if_type; /* IPMI Interface Type */
uint8_t smipmi_if_rev; /* BCD IPMI Revision */
uint8_t smipmi_i2c_address; /* I2C address of BMC */
uint8_t smipmi_nvram_address; /* I2C address of NVRAM
* storage */
uint64_t smipmi_base_address; /* Base address of BMC (BAR
* format */
uint8_t smipmi_base_flags; /* Flags field:
* bit 7:6 : register spacing
* 00 = byte
* 01 = dword
* 02 = word
* bit 4 : Lower bit BAR
* bit 3 : IRQ valid
* bit 2 : N/A
* bit 1 : Interrupt polarity
* bit 0 : Interrupt trigger */
uint8_t smipmi_irq; /* IRQ if applicable */
} __packed;
int smbios_find_table(uint8_t, struct smbtable *);
char *smbios_get_string(struct smbtable *, uint8_t, char *, size_t);
#endif

25
lib/libc/include/aarch64-openbsd-none/arm64/spinlock.h vendored Normal file
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/* $OpenBSD: spinlock.h,v 1.2 2017/09/05 02:40:54 guenther Exp $ */
/*
* Copyright (c) 2014 Patrick Wildt <patrick@blueri.se>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_SPINLOCK_H_
#define _MACHINE_SPINLOCK_H_
#define _ATOMIC_LOCK_UNLOCKED (0)
#define _ATOMIC_LOCK_LOCKED (1)
typedef int _atomic_lock_t;
#endif

21
lib/libc/include/aarch64-openbsd-none/arm64/sysarch.h vendored Normal file
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/* $OpenBSD: sysarch.h,v 1.1 2016/12/17 23:38:33 patrick Exp $ */
/*
* Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_SYSARCH_H_
// aarch64 architecture has no libarch or arch specific syscalls.
#endif /* !_MACHINE_SYSARCH_H_ */

58
lib/libc/include/aarch64-openbsd-none/arm64/tcb.h vendored Normal file
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/* $OpenBSD: tcb.h,v 1.2 2017/01/10 13:13:12 patrick Exp $ */
/*
* Copyright (c) 2011 Philip Guenther <guenther@openbsd.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_TCB_H_
#define _MACHINE_TCB_H_
#ifdef _KERNEL
#include <machine/pcb.h>
static inline void
__aarch64_set_tcb(void *tcb)
{
__asm volatile("msr tpidr_el0, %x0" : : "r" (tcb));
}
#define TCB_GET(p) \
((struct pcb *)(p)->p_addr)->pcb_tcb
#define TCB_SET(p, addr) \
do { \
((struct pcb *)(p)->p_addr)->pcb_tcb = (addr); \
__aarch64_set_tcb(addr); \
} while (0)
#else /* _KERNEL */
/* ELF TLS ABI calls for small TCB, with static TLS data after it */
#define TLS_VARIANT 1
static inline void *
__aarch64_read_tcb(void)
{
void *tcb;
__asm volatile("mrs %x0, tpidr_el0": "=r" (tcb));
return tcb;
}
#define TCB_GET() __aarch64_read_tcb()
#endif /* _KERNEL */
#endif /* _MACHINE_TCB_H_ */

24
lib/libc/include/aarch64-openbsd-none/arm64/timetc.h vendored Normal file
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/* $OpenBSD: timetc.h,v 1.3 2023/01/09 15:22:53 kettenis Exp $ */
/*
* Copyright (c) 2020 Paul Irofti <paul@irofti.net>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_TIMETC_H_
#define _MACHINE_TIMETC_H_
#define TC_AGTIMER 1
#define TC_AGTIMER_SUN50I 2
#endif /* _MACHINE_TIMETC_H_ */

93
lib/libc/include/aarch64-openbsd-none/arm64/vmmvar.h vendored Normal file
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/* $OpenBSD: vmmvar.h,v 1.3 2025/08/03 10:17:33 tb Exp $ */
/*
* Copyright (c) 2014 Mike Larkin <mlarkin@openbsd.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*
* CPU capabilities for VMM operation
*/
#ifndef _MACHINE_VMMVAR_H_
#define _MACHINE_VMMVAR_H_
#define VMM_HV_SIGNATURE "OpenBSDVMM58"
/* Exit Reasons */
#define VM_EXIT_TERMINATED 0xFFFE
#define VM_EXIT_NONE 0xFFFF
struct vmm_softc_md {
/* Capabilities */
uint32_t nr_cpus; /* [I] */
};
/*
* struct vcpu_inject_event : describes an exception or interrupt to inject.
*/
struct vcpu_inject_event {
uint8_t vie_vector; /* Exception or interrupt vector. */
uint32_t vie_errorcode; /* Optional error code. */
uint8_t vie_type;
#define VCPU_INJECT_NONE 0
#define VCPU_INJECT_INTR 1 /* External hardware interrupt. */
#define VCPU_INJECT_EX 2 /* HW or SW Exception */
#define VCPU_INJECT_NMI 3 /* Non-maskable Interrupt */
};
#define VCPU_REGS_NGPRS 31
struct vcpu_reg_state {
uint64_t vrs_gprs[VCPU_REGS_NGPRS];
};
/*
* struct vm_exit
*
* Contains VM exit information communicated to vmd(8). This information is
* gathered by vmm(4) from the CPU on each exit that requires help from vmd.
*/
struct vm_exit {
struct vcpu_reg_state vrs;
};
struct vm_intr_params {
/* Input parameters to VMM_IOC_INTR */
uint32_t vip_vm_id;
uint32_t vip_vcpu_id;
uint16_t vip_intr;
};
#define VM_RWREGS_GPRS 0x1 /* read/write GPRs */
#define VM_RWREGS_ALL (VM_RWREGS_GPRS)
struct vm_rwregs_params {
/*
* Input/output parameters to VMM_IOC_READREGS /
* VMM_IOC_WRITEREGS
*/
uint32_t vrwp_vm_id;
uint32_t vrwp_vcpu_id;
uint64_t vrwp_mask;
struct vcpu_reg_state vrwp_regs;
};
enum {
VEI_DIR_OUT,
VEI_DIR_IN
};
/* IOCTL definitions */
#define VMM_IOC_INTR _IOW('V', 6, struct vm_intr_params) /* Intr pending */
#endif /* ! _MACHINE_VMMVAR_H_ */

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/* $OpenBSD: vmparam.h,v 1.9 2023/04/28 18:33:22 robert Exp $ */
/* $NetBSD: vmparam.h,v 1.1 2003/04/26 18:39:49 fvdl Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* William Jolitz.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)vmparam.h 5.9 (Berkeley) 5/12/91
*/
#ifndef _MACHINE_VMPARAM_H_
#define _MACHINE_VMPARAM_H_
/*
* Machine dependent constants for arm64.
*/
#define USRSTACK VM_MAXUSER_ADDRESS
/*
* Virtual memory related constants, all in bytes
*/
#define MAXTSIZ ((paddr_t)256*1024*1024) /* max text size */
#ifndef DFLDSIZ
#define DFLDSIZ ((paddr_t)512*1024*1024) /* initial data size limit */
#endif
#ifndef MAXDSIZ
#define MAXDSIZ ((paddr_t)64*1024*1024*1024) /* max data size */
#endif
#ifndef BRKSIZ
#define BRKSIZ ((paddr_t)16*1024*1024*1024) /* heap gap size */
#endif
#ifndef DFLSSIZ
#define DFLSSIZ ((paddr_t)2*1024*1024) /* initial stack size limit */
#endif
#ifndef MAXSSIZ
#define MAXSSIZ ((paddr_t)32*1024*1024) /* max stack size */
#endif
#define STACKGAP_RANDOM 256*1024
/*
* Size of shared memory map
*/
#ifndef SHMMAXPGS
#define SHMMAXPGS 1024
#endif
/*
* Size of User Raw I/O map
*/
#define USRIOSIZE 300
/*
* Kernel base
*/
#define KERNEL_BASE 0xffffff8000000000ULL
/*
* Mach derived constants
*/
/* user/kernel map constants */
#define VM_MIN_ADDRESS ((vaddr_t)PAGE_SIZE)
#define USER_SPACE_BITS 39
#define VM_MAXUSER_ADDRESS ((1ULL << USER_SPACE_BITS) - 0x8000)
#define VM_MAX_ADDRESS VM_MAXUSER_ADDRESS
#ifdef _KERNEL
#define VM_MIN_STACK_ADDRESS (3ULL << (USER_SPACE_BITS - 2))
#endif
#define VM_MIN_KERNEL_ADDRESS ((vaddr_t)0xffffff8000000000ULL)
#define VM_MAX_KERNEL_ADDRESS ((vaddr_t)0xffffff83ffffffffULL)
/* virtual sizes (bytes) for various kernel submaps */
#define VM_PHYS_SIZE (USRIOSIZE*PAGE_SIZE)
#define VM_PHYSSEG_MAX 32
#define VM_PHYSSEG_STRAT VM_PSTRAT_BSEARCH
#define VM_PHYSSEG_NOADD /* can't add RAM after vm_mem_init */
#endif /* _MACHINE_VMPARAM_H_ */

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/* $OpenBSD: frame.h,v 1.3 2018/06/30 15:23:37 deraadt Exp $ */
/*
* Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_FRAME_H_
#define _MACHINE_FRAME_H_
#ifndef _LOCORE
#include <sys/signal.h>
/*
* Exception/Trap Stack Frame
*/
#define clockframe trapframe
typedef struct trapframe {
register_t tf_sp;
register_t tf_lr;
register_t tf_elr;
register_t tf_spsr;
register_t tf_x[30];
} trapframe_t;
/*
* pushed on stack for signal delivery
*/
struct sigframe {
int sf_signum;
struct sigcontext sf_sc;
siginfo_t sf_si;
};
/*
* System stack frames.
*/
/*
* Stack frame inside cpu_switch()
*/
struct switchframe {
register_t sf_x19;
register_t sf_x20;
register_t sf_x21;
register_t sf_x22;
register_t sf_x23;
register_t sf_x24;
register_t sf_x25;
register_t sf_x26;
register_t sf_x27;
register_t sf_x28;
register_t sf_x29;
register_t sf_lr;
};
struct callframe {
struct callframe *f_frame;
register_t f_lr;
};
#endif /* !_LOCORE */
#endif /* _MACHINE_FRAME_H_ */

96
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/* $OpenBSD: _float.h,v 1.1 2016/12/17 23:38:33 patrick Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE__FLOAT_H_
#define _MACHINE__FLOAT_H_
#define __FLT_RADIX 2 /* b */
#define __FLT_ROUNDS __flt_rounds()
#define __FLT_EVAL_METHOD 0 /* no promotions */
#define __FLT_MANT_DIG 24 /* p */
#define __FLT_EPSILON 1.19209290E-7F /* b**(1-p) */
#define __FLT_DIG 6 /* floor((p-1)*log10(b))+(b == 10) */
#define __FLT_MIN_EXP (-125) /* emin */
#define __FLT_MIN 1.17549435E-38F /* b**(emin-1) */
#define __FLT_MIN_10_EXP (-37) /* ceil(log10(b**(emin-1))) */
#define __FLT_MAX_EXP 128 /* emax */
#define __FLT_MAX 3.40282347E+38F /* (1-b**(-p))*b**emax */
#define __FLT_MAX_10_EXP 38 /* floor(log10((1-b**(-p))*b**emax)) */
#define __DBL_MANT_DIG 53
#define __DBL_EPSILON 2.2204460492503131E-16
#define __DBL_DIG 15
#define __DBL_MIN_EXP (-1021)
#define __DBL_MIN 2.2250738585072014E-308
#define __DBL_MIN_10_EXP (-307)
#define __DBL_MAX_EXP 1024
#define __DBL_MAX 1.7976931348623157E+308
#define __DBL_MAX_10_EXP 308
#ifdef __LDBL_MANT_DIG__
#define __LDBL_MANT_DIG __LDBL_MANT_DIG__
#define __LDBL_EPSILON __LDBL_EPSILON__
#define __LDBL_DIG __LDBL_DIG__
#define __LDBL_MIN_EXP __LDBL_MIN_EXP__
#define __LDBL_MIN __LDBL_MIN__
#define __LDBL_MIN_10_EXP __LDBL_MIN_10_EXP__
#define __LDBL_MAX_EXP __LDBL_MAX_EXP__
#define __LDBL_MAX __LDBL_MAX__
#define __LDBL_MAX_10_EXP __LDBL_MAX_10_EXP__
#else
#define __LDBL_MANT_DIG DBL_MANT_DIG
#define __LDBL_EPSILON DBL_EPSILON
#define __LDBL_DIG DBL_DIG
#define __LDBL_MIN_EXP DBL_MIN_EXP
#define __LDBL_MIN DBL_MIN
#define __LDBL_MIN_10_EXP DBL_MIN_10_EXP
#define __LDBL_MAX_EXP DBL_MAX_EXP
#define __LDBL_MAX DBL_MAX
#define __LDBL_MAX_10_EXP DBL_MAX_10_EXP
#endif
#define __DECIMAL_DIG 17
#endif /* _MACHINE__FLOAT_H_ */

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/* $OpenBSD: _types.h,v 1.6 2023/07/02 19:02:27 cheloha Exp $ */
/*-
* Copyright (c) 1990, 1993
* The Regents of the University of California. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)types.h 8.3 (Berkeley) 1/5/94
* @(#)ansi.h 8.2 (Berkeley) 1/4/94
*/
#ifndef _MACHINE__TYPES_H_
#define _MACHINE__TYPES_H_
#if defined(_KERNEL)
typedef struct label_t {
long val[13];
} label_t;
#endif
/*
* _ALIGN(p) rounds p (pointer or byte index) up to a correctly-aligned
* value for all data types (int, long, ...). The result is an
* unsigned long and must be cast to any desired pointer type.
*
* _ALIGNED_POINTER is a boolean macro that checks whether an address
* is valid to fetch data elements of type t from on this architecture.
* This does not reflect the optimal alignment, just the possibility
* (within reasonable limits).
*/
#define _ALIGNBYTES (sizeof(long) - 1)
#define _STACKALIGNBYTES 15
#define _ALIGN(p) (((unsigned long)(p) + _ALIGNBYTES) & ~_ALIGNBYTES)
#define _ALIGNED_POINTER(p,t) ((((unsigned long)(p)) & (sizeof(t) - 1)) == 0)
#define _MAX_PAGE_SHIFT 12 /* same as PAGE_SHIFT */
/* 7.18.1.1 Exact-width integer types */
typedef signed char __int8_t;
typedef unsigned char __uint8_t;
typedef short __int16_t;
typedef unsigned short __uint16_t;
typedef int __int32_t;
typedef unsigned int __uint32_t;
/* LONGLONG */
typedef long long __int64_t;
/* LONGLONG */
typedef unsigned long long __uint64_t;
/* 7.18.1.2 Minimum-width integer types */
typedef __int8_t __int_least8_t;
typedef __uint8_t __uint_least8_t;
typedef __int16_t __int_least16_t;
typedef __uint16_t __uint_least16_t;
typedef __int32_t __int_least32_t;
typedef __uint32_t __uint_least32_t;
typedef __int64_t __int_least64_t;
typedef __uint64_t __uint_least64_t;
/* 7.18.1.3 Fastest minimum-width integer types */
typedef __int32_t __int_fast8_t;
typedef __uint32_t __uint_fast8_t;
typedef __int32_t __int_fast16_t;
typedef __uint32_t __uint_fast16_t;
typedef __int32_t __int_fast32_t;
typedef __uint32_t __uint_fast32_t;
typedef __int64_t __int_fast64_t;
typedef __uint64_t __uint_fast64_t;
#define __INT_FAST8_MIN INT32_MIN
#define __INT_FAST16_MIN INT32_MIN
#define __INT_FAST32_MIN INT32_MIN
#define __INT_FAST64_MIN INT64_MIN
#define __INT_FAST8_MAX INT32_MAX
#define __INT_FAST16_MAX INT32_MAX
#define __INT_FAST32_MAX INT32_MAX
#define __INT_FAST64_MAX INT64_MAX
#define __UINT_FAST8_MAX UINT32_MAX
#define __UINT_FAST16_MAX UINT32_MAX
#define __UINT_FAST32_MAX UINT32_MAX
#define __UINT_FAST64_MAX UINT64_MAX
/* 7.18.1.4 Integer types capable of holding object pointers */
typedef long __intptr_t;
typedef unsigned long __uintptr_t;
/* 7.18.1.5 Greatest-width integer types */
typedef __int64_t __intmax_t;
typedef __uint64_t __uintmax_t;
/* Register size */
typedef long __register_t;
/* VM system types */
typedef unsigned long __vaddr_t;
typedef unsigned long __paddr_t;
typedef unsigned long __vsize_t;
typedef unsigned long __psize_t;
/* Standard system types */
typedef double __double_t;
typedef float __float_t;
typedef long __ptrdiff_t;
typedef unsigned long __size_t;
typedef long __ssize_t;
#if defined(__GNUC__) && __GNUC__ >= 3
typedef __builtin_va_list __va_list;
#else
typedef char * __va_list;
#endif
/* Wide character support types */
#ifndef __cplusplus
#ifdef __WCHAR_UNSIGNED__
typedef unsigned int __wchar_t;
#else
typedef int __wchar_t;
#endif
#endif
typedef int __wint_t;
typedef int __rune_t;
typedef void * __wctrans_t;
typedef void * __wctype_t;
#endif /* _MACHINE__TYPES_H_ */

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/* $OpenBSD: acpiapm.h,v 1.1 2019/01/23 09:57:36 phessler Exp $ */
/*
* Copyright (c) 2007 Ted Unangst <tedu@openbsd.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
extern int (*acpiapm_open)(dev_t, int, int, struct proc *);
extern int (*acpiapm_close)(dev_t, int, int, struct proc *);
extern int (*acpiapm_ioctl)(dev_t, u_long, caddr_t, int, struct proc *);
extern int (*acpiapm_kqfilter)(dev_t, struct knote *);

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/* $OpenBSD: apmvar.h,v 1.3 2023/01/22 13:14:21 kettenis Exp $ */
/*
* Copyright (c) 2001 Alexander Guy
* Copyright (c) 1995 John T. Kohl
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR `AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _MACHINE_APMVAR_H_
#define _MACHINE_APMVAR_H_
#include <sys/ioccom.h>
/* Advanced Power Management (v1.0 and v1.1 specification)
* functions/defines/etc.
*/
/* These definitions make up the heart of the user-land interface
* to the APM devices.
*/
#define APM_AC_OFF 0x00
#define APM_AC_ON 0x01
#define APM_AC_BACKUP 0x02
#define APM_AC_UNKNOWN 0xff
#define APM_BATT_HIGH 0x00
#define APM_BATT_LOW 0x01
#define APM_BATT_CRITICAL 0x02
#define APM_BATT_CHARGING 0x03
#define APM_BATT_UNKNOWN 0xff
#define APM_BATT_LIFE_UNKNOWN 0xff
#define APM_NOEVENT 0x0000
#define APM_STANDBY_REQ 0x0001
#define APM_SUSPEND_REQ 0x0002
#define APM_NORMAL_RESUME 0x0003
#define APM_CRIT_RESUME 0x0004 /* suspend/resume happened
without us */
#define APM_BATTERY_LOW 0x0005
#define APM_POWER_CHANGE 0x0006
#define APM_UPDATE_TIME 0x0007
#define APM_CRIT_SUSPEND_REQ 0x0008
#define APM_USER_STANDBY_REQ 0x0009
#define APM_USER_SUSPEND_REQ 0x000A
#define APM_SYS_STANDBY_RESUME 0x000B
#define APM_CAPABILITY_CHANGE 0x000C /* apm v1.2 */
#define APM_USER_HIBERNATE_REQ 0x000D
#define APM_EVENT_MASK 0xffff
#define APM_EVENT_COMPOSE(t,i) ((((i) & 0x7fff) << 16)|((t) & APM_EVENT_MASK))
#define APM_EVENT_TYPE(e) ((e) & APM_EVENT_MASK)
#define APM_EVENT_INDEX(e) ((e) >> 16)
/*
* LP (Laptop Package)
*
* Copyright (C) 1994 by HOSOKAWA Tatsumi <hosokawa@mt.cs.keio.ac.jp>
*
* This software may be used, modified, copied, and distributed, in
* both source and binary form provided that the above copyright and
* these terms are retained. Under no circumstances is the author
* responsible for the proper functioning of this software, nor does
* the author assume any responsibility for damages incurred with its
* use.
*
* Sep., 1994 Implemented on FreeBSD 1.1.5.1R (Toshiba AVS001WD)
*/
#define APM_BATTERY_ABSENT 4
struct apm_power_info {
u_char battery_state;
u_char ac_state;
u_char battery_life;
u_char spare1;
u_int minutes_left; /* estimate */
u_int spare2[6];
};
struct apm_ctl {
u_int dev;
u_int mode;
};
#define APM_IOC_REJECT _IOW('A', 0, struct apm_event_info) /* reject request # */
#define APM_IOC_STANDBY _IO('A', 1) /* put system into standby */
#define APM_IOC_SUSPEND _IO('A', 2) /* put system into suspend */
#define APM_IOC_GETPOWER _IOR('A', 3, struct apm_power_info) /* fetch battery state */
#define APM_IOC_DEV_CTL _IOW('A', 5, struct apm_ctl) /* put device into mode */
#define APM_IOC_PRN_CTL _IOW('A', 6, int ) /* driver power status msg */
#define APM_PRINT_ON 0 /* driver power status displayed */
#define APM_PRINT_OFF 1 /* driver power status not displayed */
#define APM_PRINT_PCT 2 /* driver power status only displayed
if the percentage changes */
#define APM_IOC_STANDBY_REQ _IO('A', 7) /* request standby */
#define APM_IOC_SUSPEND_REQ _IO('A', 8) /* request suspend */
#define APM_IOC_HIBERNATE _IO('A', 9) /* put system into hibernate */
#ifdef _KERNEL
void apm_setinfohook(int (*)(struct apm_power_info *));
int apm_record_event(u_int);
#endif
#endif /* _MACHINE_APMVAR_H_ */

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lib/libc/include/aarch64-openbsd-none/machine/armreg.h vendored Normal file
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/* $OpenBSD: armreg.h,v 1.44 2025/07/22 09:20:41 kettenis Exp $ */
/*-
* Copyright (c) 2013, 2014 Andrew Turner
* Copyright (c) 2015 The FreeBSD Foundation
* All rights reserved.
*
* This software was developed by Andrew Turner under
* sponsorship from the FreeBSD Foundation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD: head/sys/arm64/include/armreg.h 309248 2016-11-28 14:24:07Z andrew $
*/
#ifndef _MACHINE_ARMREG_H_
#define _MACHINE_ARMREG_H_
#define INSN_SIZE 4
#define READ_SPECIALREG(reg) \
({ uint64_t val; \
__asm volatile("mrs %0, " __STRING(reg) : "=&r" (val)); \
val; \
})
#define WRITE_SPECIALREG(reg, val) \
__asm volatile("msr " __STRING(reg) ", %0" : : "r"((uint64_t)val))
/* CCSIDR_EL1 - Current Cache Size ID Register */
#define CCSIDR_SETS_MASK 0x0fffe000
#define CCSIDR_SETS_SHIFT 13
#define CCSIDR_SETS(reg) \
((((reg) & CCSIDR_SETS_MASK) >> CCSIDR_SETS_SHIFT) + 1)
#define CCSIDR_WAYS_MASK 0x00001ff8
#define CCSIDR_WAYS_SHIFT 3
#define CCSIDR_WAYS(reg) \
((((reg) & CCSIDR_WAYS_MASK) >> CCSIDR_WAYS_SHIFT) + 1)
#define CCSIDR_LINE_MASK 0x00000007
#define CCSIDR_LINE_SIZE(reg) (1 << (((reg) & CCSIDR_LINE_MASK) + 4))
#define CCSIDR_CCIDX_SETS_MASK 0x00ffffff00000000ULL
#define CCSIDR_CCIDX_SETS_SHIFT 32
#define CCSIDR_CCIDX_SETS(reg) \
((((reg) & CCSIDR_CCIDX_SETS_MASK) >> CCSIDR_CCIDX_SETS_SHIFT) + 1)
#define CCSIDR_CCIDX_WAYS_MASK 0x0000000000fffff8ULL
#define CCSIDR_CCIDX_WAYS_SHIFT 3
#define CCSIDR_CCIDX_WAYS(reg) \
((((reg) & CCSIDR_CCIDX_WAYS_MASK) >> CCSIDR_CCIDX_WAYS_SHIFT) + 1)
#define CCSIDR_CCIDX_LINE_MASK 0x0000000000000007ULL
#define CCSIDR_CCIDX_LINE_SIZE(reg) \
(1 << (((reg) & CCSIDR_CCIDX_LINE_MASK) + 4))
/* CLIDR_EL1 - Cache Level ID Register */
#define CLIDR_CTYPE_MASK 0x7
#define CLIDR_CTYPE_INSN 0x1
#define CLIDR_CTYPE_DATA 0x2
#define CLIDR_CTYPE_UNIFIED 0x4
/* CNTHCTL_EL2 - Counter-timer Hypervisor Control Register */
#define CNTHCTL_EVNTI_MASK (0xf << 4) /* Bit to trigger event stream */
#define CNTHCTL_EVNTDIR (1 << 3) /* Control transition trigger bit */
#define CNTHCTL_EVNTEN (1 << 2) /* Enable event stream */
#define CNTHCTL_EL1PCEN (1 << 1) /* Allow EL0/1 physical timer access */
#define CNTHCTL_EL1PCTEN (1 << 0) /*Allow EL0/1 physical counter access*/
/* CNTKCTL_EL1 - Counter-timer Kernel Control Register */
#define CNTKCTL_EL0VCTEN (1 << 1) /* Allow EL0 virtual counter access */
/* CNTV_CTL_EL0 */
#define CNTV_CTL_ENABLE (1 << 0)
#define CNTV_CTL_IMASK (1 << 1)
#define CNTV_CTL_ISTATUS (1 << 2)
/* CPACR_EL1 */
#define CPACR_ZEN_MASK (0x3 << 16)
#define CPACR_ZEN_TRAP_ALL1 (0x0 << 16) /* Traps from EL0 and EL1 */
#define CPACR_ZEN_TRAP_EL0 (0x1 << 16) /* Traps from EL0 */
#define CPACR_ZEN_TRAP_ALL2 (0x2 << 16) /* Traps from EL0 and EL1 */
#define CPACR_ZEN_TRAP_NONE (0x3 << 16) /* No traps */
#define CPACR_FPEN_MASK (0x3 << 20)
#define CPACR_FPEN_TRAP_ALL1 (0x0 << 20) /* Traps from EL0 and EL1 */
#define CPACR_FPEN_TRAP_EL0 (0x1 << 20) /* Traps from EL0 */
#define CPACR_FPEN_TRAP_ALL2 (0x2 << 20) /* Traps from EL0 and EL1 */
#define CPACR_FPEN_TRAP_NONE (0x3 << 20) /* No traps */
#define CPACR_TTA (0x1 << 28)
/* CSSELR_EL1 - Cache Size Selection Register */
#define CSSELR_IND (1 << 0)
#define CSSELR_LEVEL_SHIFT 1
/* CTR_EL0 - Cache Type Register */
#define CTR_DLINE_SHIFT 16
#define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT)
#define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT)
#define CTR_IL1P_SHIFT 14
#define CTR_IL1P_MASK (0x3 << CTR_IL1P_SHIFT)
#define CTR_IL1P_AIVIVT (0x1 << CTR_IL1P_SHIFT)
#define CTR_IL1P_VIPT (0x2 << CTR_IL1P_SHIFT)
#define CTR_IL1P_PIPT (0x3 << CTR_IL1P_SHIFT)
#define CTR_ILINE_SHIFT 0
#define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT)
#define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT)
/* MPIDR_EL1 - Multiprocessor Affinity Register */
#define MPIDR_AFF3 (0xFFULL << 32)
#define MPIDR_AFF2 (0xFFULL << 16)
#define MPIDR_AFF1 (0xFFULL << 8)
#define MPIDR_AFF0 (0xFFULL << 0)
#define MPIDR_AFF (MPIDR_AFF3|MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0)
/* DCZID_EL0 - Data Cache Zero ID register */
#define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */
#define DCZID_BS_SHIFT 0
#define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT)
#define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT)
/* ESR_ELx */
#define ESR_ELx_ISS_MASK 0x00ffffff
#define ISS_INSN_FnV (0x01 << 10)
#define ISS_INSN_EA (0x01 << 9)
#define ISS_INSN_S1PTW (0x01 << 7)
#define ISS_INSN_IFSC_MASK (0x1f << 0)
#define ISS_DATA_ISV (0x01 << 24)
#define ISS_DATA_SAS_MASK (0x03 << 22)
#define ISS_DATA_SSE (0x01 << 21)
#define ISS_DATA_SRT_MASK (0x1f << 16)
#define ISS_DATA_SF (0x01 << 15)
#define ISS_DATA_AR (0x01 << 14)
#define ISS_DATA_FnV (0x01 << 10)
#define ISS_DATA_EA (0x01 << 9)
#define ISS_DATA_CM (0x01 << 8)
#define ISS_DATA_S1PTW (0x01 << 7)
#define ISS_DATA_WnR (0x01 << 6)
#define ISS_DATA_DFSC_MASK (0x3f << 0)
#define ISS_DATA_DFSC_ASF_L0 (0x00 << 0)
#define ISS_DATA_DFSC_ASF_L1 (0x01 << 0)
#define ISS_DATA_DFSC_ASF_L2 (0x02 << 0)
#define ISS_DATA_DFSC_ASF_L3 (0x03 << 0)
#define ISS_DATA_DFSC_TF_L0 (0x04 << 0)
#define ISS_DATA_DFSC_TF_L1 (0x05 << 0)
#define ISS_DATA_DFSC_TF_L2 (0x06 << 0)
#define ISS_DATA_DFSC_TF_L3 (0x07 << 0)
#define ISS_DATA_DFSC_AFF_L1 (0x09 << 0)
#define ISS_DATA_DFSC_AFF_L2 (0x0a << 0)
#define ISS_DATA_DFSC_AFF_L3 (0x0b << 0)
#define ISS_DATA_DFSC_PF_L1 (0x0d << 0)
#define ISS_DATA_DFSC_PF_L2 (0x0e << 0)
#define ISS_DATA_DFSC_PF_L3 (0x0f << 0)
#define ISS_DATA_DFSC_EXT (0x10 << 0)
#define ISS_DATA_DFSC_EXT_L0 (0x14 << 0)
#define ISS_DATA_DFSC_EXT_L1 (0x15 << 0)
#define ISS_DATA_DFSC_EXT_L2 (0x16 << 0)
#define ISS_DATA_DFSC_EXT_L3 (0x17 << 0)
#define ISS_DATA_DFSC_ECC (0x18 << 0)
#define ISS_DATA_DFSC_ECC_L0 (0x1c << 0)
#define ISS_DATA_DFSC_ECC_L1 (0x1d << 0)
#define ISS_DATA_DFSC_ECC_L2 (0x1e << 0)
#define ISS_DATA_DFSC_ECC_L3 (0x1f << 0)
#define ISS_DATA_DFSC_ALIGN (0x21 << 0)
#define ISS_DATA_DFSC_TLB_CONFLICT (0x30 << 0)
#define ISS_MSR_DIR_SHIFT 0
#define ISS_MSR_DIR (0x01 << ISS_MSR_DIR_SHIFT)
#define ISS_MSR_Rt_SHIFT 5
#define ISS_MSR_Rt_MASK (0x1f << ISS_MSR_Rt_SHIFT)
#define ISS_MSR_Rt(x) (((x) & ISS_MSR_Rt_MASK) >> ISS_MSR_Rt_SHIFT)
#define ISS_MSR_CRm_SHIFT 1
#define ISS_MSR_CRm_MASK (0xf << ISS_MSR_CRm_SHIFT)
#define ISS_MSR_CRm(x) (((x) & ISS_MSR_CRm_MASK) >> ISS_MSR_CRm_SHIFT)
#define ISS_MSR_CRn_SHIFT 10
#define ISS_MSR_CRn_MASK (0xf << ISS_MSR_CRn_SHIFT)
#define ISS_MSR_CRn(x) (((x) & ISS_MSR_CRn_MASK) >> ISS_MSR_CRn_SHIFT)
#define ISS_MSR_OP1_SHIFT 14
#define ISS_MSR_OP1_MASK (0x7 << ISS_MSR_OP1_SHIFT)
#define ISS_MSR_OP1(x) (((x) & ISS_MSR_OP1_MASK) >> ISS_MSR_OP1_SHIFT)
#define ISS_MSR_OP2_SHIFT 17
#define ISS_MSR_OP2_MASK (0x7 << ISS_MSR_OP2_SHIFT)
#define ISS_MSR_OP2(x) (((x) & ISS_MSR_OP2_MASK) >> ISS_MSR_OP2_SHIFT)
#define ISS_MSR_OP0_SHIFT 20
#define ISS_MSR_OP0_MASK (0x3 << ISS_MSR_OP0_SHIFT)
#define ISS_MSR_OP0(x) (((x) & ISS_MSR_OP0_MASK) >> ISS_MSR_OP0_SHIFT)
#define ISS_BRK_COMMENT_MASK 0xffff
#define ESR_ELx_IL (0x01 << 25)
#define ESR_ELx_EC_SHIFT 26
#define ESR_ELx_EC_MASK (0x3f << 26)
#define ESR_ELx_EXCEPTION(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
#define EXCP_UNKNOWN 0x00 /* Unkwn exception */
#define EXCP_FP_SIMD 0x07 /* FP/SIMD trap */
#define EXCP_BRANCH_TGT 0x0d /* Branch target exception */
#define EXCP_ILL_STATE 0x0e /* Illegal execution state */
#define EXCP_SVC 0x15 /* SVC trap */
#define EXCP_MSR 0x18 /* MSR/MRS trap */
#define EXCP_SVE 0x19 /* SVE trap */
#define EXCP_FPAC 0x1c /* Faulting PAC trap */
#define EXCP_INSN_ABORT_L 0x20 /* Instruction abort, from lower EL */
#define EXCP_INSN_ABORT 0x21 /* Instruction abort, from same EL */
#define EXCP_PC_ALIGN 0x22 /* PC alignment fault */
#define EXCP_DATA_ABORT_L 0x24 /* Data abort, from lower EL */
#define EXCP_DATA_ABORT 0x25 /* Data abort, from same EL */
#define EXCP_SP_ALIGN 0x26 /* SP alignment fault */
#define EXCP_TRAP_FP 0x2c /* Trapped FP exception */
#define EXCP_SERROR 0x2f /* SError interrupt */
#define EXCP_SOFTSTP_EL0 0x32 /* Software Step, from lower EL */
#define EXCP_SOFTSTP_EL1 0x33 /* Software Step, from same EL */
#define EXCP_WATCHPT_EL1 0x35 /* Watchpoint, from same EL */
#define EXCP_BRK 0x3c /* Breakpoint */
/* ICC_CTLR_EL1 */
#define ICC_CTLR_EL1_EOIMODE (1U << 1)
#define ICC_CTLR_EL1_PRIBITS_SHIFT 8
#define ICC_CTLR_EL1_PRIBITS_MASK (0x7UL << 8)
#define ICC_CTLR_EL1_PRIBITS(reg) \
(((reg) & ICC_CTLR_EL1_PRIBITS_MASK) >> ICC_CTLR_EL1_PRIBITS_SHIFT)
/* ICC_IAR1_EL1 */
#define ICC_IAR1_EL1_SPUR (0x03ff)
/* ICC_IGRPEN0_EL1 */
#define ICC_IGRPEN0_EL1_EN (1U << 0)
/* ICC_PMR_EL1 */
#define ICC_PMR_EL1_PRIO_MASK (0xFFUL)
/* ICC_SGI1R_EL1 */
#define ICC_SGI1R_EL1_TL_MASK 0xffffUL
#define ICC_SGI1R_EL1_AFF1_SHIFT 16
#define ICC_SGI1R_EL1_SGIID_SHIFT 24
#define ICC_SGI1R_EL1_AFF2_SHIFT 32
#define ICC_SGI1R_EL1_AFF3_SHIFT 48
#define ICC_SGI1R_EL1_SGIID_MASK 0xfUL
#define ICC_SGI1R_EL1_IRM (0x1UL << 40)
/* ICC_SRE_EL1 */
#define ICC_SRE_EL1_SRE (1U << 0)
/* ICC_SRE_EL2 */
#define ICC_SRE_EL2_SRE (1U << 0)
#define ICC_SRE_EL2_EN (1U << 3)
/* ID_AA64DFR0_EL1 */
#define ID_AA64DFR0_MASK 0x00000000f0f0ffffUL
#define ID_AA64DFR0_DEBUG_VER_SHIFT 0
#define ID_AA64DFR0_DEBUG_VER_MASK (0xfULL << ID_AA64DFR0_DEBUG_VER_SHIFT)
#define ID_AA64DFR0_DEBUG_VER(x) ((x) & ID_AA64DFR0_DEBUG_VER_MASK)
#define ID_AA64DFR0_DEBUG_VER_8 (0x6ULL << ID_AA64DFR0_DEBUG_VER_SHIFT)
#define ID_AA64DFR0_DEBUG_VER_8_VHE (0x7ULL << ID_AA64DFR0_DEBUG_VER_SHIFT)
#define ID_AA64DFR0_TRACE_VER_SHIFT 4
#define ID_AA64DFR0_TRACE_VER_MASK (0xfULL << ID_AA64DFR0_TRACE_VER_SHIFT)
#define ID_AA64DFR0_TRACE_VER(x) ((x) & ID_AA64DFR0_TRACE_VER_MASK)
#define ID_AA64DFR0_TRACE_VER_NONE (0x0ULL << ID_AA64DFR0_TRACE_VER_SHIFT)
#define ID_AA64DFR0_TRACE_VER_IMPL (0x1ULL << ID_AA64DFR0_TRACE_VER_SHIFT)
#define ID_AA64DFR0_PMU_VER_SHIFT 8
#define ID_AA64DFR0_PMU_VER_MASK (0xfULL << ID_AA64DFR0_PMU_VER_SHIFT)
#define ID_AA64DFR0_PMU_VER(x) ((x) & ID_AA64DFR0_PMU_VER_MASK)
#define ID_AA64DFR0_PMU_VER_NONE (0x0ULL << ID_AA64DFR0_PMU_VER_SHIFT)
#define ID_AA64DFR0_PMU_VER_3 (0x1ULL << ID_AA64DFR0_PMU_VER_SHIFT)
#define ID_AA64DFR0_PMU_VER_3_1 (0x4ULL << ID_AA64DFR0_PMU_VER_SHIFT)
#define ID_AA64DFR0_PMU_VER_IMPL (0xfULL << ID_AA64DFR0_PMU_VER_SHIFT)
#define ID_AA64DFR0_BRPS_SHIFT 12
#define ID_AA64DFR0_BRPS_MASK (0xfULL << ID_AA64DFR0_BRPS_SHIFT)
#define ID_AA64DFR0_BRPS(x) \
((((x) >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) + 1)
#define ID_AA64DFR0_WRPS_SHIFT 20
#define ID_AA64DFR0_WRPS_MASK (0xfULL << ID_AA64DFR0_WRPS_SHIFT)
#define ID_AA64DFR0_WRPS(x) \
((((x) >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) + 1)
#define ID_AA64DFR0_CTX_CMPS_SHIFT 28
#define ID_AA64DFR0_CTX_CMPS_MASK (0xfULL << ID_AA64DFR0_CTX_CMPS_SHIFT)
#define ID_AA64DFR0_CTX_CMPS(x) \
((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1)
/* ID_AA64ISAR0_EL1 */
#define ID_AA64ISAR0_MASK 0xfffffffff0fffff0ULL
#define ID_AA64ISAR0_AES_SHIFT 4
#define ID_AA64ISAR0_AES_MASK (0xfULL << ID_AA64ISAR0_AES_SHIFT)
#define ID_AA64ISAR0_AES(x) ((x) & ID_AA64ISAR0_AES_MASK)
#define ID_AA64ISAR0_AES_NONE (0x0ULL << ID_AA64ISAR0_AES_SHIFT)
#define ID_AA64ISAR0_AES_BASE (0x1ULL << ID_AA64ISAR0_AES_SHIFT)
#define ID_AA64ISAR0_AES_PMULL (0x2ULL << ID_AA64ISAR0_AES_SHIFT)
#define ID_AA64ISAR0_SHA1_SHIFT 8
#define ID_AA64ISAR0_SHA1_MASK (0xfULL << ID_AA64ISAR0_SHA1_SHIFT)
#define ID_AA64ISAR0_SHA1(x) ((x) & ID_AA64ISAR0_SHA1_MASK)
#define ID_AA64ISAR0_SHA1_NONE (0x0ULL << ID_AA64ISAR0_SHA1_SHIFT)
#define ID_AA64ISAR0_SHA1_BASE (0x1ULL << ID_AA64ISAR0_SHA1_SHIFT)
#define ID_AA64ISAR0_SHA2_SHIFT 12
#define ID_AA64ISAR0_SHA2_MASK (0xfULL << ID_AA64ISAR0_SHA2_SHIFT)
#define ID_AA64ISAR0_SHA2(x) ((x) & ID_AA64ISAR0_SHA2_MASK)
#define ID_AA64ISAR0_SHA2_NONE (0x0ULL << ID_AA64ISAR0_SHA2_SHIFT)
#define ID_AA64ISAR0_SHA2_BASE (0x1ULL << ID_AA64ISAR0_SHA2_SHIFT)
#define ID_AA64ISAR0_SHA2_512 (0x2ULL << ID_AA64ISAR0_SHA2_SHIFT)
#define ID_AA64ISAR0_CRC32_SHIFT 16
#define ID_AA64ISAR0_CRC32_MASK (0xfULL << ID_AA64ISAR0_CRC32_SHIFT)
#define ID_AA64ISAR0_CRC32(x) ((x) & ID_AA64ISAR0_CRC32_MASK)
#define ID_AA64ISAR0_CRC32_NONE (0x0ULL << ID_AA64ISAR0_CRC32_SHIFT)
#define ID_AA64ISAR0_CRC32_BASE (0x1ULL << ID_AA64ISAR0_CRC32_SHIFT)
#define ID_AA64ISAR0_ATOMIC_SHIFT 20
#define ID_AA64ISAR0_ATOMIC_MASK (0xfULL << ID_AA64ISAR0_ATOMIC_SHIFT)
#define ID_AA64ISAR0_ATOMIC(x) ((x) & ID_AA64ISAR0_ATOMIC_MASK)
#define ID_AA64ISAR0_ATOMIC_NONE (0x0ULL << ID_AA64ISAR0_ATOMIC_SHIFT)
#define ID_AA64ISAR0_ATOMIC_IMPL (0x2ULL << ID_AA64ISAR0_ATOMIC_SHIFT)
#define ID_AA64ISAR0_RDM_SHIFT 28
#define ID_AA64ISAR0_RDM_MASK (0xfULL << ID_AA64ISAR0_RDM_SHIFT)
#define ID_AA64ISAR0_RDM(x) ((x) & ID_AA64ISAR0_RDM_MASK)
#define ID_AA64ISAR0_RDM_NONE (0x0ULL << ID_AA64ISAR0_RDM_SHIFT)
#define ID_AA64ISAR0_RDM_IMPL (0x1ULL << ID_AA64ISAR0_RDM_SHIFT)
#define ID_AA64ISAR0_SHA3_SHIFT 32
#define ID_AA64ISAR0_SHA3_MASK (0xfULL << ID_AA64ISAR0_SHA3_SHIFT)
#define ID_AA64ISAR0_SHA3(x) ((x) & ID_AA64ISAR0_SHA3_MASK)
#define ID_AA64ISAR0_SHA3_NONE (0x0ULL << ID_AA64ISAR0_SHA3_SHIFT)
#define ID_AA64ISAR0_SHA3_IMPL (0x1ULL << ID_AA64ISAR0_SHA3_SHIFT)
#define ID_AA64ISAR0_SM3_SHIFT 36
#define ID_AA64ISAR0_SM3_MASK (0xfULL << ID_AA64ISAR0_SM3_SHIFT)
#define ID_AA64ISAR0_SM3(x) ((x) & ID_AA64ISAR0_SM3_MASK)
#define ID_AA64ISAR0_SM3_NONE (0x0ULL << ID_AA64ISAR0_SM3_SHIFT)
#define ID_AA64ISAR0_SM3_IMPL (0x1ULL << ID_AA64ISAR0_SM3_SHIFT)
#define ID_AA64ISAR0_SM4_SHIFT 40
#define ID_AA64ISAR0_SM4_MASK (0xfULL << ID_AA64ISAR0_SM4_SHIFT)
#define ID_AA64ISAR0_SM4(x) ((x) & ID_AA64ISAR0_SM4_MASK)
#define ID_AA64ISAR0_SM4_NONE (0x0ULL << ID_AA64ISAR0_SM4_SHIFT)
#define ID_AA64ISAR0_SM4_IMPL (0x1ULL << ID_AA64ISAR0_SM4_SHIFT)
#define ID_AA64ISAR0_DP_SHIFT 44
#define ID_AA64ISAR0_DP_MASK (0xfULL << ID_AA64ISAR0_DP_SHIFT)
#define ID_AA64ISAR0_DP(x) ((x) & ID_AA64ISAR0_DP_MASK)
#define ID_AA64ISAR0_DP_NONE (0x0ULL << ID_AA64ISAR0_DP_SHIFT)
#define ID_AA64ISAR0_DP_IMPL (0x1ULL << ID_AA64ISAR0_DP_SHIFT)
#define ID_AA64ISAR0_FHM_SHIFT 48
#define ID_AA64ISAR0_FHM_MASK (0xfULL << ID_AA64ISAR0_FHM_SHIFT)
#define ID_AA64ISAR0_FHM(x) ((x) & ID_AA64ISAR0_FHM_MASK)
#define ID_AA64ISAR0_FHM_NONE (0x0ULL << ID_AA64ISAR0_FHM_SHIFT)
#define ID_AA64ISAR0_FHM_IMPL (0x1ULL << ID_AA64ISAR0_FHM_SHIFT)
#define ID_AA64ISAR0_TS_SHIFT 52
#define ID_AA64ISAR0_TS_MASK (0xfULL << ID_AA64ISAR0_TS_SHIFT)
#define ID_AA64ISAR0_TS(x) ((x) & ID_AA64ISAR0_TS_MASK)
#define ID_AA64ISAR0_TS_NONE (0x0ULL << ID_AA64ISAR0_TS_SHIFT)
#define ID_AA64ISAR0_TS_BASE (0x1ULL << ID_AA64ISAR0_TS_SHIFT)
#define ID_AA64ISAR0_TS_AXFLAG (0x2ULL << ID_AA64ISAR0_TS_SHIFT)
#define ID_AA64ISAR0_TLB_SHIFT 56
#define ID_AA64ISAR0_TLB_MASK (0xfULL << ID_AA64ISAR0_TLB_SHIFT)
#define ID_AA64ISAR0_TLB(x) ((x) & ID_AA64ISAR0_TLB_MASK)
#define ID_AA64ISAR0_TLB_NONE (0x0ULL << ID_AA64ISAR0_TLB_SHIFT)
#define ID_AA64ISAR0_TLB_IOS (0x1ULL << ID_AA64ISAR0_TLB_SHIFT)
#define ID_AA64ISAR0_TLB_IRANGE (0x2ULL << ID_AA64ISAR0_TLB_SHIFT)
#define ID_AA64ISAR0_RNDR_SHIFT 60
#define ID_AA64ISAR0_RNDR_MASK (0xfULL << ID_AA64ISAR0_RNDR_SHIFT)
#define ID_AA64ISAR0_RNDR(x) ((x) & ID_AA64ISAR0_RNDR_MASK)
#define ID_AA64ISAR0_RNDR_NONE (0x0ULL << ID_AA64ISAR0_RNDR_SHIFT)
#define ID_AA64ISAR0_RNDR_IMPL (0x1ULL << ID_AA64ISAR0_RNDR_SHIFT)
/* ID_AA64ISAR1_EL1 */
#define ID_AA64ISAR1_MASK 0xffffffffffffffffULL
#define ID_AA64ISAR1_DPB_SHIFT 0
#define ID_AA64ISAR1_DPB_MASK (0xfULL << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_DPB(x) ((x) & ID_AA64ISAR1_DPB_MASK)
#define ID_AA64ISAR1_DPB_NONE (0x0ULL << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_DPB_IMPL (0x1ULL << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_DPB_DCCVADP (0x2ULL << ID_AA64ISAR1_DPB_SHIFT)
#define ID_AA64ISAR1_APA_SHIFT 4
#define ID_AA64ISAR1_APA_MASK (0xfULL << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_APA(x) ((x) & ID_AA64ISAR1_APA_MASK)
#define ID_AA64ISAR1_APA_NONE (0x0ULL << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_APA_PAC (0x1ULL << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_APA_EPAC (0x2ULL << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_APA_EPAC2 (0x3ULL << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_APA_FPAC (0x4ULL << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_APA_FPAC_COMBINED (0x5ULL << ID_AA64ISAR1_APA_SHIFT)
#define ID_AA64ISAR1_API_SHIFT 8
#define ID_AA64ISAR1_API_MASK (0xfULL << ID_AA64ISAR1_API_SHIFT)
#define ID_AA64ISAR1_API(x) ((x) & ID_AA64ISAR1_API_MASK)
#define ID_AA64ISAR1_API_NONE (0x0ULL << ID_AA64ISAR1_API_SHIFT)
#define ID_AA64ISAR1_API_PAC (0x1ULL << ID_AA64ISAR1_API_SHIFT)
#define ID_AA64ISAR1_API_EPAC (0x2ULL << ID_AA64ISAR1_API_SHIFT)
#define ID_AA64ISAR1_API_EPAC2 (0x3ULL << ID_AA64ISAR1_API_SHIFT)
#define ID_AA64ISAR1_API_FPAC (0x4ULL << ID_AA64ISAR1_API_SHIFT)
#define ID_AA64ISAR1_API_FPAC_COMBINED (0x5ULL << ID_AA64ISAR1_API_SHIFT)
#define ID_AA64ISAR1_JSCVT_SHIFT 12
#define ID_AA64ISAR1_JSCVT_MASK (0xfULL << ID_AA64ISAR1_JSCVT_SHIFT)
#define ID_AA64ISAR1_JSCVT(x) ((x) & ID_AA64ISAR1_JSCVT_MASK)
#define ID_AA64ISAR1_JSCVT_NONE (0x0ULL << ID_AA64ISAR1_JSCVT_SHIFT)
#define ID_AA64ISAR1_JSCVT_IMPL (0x1ULL << ID_AA64ISAR1_JSCVT_SHIFT)
#define ID_AA64ISAR1_FCMA_SHIFT 16
#define ID_AA64ISAR1_FCMA_MASK (0xfULL << ID_AA64ISAR1_FCMA_SHIFT)
#define ID_AA64ISAR1_FCMA(x) ((x) & ID_AA64ISAR1_FCMA_MASK)
#define ID_AA64ISAR1_FCMA_NONE (0x0ULL << ID_AA64ISAR1_FCMA_SHIFT)
#define ID_AA64ISAR1_FCMA_IMPL (0x1ULL << ID_AA64ISAR1_FCMA_SHIFT)
#define ID_AA64ISAR1_LRCPC_SHIFT 20
#define ID_AA64ISAR1_LRCPC_MASK (0xfULL << ID_AA64ISAR1_LRCPC_SHIFT)
#define ID_AA64ISAR1_LRCPC(x) ((x) & ID_AA64ISAR1_LRCPC_MASK)
#define ID_AA64ISAR1_LRCPC_NONE (0x0ULL << ID_AA64ISAR1_LRCPC_SHIFT)
#define ID_AA64ISAR1_LRCPC_BASE (0x1ULL << ID_AA64ISAR1_LRCPC_SHIFT)
#define ID_AA64ISAR1_LRCPC_LDAPUR (0x2ULL << ID_AA64ISAR1_LRCPC_SHIFT)
#define ID_AA64ISAR1_GPA_SHIFT 24
#define ID_AA64ISAR1_GPA_MASK (0xfULL << ID_AA64ISAR1_GPA_SHIFT)
#define ID_AA64ISAR1_GPA(x) ((x) & ID_AA64ISAR1_GPA_MASK)
#define ID_AA64ISAR1_GPA_NONE (0x0ULL << ID_AA64ISAR1_GPA_SHIFT)
#define ID_AA64ISAR1_GPA_IMPL (0x1ULL << ID_AA64ISAR1_GPA_SHIFT)
#define ID_AA64ISAR1_GPI_SHIFT 28
#define ID_AA64ISAR1_GPI_MASK (0xfULL << ID_AA64ISAR1_GPI_SHIFT)
#define ID_AA64ISAR1_GPI(x) ((x) & ID_AA64ISAR1_GPI_MASK)
#define ID_AA64ISAR1_GPI_NONE (0x0ULL << ID_AA64ISAR1_GPI_SHIFT)
#define ID_AA64ISAR1_GPI_IMPL (0x1ULL << ID_AA64ISAR1_GPI_SHIFT)
#define ID_AA64ISAR1_FRINTTS_SHIFT 32
#define ID_AA64ISAR1_FRINTTS_MASK (0xfULL << ID_AA64ISAR1_FRINTTS_SHIFT)
#define ID_AA64ISAR1_FRINTTS(x) ((x) & ID_AA64ISAR1_FRINTTS_MASK)
#define ID_AA64ISAR1_FRINTTS_NONE (0x0ULL << ID_AA64ISAR1_FRINTTS_SHIFT)
#define ID_AA64ISAR1_FRINTTS_IMPL (0x1ULL << ID_AA64ISAR1_FRINTTS_SHIFT)
#define ID_AA64ISAR1_SB_SHIFT 36
#define ID_AA64ISAR1_SB_MASK (0xfULL << ID_AA64ISAR1_SB_SHIFT)
#define ID_AA64ISAR1_SB(x) ((x) & ID_AA64ISAR1_SB_MASK)
#define ID_AA64ISAR1_SB_NONE (0x0ULL << ID_AA64ISAR1_SB_SHIFT)
#define ID_AA64ISAR1_SB_IMPL (0x1ULL << ID_AA64ISAR1_SB_SHIFT)
#define ID_AA64ISAR1_SPECRES_SHIFT 40
#define ID_AA64ISAR1_SPECRES_MASK (0xfULL << ID_AA64ISAR1_SPECRES_SHIFT)
#define ID_AA64ISAR1_SPECRES(x) ((x) & ID_AA64ISAR1_SPECRES_MASK)
#define ID_AA64ISAR1_SPECRES_NONE (0x0ULL << ID_AA64ISAR1_SPECRES_SHIFT)
#define ID_AA64ISAR1_SPECRES_IMPL (0x1ULL << ID_AA64ISAR1_SPECRES_SHIFT)
#define ID_AA64ISAR1_BF16_SHIFT 44
#define ID_AA64ISAR1_BF16_MASK (0xfULL << ID_AA64ISAR1_BF16_SHIFT)
#define ID_AA64ISAR1_BF16(x) ((x) & ID_AA64ISAR1_BF16_MASK)
#define ID_AA64ISAR1_BF16_NONE (0x0ULL << ID_AA64ISAR1_BF16_SHIFT)
#define ID_AA64ISAR1_BF16_BASE (0x1ULL << ID_AA64ISAR1_BF16_SHIFT)
#define ID_AA64ISAR1_BF16_EBF (0x2ULL << ID_AA64ISAR1_BF16_SHIFT)
#define ID_AA64ISAR1_DGH_SHIFT 48
#define ID_AA64ISAR1_DGH_MASK (0xfULL << ID_AA64ISAR1_DGH_SHIFT)
#define ID_AA64ISAR1_DGH(x) ((x) & ID_AA64ISAR1_DGH_MASK)
#define ID_AA64ISAR1_DGH_NONE (0x0ULL << ID_AA64ISAR1_DGH_SHIFT)
#define ID_AA64ISAR1_DGH_IMPL (0x1ULL << ID_AA64ISAR1_DGH_SHIFT)
#define ID_AA64ISAR1_I8MM_SHIFT 52
#define ID_AA64ISAR1_I8MM_MASK (0xfULL << ID_AA64ISAR1_I8MM_SHIFT)
#define ID_AA64ISAR1_I8MM(x) ((x) & ID_AA64ISAR1_I8MM_MASK)
#define ID_AA64ISAR1_I8MM_NONE (0x0ULL << ID_AA64ISAR1_I8MM_SHIFT)
#define ID_AA64ISAR1_I8MM_IMPL (0x1ULL << ID_AA64ISAR1_I8MM_SHIFT)
#define ID_AA64ISAR1_XS_SHIFT 56
#define ID_AA64ISAR1_XS_MASK (0xfULL << ID_AA64ISAR1_XS_SHIFT)
#define ID_AA64ISAR1_XS(x) ((x) & ID_AA64ISAR1_XS_MASK)
#define ID_AA64ISAR1_XS_NONE (0x0ULL << ID_AA64ISAR1_XS_SHIFT)
#define ID_AA64ISAR1_XS_IMPL (0x1ULL << ID_AA64ISAR1_XS_SHIFT)
#define ID_AA64ISAR1_LS64_SHIFT 60
#define ID_AA64ISAR1_LS64_MASK (0xfULL << ID_AA64ISAR1_LS64_SHIFT)
#define ID_AA64ISAR1_LS64(x) ((x) & ID_AA64ISAR1_LS64_MASK)
#define ID_AA64ISAR1_LS64_NONE (0x0ULL << ID_AA64ISAR1_LS64_SHIFT)
#define ID_AA64ISAR1_LS64_BASE (0x1ULL << ID_AA64ISAR1_LS64_SHIFT)
#define ID_AA64ISAR1_LS64_V (0x2ULL << ID_AA64ISAR1_LS64_SHIFT)
#define ID_AA64ISAR1_LS64_ACCDATA (0x3ULL << ID_AA64ISAR1_LS64_SHIFT)
/* ID_AA64ISAR2_EL1 */
#define ID_AA64ISAR2_MASK 0x00ff0000f0ffffffULL
#define ID_AA64ISAR2_WFXT_SHIFT 0
#define ID_AA64ISAR2_WFXT_MASK (0xfULL << ID_AA64ISAR2_WFXT_SHIFT)
#define ID_AA64ISAR2_WFXT(x) ((x) & ID_AA64ISAR2_WFXT_MASK)
#define ID_AA64ISAR2_WFXT_NONE (0x0ULL << ID_AA64ISAR2_WFXT_SHIFT)
#define ID_AA64ISAR2_WFXT_IMPL (0x2ULL << ID_AA64ISAR2_WFXT_SHIFT)
#define ID_AA64ISAR2_RPRES_SHIFT 4
#define ID_AA64ISAR2_RPRES_MASK (0xfULL << ID_AA64ISAR2_RPRES_SHIFT)
#define ID_AA64ISAR2_RPRES(x) ((x) & ID_AA64ISAR2_RPRES_MASK)
#define ID_AA64ISAR2_RPRES_NONE (0x0ULL << ID_AA64ISAR2_RPRES_SHIFT)
#define ID_AA64ISAR2_RPRES_IMPL (0x1ULL << ID_AA64ISAR2_RPRES_SHIFT)
#define ID_AA64ISAR2_GPA3_SHIFT 8
#define ID_AA64ISAR2_GPA3_WIDTH 4
#define ID_AA64ISAR2_GPA3_MASK (0xfULL << ID_AA64ISAR2_GPA3_SHIFT)
#define ID_AA64ISAR2_GPA3(x) ((x) & ID_AA64ISAR2_GPA3_MASK)
#define ID_AA64ISAR2_GPA3_NONE (0x0ULL << ID_AA64ISAR2_GPA3_SHIFT)
#define ID_AA64ISAR2_GPA3_IMPL (0x1ULL << ID_AA64ISAR2_GPA3_SHIFT)
#define ID_AA64ISAR2_APA3_SHIFT 12
#define ID_AA64ISAR2_APA3_WIDTH 4
#define ID_AA64ISAR2_APA3_MASK (0xfULL << ID_AA64ISAR2_APA3_SHIFT)
#define ID_AA64ISAR2_APA3(x) ((x) & ID_AA64ISAR2_APA3_MASK)
#define ID_AA64ISAR2_APA3_NONE (0x0ULL << ID_AA64ISAR2_APA3_SHIFT)
#define ID_AA64ISAR2_APA3_PAC (0x1ULL << ID_AA64ISAR2_APA3_SHIFT)
#define ID_AA64ISAR2_APA3_EPAC (0x2ULL << ID_AA64ISAR2_APA3_SHIFT)
#define ID_AA64ISAR2_APA3_EPAC2 (0x3ULL << ID_AA64ISAR2_APA3_SHIFT)
#define ID_AA64ISAR2_APA3_FPAC (0x4ULL << ID_AA64ISAR2_APA3_SHIFT)
#define ID_AA64ISAR2_APA3_FPAC_COMBINED (0x5ULL << ID_AA64ISAR2_APA3_SHIFT)
#define ID_AA64ISAR2_MOPS_SHIFT 16
#define ID_AA64ISAR2_MOPS_MASK (0xfULL << ID_AA64ISAR2_MOPS_SHIFT)
#define ID_AA64ISAR2_MOPS(x) ((x) & ID_AA64ISAR2_MOPS_MASK)
#define ID_AA64ISAR2_MOPS_NONE (0x0ULL << ID_AA64ISAR2_MOPS_SHIFT)
#define ID_AA64ISAR2_MOPS_IMPL (0x1ULL << ID_AA64ISAR2_MOPS_SHIFT)
#define ID_AA64ISAR2_BC_SHIFT 20
#define ID_AA64ISAR2_BC_MASK (0xfULL << ID_AA64ISAR2_BC_SHIFT)
#define ID_AA64ISAR2_BC(x) ((x) & ID_AA64ISAR2_BC_MASK)
#define ID_AA64ISAR2_BC_NONE (0x0ULL << ID_AA64ISAR2_BC_SHIFT)
#define ID_AA64ISAR2_BC_IMPL (0x1ULL << ID_AA64ISAR2_BC_SHIFT)
#define ID_AA64ISAR2_CLRBHB_SHIFT 28
#define ID_AA64ISAR2_CLRBHB_MASK (0xfULL << ID_AA64ISAR2_CLRBHB_SHIFT)
#define ID_AA64ISAR2_CLRBHB(x) ((x) & ID_AA64ISAR2_CLRBHB_MASK)
#define ID_AA64ISAR2_CLRBHB_NONE (0x0ULL << ID_AA64ISAR2_CLRBHB_SHIFT)
#define ID_AA64ISAR2_CLRBHB_IMPL (0x1ULL << ID_AA64ISAR2_CLRBHB_SHIFT)
#define ID_AA64ISAR2_RPRFM_SHIFT 48
#define ID_AA64ISAR2_RPRFM_MASK (0xfULL << ID_AA64ISAR2_RPRFM_SHIFT)
#define ID_AA64ISAR2_RPRFM(x) ((x) & ID_AA64ISAR2_RPRFM_MASK)
#define ID_AA64ISAR2_RPRFM_NONE (0x0ULL << ID_AA64ISAR2_RPRFM_SHIFT)
#define ID_AA64ISAR2_RPRFM_IMPL (0x1ULL << ID_AA64ISAR2_RPRFM_SHIFT)
#define ID_AA64ISAR2_CSSC_SHIFT 52
#define ID_AA64ISAR2_CSSC_MASK (0xfULL << ID_AA64ISAR2_CSSC_SHIFT)
#define ID_AA64ISAR2_CSSC(x) ((x) & ID_AA64ISAR2_CSSC_MASK)
#define ID_AA64ISAR2_CSSC_NONE (0x0ULL << ID_AA64ISAR2_CSSC_SHIFT)
#define ID_AA64ISAR2_CSSC_IMPL (0x1ULL << ID_AA64ISAR2_CSSC_SHIFT)
/* ID_AA64MMFR0_EL1 */
#define ID_AA64MMFR0_MASK 0xf0000000ffffffffULL
#define ID_AA64MMFR0_PA_RANGE_SHIFT 0
#define ID_AA64MMFR0_PA_RANGE_MASK (0xfULL << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_PA_RANGE(x) ((x) & ID_AA64MMFR0_PA_RANGE_MASK)
#define ID_AA64MMFR0_PA_RANGE_4G (0x0ULL << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_PA_RANGE_64G (0x1ULL << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_PA_RANGE_1T (0x2ULL << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_PA_RANGE_4T (0x3ULL << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_PA_RANGE_16T (0x4ULL << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_PA_RANGE_256T (0x5ULL << ID_AA64MMFR0_PA_RANGE_SHIFT)
#define ID_AA64MMFR0_ASID_BITS_SHIFT 4
#define ID_AA64MMFR0_ASID_BITS_MASK (0xfULL << ID_AA64MMFR0_ASID_BITS_SHIFT)
#define ID_AA64MMFR0_ASID_BITS(x) ((x) & ID_AA64MMFR0_ASID_BITS_MASK)
#define ID_AA64MMFR0_ASID_BITS_8 (0x0ULL << ID_AA64MMFR0_ASID_BITS_SHIFT)
#define ID_AA64MMFR0_ASID_BITS_16 (0x2ULL << ID_AA64MMFR0_ASID_BITS_SHIFT)
#define ID_AA64MMFR0_BIGEND_SHIFT 8
#define ID_AA64MMFR0_BIGEND_MASK (0xfULL << ID_AA64MMFR0_BIGEND_SHIFT)
#define ID_AA64MMFR0_BIGEND(x) ((x) & ID_AA64MMFR0_BIGEND_MASK)
#define ID_AA64MMFR0_BIGEND_FIXED (0x0ULL << ID_AA64MMFR0_BIGEND_SHIFT)
#define ID_AA64MMFR0_BIGEND_MIXED (0x1ULL << ID_AA64MMFR0_BIGEND_SHIFT)
#define ID_AA64MMFR0_S_NS_MEM_SHIFT 12
#define ID_AA64MMFR0_S_NS_MEM_MASK (0xfULL << ID_AA64MMFR0_S_NS_MEM_SHIFT)
#define ID_AA64MMFR0_S_NS_MEM(x) ((x) & ID_AA64MMFR0_S_NS_MEM_MASK)
#define ID_AA64MMFR0_S_NS_MEM_NONE (0x0ULL << ID_AA64MMFR0_S_NS_MEM_SHIFT)
#define ID_AA64MMFR0_S_NS_MEM_DISTINCT (0x1ULL << ID_AA64MMFR0_S_NS_MEM_SHIFT)
#define ID_AA64MMFR0_BIGEND_EL0_SHIFT 16
#define ID_AA64MMFR0_BIGEND_EL0_MASK (0xfULL << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
#define ID_AA64MMFR0_BIGEND_EL0(x) ((x) & ID_AA64MMFR0_BIGEND_EL0_MASK)
#define ID_AA64MMFR0_BIGEND_EL0_FIXED (0x0ULL << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
#define ID_AA64MMFR0_BIGEND_EL0_MIXED (0x1ULL << ID_AA64MMFR0_BIGEND_EL0_SHIFT)
#define ID_AA64MMFR0_TGRAN16_SHIFT 20
#define ID_AA64MMFR0_TGRAN16_MASK (0xfULL << ID_AA64MMFR0_TGRAN16_SHIFT)
#define ID_AA64MMFR0_TGRAN16(x) ((x) & ID_AA64MMFR0_TGRAN16_MASK)
#define ID_AA64MMFR0_TGRAN16_NONE (0x0ULL << ID_AA64MMFR0_TGRAN16_SHIFT)
#define ID_AA64MMFR0_TGRAN16_IMPL (0x1ULL << ID_AA64MMFR0_TGRAN16_SHIFT)
#define ID_AA64MMFR0_TGRAN64_SHIFT 24
#define ID_AA64MMFR0_TGRAN64_MASK (0xfULL << ID_AA64MMFR0_TGRAN64_SHIFT)
#define ID_AA64MMFR0_TGRAN64(x) ((x) & ID_AA64MMFR0_TGRAN64_MASK)
#define ID_AA64MMFR0_TGRAN64_IMPL (0x0ULL << ID_AA64MMFR0_TGRAN64_SHIFT)
#define ID_AA64MMFR0_TGRAN64_NONE (0xfULL << ID_AA64MMFR0_TGRAN64_SHIFT)
#define ID_AA64MMFR0_TGRAN4_SHIFT 28
#define ID_AA64MMFR0_TGRAN4_MASK (0xfULL << ID_AA64MMFR0_TGRAN4_SHIFT)
#define ID_AA64MMFR0_TGRAN4(x) ((x) & ID_AA64MMFR0_TGRAN4_MASK)
#define ID_AA64MMFR0_TGRAN4_IMPL (0x0ULL << ID_AA64MMFR0_TGRAN4_SHIFT)
#define ID_AA64MMFR0_TGRAN4_NONE (0xfULL << ID_AA64MMFR0_TGRAN4_SHIFT)
#define ID_AA64MMFR0_ECV_SHIFT 60
#define ID_AA64MMFR0_ECV_MASK (0xfULL << ID_AA64MMFR0_ECV_SHIFT)
#define ID_AA64MMFR0_ECV(x) ((x) & ID_AA64MMFR0_ECV_MASK)
#define ID_AA64MMFR0_ECV_NONE (0x0ULL << ID_AA64MMFR0_ECV_SHIFT)
#define ID_AA64MMFR0_ECV_IMPL (0x1ULL << ID_AA64MMFR0_ECV_SHIFT)
#define ID_AA64MMFR0_ECV_CNTHCTL (0x2ULL << ID_AA64MMFR0_ECV_SHIFT)
/* ID_AA64MMFR1_EL1 */
#define ID_AA64MMFR1_MASK 0xf000f000ffffffffULL
#define ID_AA64MMFR1_HAFDBS_SHIFT 0
#define ID_AA64MMFR1_HAFDBS_MASK (0xfULL << ID_AA64MMFR1_HAFDBS_SHIFT)
#define ID_AA64MMFR1_HAFDBS(x) ((x) & ID_AA64MMFR1_HAFDBS_MASK)
#define ID_AA64MMFR1_HAFDBS_NONE (0x0ULL << ID_AA64MMFR1_HAFDBS_SHIFT)
#define ID_AA64MMFR1_HAFDBS_AF (0x1ULL << ID_AA64MMFR1_HAFDBS_SHIFT)
#define ID_AA64MMFR1_HAFDBS_AF_DBS (0x2ULL << ID_AA64MMFR1_HAFDBS_SHIFT)
#define ID_AA64MMFR1_VMIDBITS_SHIFT 4
#define ID_AA64MMFR1_VMIDBITS_MASK (0xfULL << ID_AA64MMFR1_VMIDBITS_SHIFT)
#define ID_AA64MMFR1_VMIDBITS(x) ((x) & ID_AA64MMFR1_VMIDBITS_MASK)
#define ID_AA64MMFR1_VMIDBITS_8 (0x0ULL << ID_AA64MMFR1_VMIDBITS_SHIFT)
#define ID_AA64MMFR1_VMIDBITS_16 (0x2ULL << ID_AA64MMFR1_VMIDBITS_SHIFT)
#define ID_AA64MMFR1_VH_SHIFT 8
#define ID_AA64MMFR1_VH_MASK (0xfULL << ID_AA64MMFR1_VH_SHIFT)
#define ID_AA64MMFR1_VH(x) ((x) & ID_AA64MMFR1_VH_MASK)
#define ID_AA64MMFR1_VH_NONE (0x0ULL << ID_AA64MMFR1_VH_SHIFT)
#define ID_AA64MMFR1_VH_IMPL (0x1ULL << ID_AA64MMFR1_VH_SHIFT)
#define ID_AA64MMFR1_HPDS_SHIFT 12
#define ID_AA64MMFR1_HPDS_MASK (0xfULL << ID_AA64MMFR1_HPDS_SHIFT)
#define ID_AA64MMFR1_HPDS(x) ((x) & ID_AA64MMFR1_HPDS_MASK)
#define ID_AA64MMFR1_HPDS_NONE (0x0ULL << ID_AA64MMFR1_HPDS_SHIFT)
#define ID_AA64MMFR1_HPDS_IMPL (0x1ULL << ID_AA64MMFR1_HPDS_SHIFT)
#define ID_AA64MMFR1_LO_SHIFT 16
#define ID_AA64MMFR1_LO_MASK (0xfULL << ID_AA64MMFR1_LO_SHIFT)
#define ID_AA64MMFR1_LO(x) ((x) & ID_AA64MMFR1_LO_MASK)
#define ID_AA64MMFR1_LO_NONE (0x0ULL << ID_AA64MMFR1_LO_SHIFT)
#define ID_AA64MMFR1_LO_IMPL (0x1ULL << ID_AA64MMFR1_LO_SHIFT)
#define ID_AA64MMFR1_PAN_SHIFT 20
#define ID_AA64MMFR1_PAN_MASK (0xfULL << ID_AA64MMFR1_PAN_SHIFT)
#define ID_AA64MMFR1_PAN(x) ((x) & ID_AA64MMFR1_PAN_MASK)
#define ID_AA64MMFR1_PAN_NONE (0x0ULL << ID_AA64MMFR1_PAN_SHIFT)
#define ID_AA64MMFR1_PAN_IMPL (0x1ULL << ID_AA64MMFR1_PAN_SHIFT)
#define ID_AA64MMFR1_PAN_ATS1E1 (0x2ULL << ID_AA64MMFR1_PAN_SHIFT)
#define ID_AA64MMFR1_PAN_EPAN (0x3ULL << ID_AA64MMFR1_PAN_SHIFT)
#define ID_AA64MMFR1_SPECSEI_SHIFT 24
#define ID_AA64MMFR1_SPECSEI_MASK (0xfULL << ID_AA64MMFR1_SPECSEI_SHIFT)
#define ID_AA64MMFR1_SPECSEI(x) ((x) & ID_AA64MMFR1_SPECSEI_MASK)
#define ID_AA64MMFR1_SPECSEI_NONE (0x0ULL << ID_AA64MMFR1_SPECSEI_SHIFT)
#define ID_AA64MMFR1_SPECSEI_IMPL (0x1ULL << ID_AA64MMFR1_SPECSEI_SHIFT)
#define ID_AA64MMFR1_XNX_SHIFT 28
#define ID_AA64MMFR1_XNX_MASK (0xfULL << ID_AA64MMFR1_XNX_SHIFT)
#define ID_AA64MMFR1_XNX(x) ((x) & ID_AA64MMFR1_XNX_MASK)
#define ID_AA64MMFR1_XNX_NONE (0x0ULL << ID_AA64MMFR1_XNX_SHIFT)
#define ID_AA64MMFR1_XNX_IMPL (0x1ULL << ID_AA64MMFR1_XNX_SHIFT)
#define ID_AA64MMFR1_AFP_SHIFT 44
#define ID_AA64MMFR1_AFP_MASK (0xfULL << ID_AA64MMFR1_AFP_SHIFT)
#define ID_AA64MMFR1_AFP(x) ((x) & ID_AA64MMFR1_AFP_MASK)
#define ID_AA64MMFR1_AFP_NONE (0x0ULL << ID_AA64MMFR1_AFP_SHIFT)
#define ID_AA64MMFR1_AFP_IMPL (0x1ULL << ID_AA64MMFR1_AFP_SHIFT)
#define ID_AA64MMFR1_ECBHB_SHIFT 60
#define ID_AA64MMFR1_ECBHB_MASK (0xfULL << ID_AA64MMFR1_ECBHB_SHIFT)
#define ID_AA64MMFR1_ECBHB(x) ((x) & ID_AA64MMFR1_ECBHB_MASK)
#define ID_AA64MMFR1_ECBHB_NONE (0x0ULL << ID_AA64MMFR1_ECBHB_SHIFT)
#define ID_AA64MMFR1_ECBHB_IMPL (0x1ULL << ID_AA64MMFR1_ECBHB_SHIFT)
/* ID_AA64MMFR2_EL1 */
#define ID_AA64MMFR2_MASK 0xffff0fffffffffffULL
#define ID_AA64MMFR2_CCIDX_SHIFT 20
#define ID_AA64MMFR2_CCIDX_MASK (0xfULL << ID_AA64MMFR2_CCIDX_SHIFT)
#define ID_AA64MMFR2_CCIDX(x) ((x) & ID_AA64MMFR2_CCIDX_MASK)
#define ID_AA64MMFR2_CCIDX_IMPL (0x1ULL << ID_AA64MMFR2_CCIDX_SHIFT)
#define ID_AA64MMFR2_AT_SHIFT 32
#define ID_AA64MMFR2_AT_MASK (0xfULL << ID_AA64MMFR2_AT_SHIFT)
#define ID_AA64MMFR2_AT(x) ((x) & ID_AA64MMFR2_AT_MASK)
#define ID_AA64MMFR2_AT_NONE (0x0ULL << ID_AA64MMFR2_AT_SHIFT)
#define ID_AA64MMFR2_AT_IMPL (0x1ULL << ID_AA64MMFR2_AT_SHIFT)
#define ID_AA64MMFR2_IDS_SHIFT 36
#define ID_AA64MMFR2_IDS_MASK (0xfULL << ID_AA64MMFR2_IDS_SHIFT)
#define ID_AA64MMFR2_IDS(x) ((x) & ID_AA64MMFR2_IDS_MASK)
#define ID_AA64MMFR2_IDS_NONE (0x0ULL << ID_AA64MMFR2_IDS_SHIFT)
#define ID_AA64MMFR2_IDS_IMPL (0x1ULL << ID_AA64MMFR2_IDS_SHIFT)
/* ID_AA64PFR0_EL1 */
#define ID_AA64PFR0_MASK 0xff0fffffffffffffULL
#define ID_AA64PFR0_EL0_SHIFT 0
#define ID_AA64PFR0_EL0_MASK (0xfULL << ID_AA64PFR0_EL0_SHIFT)
#define ID_AA64PFR0_EL0(x) ((x) & ID_AA64PFR0_EL0_MASK)
#define ID_AA64PFR0_EL0_64 (0x1ULL << ID_AA64PFR0_EL0_SHIFT)
#define ID_AA64PFR0_EL0_64_32 (0x2ULL << ID_AA64PFR0_EL0_SHIFT)
#define ID_AA64PFR0_EL1_SHIFT 4
#define ID_AA64PFR0_EL1_MASK (0xfULL << ID_AA64PFR0_EL1_SHIFT)
#define ID_AA64PFR0_EL1(x) ((x) & ID_AA64PFR0_EL1_MASK)
#define ID_AA64PFR0_EL1_64 (0x1ULL << ID_AA64PFR0_EL1_SHIFT)
#define ID_AA64PFR0_EL1_64_32 (0x2ULL << ID_AA64PFR0_EL1_SHIFT)
#define ID_AA64PFR0_EL2_SHIFT 8
#define ID_AA64PFR0_EL2_MASK (0xfULL << ID_AA64PFR0_EL2_SHIFT)
#define ID_AA64PFR0_EL2(x) ((x) & ID_AA64PFR0_EL2_MASK)
#define ID_AA64PFR0_EL2_NONE (0x0ULL << ID_AA64PFR0_EL2_SHIFT)
#define ID_AA64PFR0_EL2_64 (0x1ULL << ID_AA64PFR0_EL2_SHIFT)
#define ID_AA64PFR0_EL2_64_32 (0x2ULL << ID_AA64PFR0_EL2_SHIFT)
#define ID_AA64PFR0_EL3_SHIFT 12
#define ID_AA64PFR0_EL3_MASK (0xfULL << ID_AA64PFR0_EL3_SHIFT)
#define ID_AA64PFR0_EL3(x) ((x) & ID_AA64PFR0_EL3_MASK)
#define ID_AA64PFR0_EL3_NONE (0x0ULL << ID_AA64PFR0_EL3_SHIFT)
#define ID_AA64PFR0_EL3_64 (0x1ULL << ID_AA64PFR0_EL3_SHIFT)
#define ID_AA64PFR0_EL3_64_32 (0x2ULL << ID_AA64PFR0_EL3_SHIFT)
#define ID_AA64PFR0_FP_SHIFT 16
#define ID_AA64PFR0_FP_MASK (0xfULL << ID_AA64PFR0_FP_SHIFT)
#define ID_AA64PFR0_FP(x) ((x) & ID_AA64PFR0_FP_MASK)
#define ID_AA64PFR0_FP_IMPL (0x0ULL << ID_AA64PFR0_FP_SHIFT)
#define ID_AA64PFR0_FP_HP (0x1ULL << ID_AA64PFR0_FP_SHIFT)
#define ID_AA64PFR0_FP_NONE (0xfULL << ID_AA64PFR0_FP_SHIFT)
#define ID_AA64PFR0_ADV_SIMD_SHIFT 20
#define ID_AA64PFR0_ADV_SIMD_MASK (0xfULL << ID_AA64PFR0_ADV_SIMD_SHIFT)
#define ID_AA64PFR0_ADV_SIMD(x) ((x) & ID_AA64PFR0_ADV_SIMD_MASK)
#define ID_AA64PFR0_ADV_SIMD_IMPL (0x0ULL << ID_AA64PFR0_ADV_SIMD_SHIFT)
#define ID_AA64PFR0_ADV_SIMD_HP (0x1ULL << ID_AA64PFR0_ADV_SIMD_SHIFT)
#define ID_AA64PFR0_ADV_SIMD_NONE (0xfULL << ID_AA64PFR0_ADV_SIMD_SHIFT)
#define ID_AA64PFR0_GIC_BITS 0x4 /* Number of bits in GIC field */
#define ID_AA64PFR0_GIC_SHIFT 24
#define ID_AA64PFR0_GIC_MASK (0xfULL << ID_AA64PFR0_GIC_SHIFT)
#define ID_AA64PFR0_GIC(x) ((x) & ID_AA64PFR0_GIC_MASK)
#define ID_AA64PFR0_GIC_CPUIF_NONE (0x0ULL << ID_AA64PFR0_GIC_SHIFT)
#define ID_AA64PFR0_GIC_CPUIF_EN (0x1ULL << ID_AA64PFR0_GIC_SHIFT)
#define ID_AA64PFR0_RAS_SHIFT 28
#define ID_AA64PFR0_RAS_MASK (0xfULL << ID_AA64PFR0_RAS_SHIFT)
#define ID_AA64PFR0_RAS(x) ((x) & ID_AA64PFR0_RAS_MASK)
#define ID_AA64PFR0_RAS_NONE (0x0ULL << ID_AA64PFR0_RAS_SHIFT)
#define ID_AA64PFR0_RAS_IMPL (0x1ULL << ID_AA64PFR0_RAS_SHIFT)
#define ID_AA64PFR0_RAS_IMPL_V1P1 (0x2ULL << ID_AA64PFR0_RAS_SHIFT)
#define ID_AA64PFR0_SVE_SHIFT 32
#define ID_AA64PFR0_SVE_MASK (0xfULL << ID_AA64PFR0_SVE_SHIFT)
#define ID_AA64PFR0_SVE(x) ((x) & ID_AA64PFR0_SVE_MASK)
#define ID_AA64PFR0_SVE_NONE (0x0ULL << ID_AA64PFR0_SVE_SHIFT)
#define ID_AA64PFR0_SVE_IMPL (0x1ULL << ID_AA64PFR0_SVE_SHIFT)
#define ID_AA64PFR0_SEL2_SHIFT 36
#define ID_AA64PFR0_SEL2_MASK (0xfULL << ID_AA64PFR0_SEL2_SHIFT)
#define ID_AA64PFR0_SEL2(x) ((x) & ID_AA64PFR0_SEL2_MASK)
#define ID_AA64PFR0_SEL2_NONE (0x0ULL << ID_AA64PFR0_SEL2_SHIFT)
#define ID_AA64PFR0_SEL2_IMPL (0x1ULL << ID_AA64PFR0_SEL2_SHIFT)
#define ID_AA64PFR0_MPAM_SHIFT 40
#define ID_AA64PFR0_MPAM_MASK (0xfULL << ID_AA64PFR0_MPAM_SHIFT)
#define ID_AA64PFR0_MPAM(x) ((x) & ID_AA64PFR0_MPAM_MASK)
#define ID_AA64PFR0_MPAM_NONE (0x0ULL << ID_AA64PFR0_MPAM_SHIFT)
#define ID_AA64PFR0_MPAM_IMPL (0x1ULL << ID_AA64PFR0_MPAM_SHIFT)
#define ID_AA64PFR0_AMU_SHIFT 44
#define ID_AA64PFR0_AMU_MASK (0xfULL << ID_AA64PFR0_AMU_SHIFT)
#define ID_AA64PFR0_AMU(x) ((x) & ID_AA64PFR0_AMU_MASK)
#define ID_AA64PFR0_AMU_NONE (0x0ULL << ID_AA64PFR0_AMU_SHIFT)
#define ID_AA64PFR0_AMU_IMPL (0x1ULL << ID_AA64PFR0_AMU_SHIFT)
#define ID_AA64PFR0_AMU_IMPL_V1P1 (0x2ULL << ID_AA64PFR0_AMU_SHIFT)
#define ID_AA64PFR0_DIT_SHIFT 48
#define ID_AA64PFR0_DIT_MASK (0xfULL << ID_AA64PFR0_DIT_SHIFT)
#define ID_AA64PFR0_DIT(x) ((x) & ID_AA64PFR0_DIT_MASK)
#define ID_AA64PFR0_DIT_UNKNOWN (0x0ULL << ID_AA64PFR0_DIT_SHIFT)
#define ID_AA64PFR0_DIT_IMPL (0x1ULL << ID_AA64PFR0_DIT_SHIFT)
#define ID_AA64PFR0_CSV2_SHIFT 56
#define ID_AA64PFR0_CSV2_MASK (0xfULL << ID_AA64PFR0_CSV2_SHIFT)
#define ID_AA64PFR0_CSV2(x) ((x) & ID_AA64PFR0_CSV2_MASK)
#define ID_AA64PFR0_CSV2_UNKNOWN (0x0ULL << ID_AA64PFR0_CSV2_SHIFT)
#define ID_AA64PFR0_CSV2_IMPL (0x1ULL << ID_AA64PFR0_CSV2_SHIFT)
#define ID_AA64PFR0_CSV2_SCXT (0x2ULL << ID_AA64PFR0_CSV2_SHIFT)
#define ID_AA64PFR0_CSV2_HCXT (0x3ULL << ID_AA64PFR0_CSV2_SHIFT)
#define ID_AA64PFR0_CSV3_SHIFT 60
#define ID_AA64PFR0_CSV3_MASK (0xfULL << ID_AA64PFR0_CSV3_SHIFT)
#define ID_AA64PFR0_CSV3(x) ((x) & ID_AA64PFR0_CSV3_MASK)
#define ID_AA64PFR0_CSV3_UNKNOWN (0x0ULL << ID_AA64PFR0_CSV3_SHIFT)
#define ID_AA64PFR0_CSV3_IMPL (0x1ULL << ID_AA64PFR0_CSV3_SHIFT)
/* ID_AA64PFR1_EL1 */
#define ID_AA64PFR1_MASK 0x000000000000ffffULL
#define ID_AA64PFR1_BT_SHIFT 0
#define ID_AA64PFR1_BT_MASK (0xfULL << ID_AA64PFR1_BT_SHIFT)
#define ID_AA64PFR1_BT(x) ((x) & ID_AA64PFR1_BT_MASK)
#define ID_AA64PFR1_BT_NONE (0x0ULL << ID_AA64PFR1_BT_SHIFT)
#define ID_AA64PFR1_BT_IMPL (0x1ULL << ID_AA64PFR1_BT_SHIFT)
#define ID_AA64PFR1_SSBS_SHIFT 4
#define ID_AA64PFR1_SSBS_MASK (0xfULL << ID_AA64PFR1_SSBS_SHIFT)
#define ID_AA64PFR1_SSBS(x) ((x) & ID_AA64PFR1_SSBS_MASK)
#define ID_AA64PFR1_SSBS_NONE (0x0ULL << ID_AA64PFR1_SSBS_SHIFT)
#define ID_AA64PFR1_SSBS_PSTATE (0x1ULL << ID_AA64PFR1_SSBS_SHIFT)
#define ID_AA64PFR1_SSBS_PSTATE_MSR (0x2ULL << ID_AA64PFR1_SSBS_SHIFT)
#define ID_AA64PFR1_MTE_SHIFT 8
#define ID_AA64PFR1_MTE_MASK (0xfULL << ID_AA64PFR1_MTE_SHIFT)
#define ID_AA64PFR1_MTE(x) ((x) & ID_AA64PFR1_MTE_MASK)
#define ID_AA64PFR1_MTE_NONE (0x0ULL << ID_AA64PFR1_MTE_SHIFT)
#define ID_AA64PFR1_MTE_IMPL (0x1ULL << ID_AA64PFR1_MTE_SHIFT)
#define ID_AA64PFR1_RAS_FRAC_SHIFT 12
#define ID_AA64PFR1_RAS_FRAC_MASK (0xfULL << ID_AA64PFR1_RAS_FRAC_SHIFT)
#define ID_AA64PFR1_RAS_FRAC(x) ((x) & ID_AA64PFR1_RAS_FRAC_MASK)
#define ID_AA64PFR1_RAS_FRAC_NONE (0x0ULL << ID_AA64PFR1_RAS_FRAC_SHIFT)
#define ID_AA64PFR1_RAS_FRAC_IMPL (0x1ULL << ID_AA64PFR1_RAS_FRAC_SHIFT)
/* ID_AA64ZFR0_EL1 */
#define ID_AA64ZFR0_MASK 0x0ff0ff0f00ff00ffULL
#define ID_AA64ZFR0_SVEVER_SHIFT 0
#define ID_AA64ZFR0_SVEVER_MASK (0xfULL << ID_AA64ZFR0_SVEVER_SHIFT)
#define ID_AA64ZFR0_SVEVER(x) ((x) & ID_AA64ZFR0_SVEVER_MASK)
#define ID_AA64ZFR0_SVEVER_SVE1 (0x0ULL << ID_AA64ZFR0_SVEVER_SHIFT)
#define ID_AA64ZFR0_SVEVER_SVE2 (0x1ULL << ID_AA64ZFR0_SVEVER_SHIFT)
#define ID_AA64ZFR0_SVEVER_SVE2P1 (0x2ULL << ID_AA64ZFR0_SVEVER_SHIFT)
#define ID_AA64ZFR0_AES_SHIFT 4
#define ID_AA64ZFR0_AES_MASK (0xfULL << ID_AA64ZFR0_AES_SHIFT)
#define ID_AA64ZFR0_AES(x) ((x) & ID_AA64ZFR0_AES_MASK)
#define ID_AA64ZFR0_AES_NONE (0x0ULL << ID_AA64ZFR0_AES_SHIFT)
#define ID_AA64ZFR0_AES_BASE (0x1ULL << ID_AA64ZFR0_AES_SHIFT)
#define ID_AA64ZFR0_AES_PMULL (0x2ULL << ID_AA64ZFR0_AES_SHIFT)
#define ID_AA64ZFR0_BITPERM_SHIFT 16
#define ID_AA64ZFR0_BITPERM_MASK (0xfULL << ID_AA64ZFR0_BITPERM_SHIFT)
#define ID_AA64ZFR0_BITPERM(x) ((x) & ID_AA64ZFR0_BITPERM_MASK)
#define ID_AA64ZFR0_BITPERM_NONE (0x0ULL << ID_AA64ZFR0_BITPERM_SHIFT)
#define ID_AA64ZFR0_BITPERM_IMPL (0x1ULL << ID_AA64ZFR0_BITPERM_SHIFT)
#define ID_AA64ZFR0_BF16_SHIFT 20
#define ID_AA64ZFR0_BF16_MASK (0xfULL << ID_AA64ZFR0_BF16_SHIFT)
#define ID_AA64ZFR0_BF16(x) ((x) & ID_AA64ZFR0_BF16_MASK)
#define ID_AA64ZFR0_BF16_NONE (0x0ULL << ID_AA64ZFR0_BF16_SHIFT)
#define ID_AA64ZFR0_BF16_BASE (0x1ULL << ID_AA64ZFR0_BF16_SHIFT)
#define ID_AA64ZFR0_BF16_EBF (0x2ULL << ID_AA64ZFR0_BF16_SHIFT)
#define ID_AA64ZFR0_SHA3_SHIFT 32
#define ID_AA64ZFR0_SHA3_MASK (0xfULL << ID_AA64ZFR0_SHA3_SHIFT)
#define ID_AA64ZFR0_SHA3(x) ((x) & ID_AA64ZFR0_SHA3_MASK)
#define ID_AA64ZFR0_SHA3_NONE (0x0ULL << ID_AA64ZFR0_SHA3_SHIFT)
#define ID_AA64ZFR0_SHA3_IMPL (0x1ULL << ID_AA64ZFR0_SHA3_SHIFT)
#define ID_AA64ZFR0_SM4_SHIFT 40
#define ID_AA64ZFR0_SM4_MASK (0xfULL << ID_AA64ZFR0_SM4_SHIFT)
#define ID_AA64ZFR0_SM4(x) ((x) & ID_AA64ZFR0_SM4_MASK)
#define ID_AA64ZFR0_SM4_NONE (0x0ULL << ID_AA64ZFR0_SM4_SHIFT)
#define ID_AA64ZFR0_SM4_IMPL (0x1ULL << ID_AA64ZFR0_SM4_SHIFT)
#define ID_AA64ZFR0_I8MM_SHIFT 44
#define ID_AA64ZFR0_I8MM_MASK (0xfULL << ID_AA64ZFR0_I8MM_SHIFT)
#define ID_AA64ZFR0_I8MM(x) ((x) & ID_AA64ZFR0_I8MM_MASK)
#define ID_AA64ZFR0_I8MM_NONE (0x0ULL << ID_AA64ZFR0_I8MM_SHIFT)
#define ID_AA64ZFR0_I8MM_IMPL (0x1ULL << ID_AA64ZFR0_I8MM_SHIFT)
#define ID_AA64ZFR0_F32MM_SHIFT 52
#define ID_AA64ZFR0_F32MM_MASK (0xfULL << ID_AA64ZFR0_F32MM_SHIFT)
#define ID_AA64ZFR0_F32MM(x) ((x) & ID_AA64ZFR0_F32MM_MASK)
#define ID_AA64ZFR0_F32MM_NONE (0x0ULL << ID_AA64ZFR0_F32MM_SHIFT)
#define ID_AA64ZFR0_F32MM_IMPL (0x1ULL << ID_AA64ZFR0_F32MM_SHIFT)
#define ID_AA64ZFR0_F64MM_SHIFT 56
#define ID_AA64ZFR0_F64MM_MASK (0xfULL << ID_AA64ZFR0_F64MM_SHIFT)
#define ID_AA64ZFR0_F64MM(x) ((x) & ID_AA64ZFR0_F64MM_MASK)
#define ID_AA64ZFR0_F64MM_NONE (0x0ULL << ID_AA64ZFR0_F64MM_SHIFT)
#define ID_AA64ZFR0_F64MM_IMPL (0x1ULL << ID_AA64ZFR0_F64MM_SHIFT)
/* MAIR_EL1 - Memory Attribute Indirection Register */
#define MAIR_ATTR_MASK(idx) (0xff << ((n)* 8))
#define MAIR_ATTR(attr, idx) ((attr) << ((idx) * 8))
#define MAIR_DEVICE_nGnRnE 0x00
#define MAIR_NORMAL_NC 0x44
#define MAIR_NORMAL_WT 0x88
#define MAIR_NORMAL_WB 0xff
/* PAR_EL1 - Physical Address Register */
#define PAR_F_SHIFT 0
#define PAR_F (0x1 << PAR_F_SHIFT)
#define PAR_SUCCESS(x) (((x) & PAR_F) == 0)
/* When PAR_F == 0 (success) */
#define PAR_SH_SHIFT 7
#define PAR_SH_MASK (0x3 << PAR_SH_SHIFT)
#define PAR_NS_SHIFT 9
#define PAR_NS_MASK (0x3 << PAR_NS_SHIFT)
#define PAR_PA_SHIFT 12
#define PAR_PA_MASK 0x0000fffffffff000
#define PAR_ATTR_SHIFT 56
#define PAR_ATTR_MASK (0xff << PAR_ATTR_SHIFT)
/* When PAR_F == 1 (aborted) */
#define PAR_FST_SHIFT 1
#define PAR_FST_MASK (0x3f << PAR_FST_SHIFT)
#define PAR_PTW_SHIFT 8
#define PAR_PTW_MASK (0x1 << PAR_PTW_SHIFT)
#define PAR_S_SHIFT 9
#define PAR_S_MASK (0x1 << PAR_S_SHIFT)
/* SCTLR_EL1 - System Control Register */
#define SCTLR_RES0 0xffffffffc8222400 /* Reserved, write 0 */
#define SCTLR_RES1 0x0000000030d00800 /* Reserved, write 1 */
#define SCTLR_M 0x0000000000000001
#define SCTLR_A 0x0000000000000002
#define SCTLR_C 0x0000000000000004
#define SCTLR_SA 0x0000000000000008
#define SCTLR_SA0 0x0000000000000010
#define SCTLR_CP15BEN 0x0000000000000020
#define SCTLR_THEE 0x0000000000000040
#define SCTLR_ITD 0x0000000000000080
#define SCTLR_SED 0x0000000000000100
#define SCTLR_UMA 0x0000000000000200
#define SCTLR_I 0x0000000000001000
#define SCTLR_EnDB 0x0000000000002000
#define SCTLR_DZE 0x0000000000004000
#define SCTLR_UCT 0x0000000000008000
#define SCTLR_nTWI 0x0000000000010000
#define SCTLR_nTWE 0x0000000000040000
#define SCTLR_WXN 0x0000000000080000
#define SCTLR_SPAN 0x0000000000800000
#define SCTLR_EOE 0x0000000001000000
#define SCTLR_EE 0x0000000002000000
#define SCTLR_UCI 0x0000000004000000
#define SCTLR_EnDA 0x0000000008000000
#define SCTLR_EnIB 0x0000000040000000
#define SCTLR_EnIA 0x0000000080000000
#define SCTLR_BT0 0x0000000800000000
#define SCTLR_BT1 0x0000001000000000
#define SCTLR_EPAN 0x0200000000000000
/* SPSR_EL1 */
/*
* When the exception is taken in AArch64:
* M[4] is 0 for AArch64 mode
* M[3:2] is the exception level
* M[1] is unused
* M[0] is the SP select:
* 0: always SP0
* 1: current ELs SP
*/
#define PSR_M_EL0t 0x00000000
#define PSR_M_EL1t 0x00000004
#define PSR_M_EL1h 0x00000005
#define PSR_M_EL2t 0x00000008
#define PSR_M_EL2h 0x00000009
#define PSR_M_MASK 0x0000001f
#define PSR_F 0x00000040
#define PSR_I 0x00000080
#define PSR_A 0x00000100
#define PSR_D 0x00000200
#define PSR_BTYPE 0x00000c00
#define PSR_SSBS 0x00001000
#define PSR_IL 0x00100000
#define PSR_SS 0x00200000
#define PSR_PAN 0x00400000
#define PSR_UAO 0x00800000
#define PSR_DIT 0x01000000
#define PSR_TCO 0x02000000
#define PSR_V 0x10000000
#define PSR_C 0x20000000
#define PSR_Z 0x40000000
#define PSR_N 0x80000000
/* TCR_EL1 - Translation Control Register */
#define TCR_AS (1UL << 36)
#define TCR_IPS_SHIFT 32
#define TCR_IPS_32BIT (0UL << TCR_IPS_SHIFT)
#define TCR_IPS_36BIT (1UL << TCR_IPS_SHIFT)
#define TCR_IPS_40BIT (2UL << TCR_IPS_SHIFT)
#define TCR_IPS_42BIT (3UL << TCR_IPS_SHIFT)
#define TCR_IPS_44BIT (4UL << TCR_IPS_SHIFT)
#define TCR_IPS_48BIT (5UL << TCR_IPS_SHIFT)
#define TCR_TG1_SHIFT 30
#define TCR_TG1_16K (1UL << TCR_TG1_SHIFT)
#define TCR_TG1_4K (2UL << TCR_TG1_SHIFT)
#define TCR_TG1_64K (3UL << TCR_TG1_SHIFT)
#define TCR_SH1_SHIFT 28
#define TCR_SH1_IS (0x3UL << TCR_SH1_SHIFT)
#define TCR_ORGN1_SHIFT 26
#define TCR_ORGN1_WBWA (0x1UL << TCR_ORGN1_SHIFT)
#define TCR_IRGN1_SHIFT 24
#define TCR_IRGN1_WBWA (0x1UL << TCR_IRGN1_SHIFT)
#define TCR_A1 (1UL << 22)
#define TCR_TG0_SHIFT 14
#define TCR_TG0_4K (0UL << TCR_TG0_SHIFT)
#define TCR_TG0_64K (1UL << TCR_TG0_SHIFT)
#define TCR_TG0_16K (2UL << TCR_TG0_SHIFT)
#define TCR_SH0_SHIFT 12
#define TCR_SH0_IS (0x3UL << TCR_SH0_SHIFT)
#define TCR_ORGN0_SHIFT 10
#define TCR_ORGN0_WBWA (0x1UL << TCR_ORGN0_SHIFT)
#define TCR_IRGN0_SHIFT 8
#define TCR_IRGN0_WBWA (0x1UL << TCR_IRGN0_SHIFT)
#define TCR_CACHE_ATTRS ((TCR_IRGN0_WBWA | TCR_IRGN1_WBWA) |\
(TCR_ORGN0_WBWA | TCR_ORGN1_WBWA))
#define TCR_SMP_ATTRS (TCR_SH0_IS | TCR_SH1_IS)
#define TCR_T1SZ_SHIFT 16
#define TCR_T0SZ_SHIFT 0
#define TCR_T1SZ(x) ((x) << TCR_T1SZ_SHIFT)
#define TCR_T0SZ(x) ((x) << TCR_T0SZ_SHIFT)
#define TCR_TxSZ(x) (TCR_T1SZ(x) | TCR_T0SZ(x))
/* Monitor Debug System Control Register */
#define DBG_MDSCR_SS (0x1 << 0)
#define DBG_MDSCR_TDCC (0x1 << 12)
#define DBG_MDSCR_KDE (0x1 << 13)
#define DBG_MDSCR_MDE (0x1 << 15)
/* Performance Monitoring Counters */
#define PMCR_E (1 << 0) /* Enable all counters */
#define PMCR_P (1 << 1) /* Reset all counters */
#define PMCR_C (1 << 2) /* Clock counter reset */
#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */
#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */
#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
#define PMCR_LC (1 << 6) /* Long cycle count enable */
#define PMCR_IMP_SHIFT 24 /* Implementer code */
#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT)
#define PMCR_IDCODE_SHIFT 16 /* Identification code */
#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT)
#define PMCR_IDCODE_CORTEX_A57 0x01
#define PMCR_IDCODE_CORTEX_A72 0x02
#define PMCR_IDCODE_CORTEX_A53 0x03
#define PMCR_N_SHIFT 11 /* Number of counters implemented */
#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT)
#define I_bit (1 << 7) /* IRQ disable */
#define F_bit 0 /* FIQ disable - not actually used */
#endif /* !_MACHINE_ARMREG_H_ */

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@ -0,0 +1,150 @@
/* $OpenBSD: asm.h,v 1.12 2023/03/27 19:02:48 kettenis Exp $ */
/* $NetBSD: asm.h,v 1.4 2001/07/16 05:43:32 matt Exp $ */
/*
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* William Jolitz.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)asm.h 5.5 (Berkeley) 5/7/91
*/
#ifndef _MACHINE_ASM_H_
#define _MACHINE_ASM_H_
#define _C_LABEL(x) x
#define _ASM_LABEL(x) x
#ifdef __STDC__
# define __CONCAT(x,y) x ## y
# define __STRING(x) #x
#else
# define __CONCAT(x,y) x/**/y
# define __STRING(x) "x"
#endif
#ifndef _ALIGN_TEXT
# define _ALIGN_TEXT .align 0
#endif
/*
* gas/arm uses @ as a single comment character and thus cannot be used here
* Instead it recognised the # instead of an @ symbols in .type directives
* We define a couple of macros so that assembly code will not be dependant
* on one or the other.
*/
#define _ASM_TYPE_FUNCTION #function
#define _ASM_TYPE_OBJECT #object
/* NB == No Binding: use .globl or .weak as necessary */
#define _ENTRY_NB(x) \
.text; _ALIGN_TEXT; .type x,_ASM_TYPE_FUNCTION; x:
#define _ENTRY(x) .globl x; _ENTRY_NB(x)
#if defined(PROF) || defined(GPROF)
# define _PROF_PROLOGUE \
stp x29, x30, [sp, #-16]!; \
mov fp, sp; \
bl __mcount; \
ldp x29, x30, [sp], #16;
#else
# define _PROF_PROLOGUE
#endif
#if defined(_RET_PROTECTOR)
# define RETGUARD_CALC_COOKIE(reg) \
eor reg, reg, x30
# define RETGUARD_LOAD_RANDOM(x, reg) \
adrp reg, __CONCAT(__retguard_, x); \
ldr reg, [reg, :lo12:__CONCAT(__retguard_, x)]
# define RETGUARD_SETUP(x, reg) \
RETGUARD_SYMBOL(x); \
RETGUARD_LOAD_RANDOM(x, reg); \
RETGUARD_CALC_COOKIE(reg)
# define RETGUARD_CHECK(x, reg) \
RETGUARD_CALC_COOKIE(reg); \
RETGUARD_LOAD_RANDOM(x, x9); \
subs reg, reg, x9; \
cbz reg, 66f; \
brk #0x1; \
66:
# define RETGUARD_PUSH(reg) \
str reg, [sp, #-16]!
# define RETGUARD_POP(reg) \
ldr reg, [sp, #16]!
# define RETGUARD_SYMBOL(x) \
.ifndef __CONCAT(__retguard_, x); \
.hidden __CONCAT(__retguard_, x); \
.type __CONCAT(__retguard_, x),@object; \
.pushsection .openbsd.randomdata.retguard,"aw",@progbits; \
.weak __CONCAT(__retguard_, x); \
.p2align 3; \
__CONCAT(__retguard_, x): ; \
.xword 0; \
.size __CONCAT(__retguard_, x), 8; \
.popsection; \
.endif
#else
# define RETGUARD_CALC_COOKIE(reg)
# define RETGUARD_LOAD_RANDOM(x, reg)
# define RETGUARD_SETUP(x, reg)
# define RETGUARD_CHECK(x, reg)
# define RETGUARD_PUSH(reg)
# define RETGUARD_POP(reg)
# define RETGUARD_SYMBOL(x)
#endif
#define ENTRY(y) _ENTRY(y); bti c; _PROF_PROLOGUE
#define ENTRY_NP(y) _ENTRY(y); bti c
#define ENTRY_NB(y) _ENTRY_NB(y); bti c; _PROF_PROLOGUE
#define ASENTRY(y) _ENTRY(y); bti c; _PROF_PROLOGUE
#define ASENTRY_NP(y) _ENTRY(y); bti c
#define END(y) .size y, . - y
#define EENTRY(sym) .globl sym; sym:
#define EEND(sym)
#ifdef __PIC__
#define PIC_SYM(x,y) x(y)
#else
#define PIC_SYM(x,y) x
#endif
#define STRONG_ALIAS(alias,sym) \
.global alias; \
alias = sym
#define WEAK_ALIAS(alias,sym) \
.weak alias; \
alias = sym
#endif /* !_MACHINE_ASM_H_ */

64
lib/libc/include/aarch64-openbsd-none/machine/atomic.h vendored Normal file
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/* $OpenBSD: atomic.h,v 1.4 2022/08/29 02:01:18 jsg Exp $ */
/* Public Domain */
#ifndef _MACHINE_ATOMIC_H_
#define _MACHINE_ATOMIC_H_
#define __membar(_f) do { __asm volatile(_f ::: "memory"); } while (0)
#define membar_enter() __membar("dmb sy")
#define membar_exit() __membar("dmb sy")
#define membar_producer() __membar("dmb st")
#define membar_consumer() __membar("dmb ld")
#define membar_sync() __membar("dmb sy")
#if defined(_KERNEL)
/* virtio needs MP membars even on SP kernels */
#define virtio_membar_producer() __membar("dmb st")
#define virtio_membar_consumer() __membar("dmb ld")
#define virtio_membar_sync() __membar("dmb sy")
/*
* Set bits
* *p = *p | v
*/
static inline void
atomic_setbits_int(volatile unsigned int *p, unsigned int v)
{
unsigned int modified, tmp;
__asm volatile (
"1: ldxr %w0, [%x3] \n\t"
" orr %w0, %w0, %w2 \n\t"
" stxr %w1, %w0, [%x3] \n\t"
" cbnz %w1, 1b \n\t"
: "=&r" (tmp), "=&r" (modified)
: "r" (v), "r" (p)
: "memory", "cc"
);
}
/*
* Clear bits
* *p = *p & (~v)
*/
static inline void
atomic_clearbits_int(volatile unsigned int *p, unsigned int v)
{
unsigned int modified, tmp;
__asm volatile (
"1: ldxr %w0, [%x3] \n\t"
" bic %w0, %w0, %w2 \n\t"
" stxr %w1, %w0, [%x3] \n\t"
" cbnz %w1, 1b \n\t"
: "=&r" (tmp), "=&r" (modified)
: "r" (v), "r" (p)
: "memory", "cc"
);
}
#endif /* defined(_KERNEL) */
#endif /* _MACHINE_ATOMIC_H_ */

47
lib/libc/include/aarch64-openbsd-none/machine/bootconfig.h vendored Normal file
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/* $OpenBSD: bootconfig.h,v 1.4 2023/12/05 05:27:26 jsg Exp $ */
/* $NetBSD: bootconfig.h,v 1.2 2001/06/21 22:08:28 chris Exp $ */
/*-
* Copyright (c) 2013 Andrew Turner <andrew@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD: head/sys/arm64/include/machdep.h 281494 2015-04-13 14:43:10Z andrew $
*/
#ifndef _MACHINE_BOOTCONFIG_H_
#define _MACHINE_BOOTCONFIG_H_
struct arm64_bootparams {
vaddr_t modulep;
vaddr_t kern_l1pt; /* L1 page table for the kernel */
uint64_t kern_delta;
vaddr_t kern_stack;
void *arg0; // passed to kernel in R0
void *arg1; // passed to kernel in R1
void *arg2; // passed to kernel in R2
};
void initarm(struct arm64_bootparams *);
#endif /* _MACHINE_BOOTCONFIG_H_ */

536
lib/libc/include/aarch64-openbsd-none/machine/bus.h vendored Normal file
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/* $OpenBSD: bus.h,v 1.11 2024/11/18 05:32:39 jsg Exp $ */
/*
* Copyright (c) 2003-2004 Opsycon AB Sweden. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _MACHINE_BUS_H_
#define _MACHINE_BUS_H_
#ifdef __STDC__
#define CAT(a,b) a##b
#define CAT3(a,b,c) a##b##c
#else
#define CAT(a,b) a/**/b
#define CAT3(a,b,c) a/**/b/**/c
#endif
/*
* Bus access types.
*/
struct bus_space;
typedef u_long bus_addr_t;
typedef u_long bus_size_t;
typedef u_long bus_space_handle_t;
typedef struct bus_space *bus_space_tag_t;
typedef struct bus_space bus_space_t;
struct bus_space {
bus_addr_t bus_base;
void *bus_private;
u_int8_t (*_space_read_1)(bus_space_tag_t , bus_space_handle_t,
bus_size_t);
void (*_space_write_1)(bus_space_tag_t , bus_space_handle_t,
bus_size_t, u_int8_t);
u_int16_t (*_space_read_2)(bus_space_tag_t , bus_space_handle_t,
bus_size_t);
void (*_space_write_2)(bus_space_tag_t , bus_space_handle_t,
bus_size_t, u_int16_t);
u_int32_t (*_space_read_4)(bus_space_tag_t , bus_space_handle_t,
bus_size_t);
void (*_space_write_4)(bus_space_tag_t , bus_space_handle_t,
bus_size_t, u_int32_t);
u_int64_t (*_space_read_8)(bus_space_tag_t , bus_space_handle_t,
bus_size_t);
void (*_space_write_8)(bus_space_tag_t , bus_space_handle_t,
bus_size_t, u_int64_t);
void (*_space_read_raw_2)(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, u_int8_t *, bus_size_t);
void (*_space_write_raw_2)(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, const u_int8_t *, bus_size_t);
void (*_space_read_raw_4)(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, u_int8_t *, bus_size_t);
void (*_space_write_raw_4)(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, const u_int8_t *, bus_size_t);
void (*_space_read_raw_8)(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, u_int8_t *, bus_size_t);
void (*_space_write_raw_8)(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, const u_int8_t *, bus_size_t);
int (*_space_map)(bus_space_tag_t , bus_addr_t,
bus_size_t, int, bus_space_handle_t *);
void (*_space_unmap)(bus_space_tag_t, bus_space_handle_t,
bus_size_t);
int (*_space_subregion)(bus_space_tag_t, bus_space_handle_t,
bus_size_t, bus_size_t, bus_space_handle_t *);
void * (*_space_vaddr)(bus_space_tag_t, bus_space_handle_t);
paddr_t (*_space_mmap)(bus_space_tag_t, bus_addr_t, off_t,
int, int);
};
#define bus_space_read_1(t, h, o) (*(t)->_space_read_1)((t), (h), (o))
#define bus_space_read_2(t, h, o) (*(t)->_space_read_2)((t), (h), (o))
#define bus_space_read_4(t, h, o) (*(t)->_space_read_4)((t), (h), (o))
#define bus_space_read_8(t, h, o) (*(t)->_space_read_8)((t), (h), (o))
#define bus_space_write_1(t, h, o, v) (*(t)->_space_write_1)((t), (h), (o), (v))
#define bus_space_write_2(t, h, o, v) (*(t)->_space_write_2)((t), (h), (o), (v))
#define bus_space_write_4(t, h, o, v) (*(t)->_space_write_4)((t), (h), (o), (v))
#define bus_space_write_8(t, h, o, v) (*(t)->_space_write_8)((t), (h), (o), (v))
#define bus_space_read_raw_2(t, h, o) \
(*(t)->_space_read_2)((t), (h), (o))
#define bus_space_read_raw_4(t, h, o) \
(*(t)->_space_read_4)((t), (h), (o))
#define bus_space_read_raw_8(t, h, o) \
(*(t)->_space_read_8)((t), (h), (o))
#define bus_space_write_raw_2(t, h, o, v) \
(*(t)->_space_write_2)((t), (h), (o), (v))
#define bus_space_write_raw_4(t, h, o, v) \
(*(t)->_space_write_4)((t), (h), (o), (v))
#define bus_space_write_raw_8(t, h, o, v) \
(*(t)->_space_write_8)((t), (h), (o), (v))
#define bus_space_read_raw_multi_2(t, h, a, b, l) \
(*(t)->_space_read_raw_2)((t), (h), (a), (b), (l))
#define bus_space_read_raw_multi_4(t, h, a, b, l) \
(*(t)->_space_read_raw_4)((t), (h), (a), (b), (l))
#define bus_space_read_raw_multi_8(t, h, a, b, l) \
(*(t)->_space_read_raw_8)((t), (h), (a), (b), (l))
#define bus_space_write_raw_multi_2(t, h, a, b, l) \
(*(t)->_space_write_raw_2)((t), (h), (a), (b), (l))
#define bus_space_write_raw_multi_4(t, h, a, b, l) \
(*(t)->_space_write_raw_4)((t), (h), (a), (b), (l))
#define bus_space_write_raw_multi_8(t, h, a, b, l) \
(*(t)->_space_write_raw_8)((t), (h), (a), (b), (l))
#define bus_space_map(t, o, s, c, p) (*(t)->_space_map)((t), (o), (s), (c), (p))
#define bus_space_unmap(t, h, s) (*(t)->_space_unmap)((t), (h), (s))
#define bus_space_subregion(t, h, o, s, p) \
(*(t)->_space_subregion)((t), (h), (o), (s), (p))
#define BUS_SPACE_MAP_CACHEABLE 0x01
#define BUS_SPACE_MAP_POSTED 0x02
#define BUS_SPACE_MAP_LINEAR 0x04
#define BUS_SPACE_MAP_PREFETCHABLE 0x08
extern bus_space_t arm64_bs_tag;
#define bus_space_vaddr(t, h) (*(t)->_space_vaddr)((t), (h))
#define bus_space_mmap(t, a, o, p, f) \
(*(t)->_space_mmap)((t), (a), (o), (p), (f))
/*----------------------------------------------------------------------------*/
#define bus_space_read_multi(n,m) \
static __inline void \
CAT(bus_space_read_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
bus_size_t o, CAT3(u_int,m,_t) *x, size_t cnt) \
{ \
while (cnt--) \
*x++ = CAT(bus_space_read_,n)(bst, bsh, o); \
}
bus_space_read_multi(1,8)
bus_space_read_multi(2,16)
bus_space_read_multi(4,32)
bus_space_read_multi(8,64)
/*----------------------------------------------------------------------------*/
#define bus_space_read_region(n,m) \
static __inline void \
CAT(bus_space_read_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
bus_addr_t ba, CAT3(u_int,m,_t) *x, size_t cnt) \
{ \
while (cnt--) { \
*x++ = CAT(bus_space_read_,n)(bst, bsh, ba); \
ba += (n); \
} \
}
bus_space_read_region(1,8)
bus_space_read_region(2,16)
bus_space_read_region(4,32)
bus_space_read_region(8,64)
/*----------------------------------------------------------------------------*/
#define bus_space_read_raw_region(n,m) \
static __inline void \
CAT(bus_space_read_raw_region_,n)(bus_space_tag_t bst, \
bus_space_handle_t bsh, \
bus_addr_t ba, u_int8_t *x, size_t cnt) \
{ \
cnt >>= ((n) >> 1); \
while (cnt--) { \
CAT(bus_space_read_raw_multi_,n)(bst, bsh, ba, x, (n)); \
ba += (n); \
x += (n); \
} \
}
bus_space_read_raw_region(2,16)
bus_space_read_raw_region(4,32)
bus_space_read_raw_region(8,64)
/*----------------------------------------------------------------------------*/
#define bus_space_write_multi(n,m) \
static __inline void \
CAT(bus_space_write_multi_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
bus_size_t o, const CAT3(u_int,m,_t) *x, size_t cnt) \
{ \
while (cnt--) \
CAT(bus_space_write_,n)(bst, bsh, o, *x++); \
}
bus_space_write_multi(1,8)
bus_space_write_multi(2,16)
bus_space_write_multi(4,32)
bus_space_write_multi(8,64)
/*----------------------------------------------------------------------------*/
#define bus_space_write_region(n,m) \
static __inline void \
CAT(bus_space_write_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
bus_addr_t ba, const CAT3(u_int,m,_t) *x, size_t cnt) \
{ \
while (cnt--) { \
CAT(bus_space_write_,n)(bst, bsh, ba, *x++); \
ba += (n); \
} \
}
bus_space_write_region(1,8)
bus_space_write_region(2,16)
bus_space_write_region(4,32)
bus_space_write_region(8,64)
/*----------------------------------------------------------------------------*/
#define bus_space_write_raw_region(n,m) \
static __inline void \
CAT(bus_space_write_raw_region_,n)(bus_space_tag_t bst, \
bus_space_handle_t bsh, \
bus_addr_t ba, const u_int8_t *x, size_t cnt) \
{ \
cnt >>= ((n) >> 1); \
while (cnt--) { \
CAT(bus_space_write_raw_multi_,n)(bst, bsh, ba, x, (n)); \
ba += (n); \
x += (n); \
} \
}
bus_space_write_raw_region(2,16)
bus_space_write_raw_region(4,32)
bus_space_write_raw_region(8,64)
/*----------------------------------------------------------------------------*/
#define bus_space_set_region(n,m) \
static __inline void \
CAT(bus_space_set_region_,n)(bus_space_tag_t bst, bus_space_handle_t bsh, \
bus_addr_t ba, CAT3(u_int,m,_t) x, size_t cnt) \
{ \
while (cnt--) { \
CAT(bus_space_write_,n)(bst, bsh, ba, x); \
ba += (n); \
} \
}
bus_space_set_region(1,8)
bus_space_set_region(2,16)
bus_space_set_region(4,32)
bus_space_set_region(8,64)
/*----------------------------------------------------------------------------*/
static __inline void
bus_space_copy_1(void *v, bus_space_handle_t h1, bus_size_t o1,
bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
{
char *s = (char *)(h1 + o1);
char *d = (char *)(h2 + o2);
while (c--)
*d++ = *s++;
}
static __inline void
bus_space_copy_2(void *v, bus_space_handle_t h1, bus_size_t o1,
bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
{
short *s = (short *)(h1 + o1);
short *d = (short *)(h2 + o2);
while (c--)
*d++ = *s++;
}
static __inline void
bus_space_copy_4(void *v, bus_space_handle_t h1, bus_size_t o1,
bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
{
int *s = (int *)(h1 + o1);
int *d = (int *)(h2 + o2);
while (c--)
*d++ = *s++;
}
static __inline void
bus_space_copy_8(void *v, bus_space_handle_t h1, bus_size_t o1,
bus_space_handle_t h2, bus_size_t o2, bus_size_t c)
{
int64_t *s = (int64_t *)(h1 + o1);
int64_t *d = (int64_t *)(h2 + o2);
while (c--)
*d++ = *s++;
}
/*----------------------------------------------------------------------------*/
/*
* Bus read/write barrier methods.
*
* void bus_space_barrier(bus_space_tag_t tag,
* bus_space_handle_t bsh, bus_size_t offset,
* bus_size_t len, int flags);
*
*/
static inline void
bus_space_barrier(bus_space_tag_t t, bus_space_handle_t h, bus_size_t offset,
bus_size_t length, int flags)
{
__asm__ volatile ("dsb sy" ::: "memory");
}
#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
#define BUS_DMA_WAITOK 0x0000
#define BUS_DMA_NOWAIT 0x0001
#define BUS_DMA_ALLOCNOW 0x0002
#define BUS_DMA_COHERENT 0x0008
#define BUS_DMA_BUS1 0x0010 /* placeholders for bus functions... */
#define BUS_DMA_BUS2 0x0020
#define BUS_DMA_BUS3 0x0040
#define BUS_DMA_BUS4 0x0080
#define BUS_DMA_READ 0x0100 /* mapping is device -> memory only */
#define BUS_DMA_WRITE 0x0200 /* mapping is memory -> device only */
#define BUS_DMA_STREAMING 0x0400 /* hint: sequential, unidirectional */
#define BUS_DMA_ZERO 0x0800 /* zero memory in dmamem_alloc */
#define BUS_DMA_NOCACHE 0x1000
#define BUS_DMA_64BIT 0x2000 /* device handles 64bit dva */
#define BUS_DMA_FIXED 0x4000 /* place mapping at specified dva */
/* Forwards needed by prototypes below. */
struct mbuf;
struct proc;
struct uio;
#define BUS_DMASYNC_POSTREAD 0x0001
#define BUS_DMASYNC_POSTWRITE 0x0002
#define BUS_DMASYNC_PREREAD 0x0004
#define BUS_DMASYNC_PREWRITE 0x0008
typedef struct machine_bus_dma_tag *bus_dma_tag_t;
typedef struct machine_bus_dmamap *bus_dmamap_t;
/*
* bus_dma_segment_t
*
* Describes a single contiguous DMA transaction. Values
* are suitable for programming into DMA registers.
*/
struct machine_bus_dma_segment {
bus_addr_t ds_addr; /* DMA address */
bus_size_t ds_len; /* length of transfer */
paddr_t _ds_paddr; /* CPU address */
vaddr_t _ds_vaddr; /* CPU address */
};
typedef struct machine_bus_dma_segment bus_dma_segment_t;
/*
* bus_dma_tag_t
*
* A machine-dependent opaque type describing the implementation of
* DMA for a given bus.
*/
struct machine_bus_dma_tag {
void *_cookie; /* cookie used in the guts */
int _flags; /* misc. flags */
/*
* DMA mapping methods.
*/
int (*_dmamap_create)(bus_dma_tag_t , bus_size_t, int,
bus_size_t, bus_size_t, int, bus_dmamap_t *);
void (*_dmamap_destroy)(bus_dma_tag_t , bus_dmamap_t);
int (*_dmamap_load)(bus_dma_tag_t , bus_dmamap_t, void *,
bus_size_t, struct proc *, int);
int (*_dmamap_load_mbuf)(bus_dma_tag_t , bus_dmamap_t,
struct mbuf *, int);
int (*_dmamap_load_uio)(bus_dma_tag_t , bus_dmamap_t,
struct uio *, int);
int (*_dmamap_load_raw)(bus_dma_tag_t , bus_dmamap_t,
bus_dma_segment_t *, int, bus_size_t, int);
int (*_dmamap_load_buffer)(bus_dma_tag_t, bus_dmamap_t, void *,
bus_size_t, struct proc *, int, paddr_t *, int *, int);
void (*_dmamap_unload)(bus_dma_tag_t , bus_dmamap_t);
void (*_dmamap_sync)(bus_dma_tag_t , bus_dmamap_t,
bus_addr_t, bus_size_t, int);
/*
* DMA memory utility functions.
*/
int (*_dmamem_alloc)(bus_dma_tag_t, bus_size_t, bus_size_t,
bus_size_t, bus_dma_segment_t *, int, int *, int);
int (*_dmamem_alloc_range)(bus_dma_tag_t, bus_size_t, bus_size_t,
bus_size_t, bus_dma_segment_t *, int, int *, int,
bus_addr_t, bus_addr_t);
void (*_dmamem_free)(bus_dma_tag_t, bus_dma_segment_t *, int);
int (*_dmamem_map)(bus_dma_tag_t, bus_dma_segment_t *,
int, size_t, caddr_t *, int);
void (*_dmamem_unmap)(bus_dma_tag_t, caddr_t, size_t);
paddr_t (*_dmamem_mmap)(bus_dma_tag_t, bus_dma_segment_t *,
int, off_t, int, int);
/*
* internal memory address translation information.
*/
bus_addr_t _dma_mask;
};
#define bus_dmamap_create(t, s, n, m, b, f, p) \
(*(t)->_dmamap_create)((t), (s), (n), (m), (b), (f), (p))
#define bus_dmamap_destroy(t, p) \
(*(t)->_dmamap_destroy)((t), (p))
#define bus_dmamap_load(t, m, b, s, p, f) \
(*(t)->_dmamap_load)((t), (m), (b), (s), (p), (f))
#define bus_dmamap_load_mbuf(t, m, b, f) \
(*(t)->_dmamap_load_mbuf)((t), (m), (b), (f))
#define bus_dmamap_load_uio(t, m, u, f) \
(*(t)->_dmamap_load_uio)((t), (m), (u), (f))
#define bus_dmamap_load_raw(t, m, sg, n, s, f) \
(*(t)->_dmamap_load_raw)((t), (m), (sg), (n), (s), (f))
#define bus_dmamap_unload(t, p) \
(*(t)->_dmamap_unload)((t), (p))
#define bus_dmamap_sync(t, p, a, l, o) \
(void)((t)->_dmamap_sync ? \
(*(t)->_dmamap_sync)((t), (p), (a), (l), (o)) : (void)0)
#define bus_dmamem_alloc(t, s, a, b, sg, n, r, f) \
(*(t)->_dmamem_alloc)((t), (s), (a), (b), (sg), (n), (r), (f))
#define bus_dmamem_alloc_range(t, s, a, b, sg, n, r, f, l, h) \
(*(t)->_dmamem_alloc_range)((t), (s), (a), (b), (sg), \
(n), (r), (f), (l), (h))
#define bus_dmamem_free(t, sg, n) \
(*(t)->_dmamem_free)((t), (sg), (n))
#define bus_dmamem_map(t, sg, n, s, k, f) \
(*(t)->_dmamem_map)((t), (sg), (n), (s), (k), (f))
#define bus_dmamem_unmap(t, k, s) \
(*(t)->_dmamem_unmap)((t), (k), (s))
#define bus_dmamem_mmap(t, sg, n, o, p, f) \
(*(t)->_dmamem_mmap)((t), (sg), (n), (o), (p), (f))
int _dmamap_create(bus_dma_tag_t, bus_size_t, int,
bus_size_t, bus_size_t, int, bus_dmamap_t *);
void _dmamap_destroy(bus_dma_tag_t, bus_dmamap_t);
int _dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *,
bus_size_t, struct proc *, int);
int _dmamap_load_mbuf(bus_dma_tag_t, bus_dmamap_t, struct mbuf *, int);
int _dmamap_load_uio(bus_dma_tag_t, bus_dmamap_t, struct uio *, int);
int _dmamap_load_raw(bus_dma_tag_t, bus_dmamap_t,
bus_dma_segment_t *, int, bus_size_t, int);
int _dmamap_load_buffer(bus_dma_tag_t, bus_dmamap_t, void *,
bus_size_t, struct proc *, int, paddr_t *, int *, int);
void _dmamap_unload(bus_dma_tag_t, bus_dmamap_t);
void _dmamap_sync(bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
bus_size_t, int);
int _dmamem_alloc(bus_dma_tag_t, bus_size_t, bus_size_t,
bus_size_t, bus_dma_segment_t *, int, int *, int);
void _dmamem_free(bus_dma_tag_t, bus_dma_segment_t *, int);
int _dmamem_map(bus_dma_tag_t, bus_dma_segment_t *,
int, size_t, caddr_t *, int);
void _dmamem_unmap(bus_dma_tag_t, caddr_t, size_t);
paddr_t _dmamem_mmap(bus_dma_tag_t, bus_dma_segment_t *, int, off_t, int, int);
int _dmamem_alloc_range(bus_dma_tag_t, bus_size_t, bus_size_t, bus_size_t,
bus_dma_segment_t *, int, int *, int, paddr_t, paddr_t);
/*
* bus_dmamap_t
*
* Describes a DMA mapping.
*/
struct machine_bus_dmamap {
/*
* PRIVATE MEMBERS: not for use by machine-independent code.
*/
bus_size_t _dm_size; /* largest DMA transfer mappable */
int _dm_segcnt; /* number of segs this map can map */
bus_size_t _dm_maxsegsz; /* largest possible segment */
bus_size_t _dm_boundary; /* don't cross this */
int _dm_flags; /* misc. flags */
void *_dm_cookie; /* cookie for bus-specific functions */
/*
* PUBLIC MEMBERS: these are used by machine-independent code.
*/
bus_size_t dm_mapsize; /* size of the mapping */
int dm_nsegs; /* # valid segments in mapping */
bus_dma_segment_t dm_segs[1]; /* segments; variable length */
};
int generic_space_map(bus_space_tag_t, bus_addr_t, bus_size_t, int,
bus_space_handle_t *);
void generic_space_unmap(bus_space_tag_t, bus_space_handle_t, bus_size_t);
int generic_space_region(bus_space_tag_t, bus_space_handle_t, bus_size_t,
bus_size_t, bus_space_handle_t *);
void *generic_space_vaddr(bus_space_tag_t, bus_space_handle_t);
paddr_t generic_space_mmap(bus_space_tag_t, bus_addr_t, off_t, int, int);
uint8_t generic_space_read_1(bus_space_tag_t, bus_space_handle_t, bus_size_t);
uint16_t generic_space_read_2(bus_space_tag_t, bus_space_handle_t, bus_size_t);
uint32_t generic_space_read_4(bus_space_tag_t, bus_space_handle_t, bus_size_t);
uint64_t generic_space_read_8(bus_space_tag_t, bus_space_handle_t, bus_size_t);
void generic_space_read_raw_2(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, uint8_t *, bus_size_t);
void generic_space_write_1(bus_space_tag_t, bus_space_handle_t, bus_size_t,
uint8_t);
void generic_space_write_2(bus_space_tag_t, bus_space_handle_t, bus_size_t,
uint16_t);
void generic_space_write_4(bus_space_tag_t, bus_space_handle_t, bus_size_t,
uint32_t);
void generic_space_write_8(bus_space_tag_t, bus_space_handle_t, bus_size_t,
uint64_t);
void generic_space_write_raw_2(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, const uint8_t *, bus_size_t);
void generic_space_read_raw_4(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, uint8_t *, bus_size_t);
void generic_space_write_raw_4(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, const uint8_t *, bus_size_t);
void generic_space_read_raw_8(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, uint8_t *, bus_size_t);
void generic_space_write_raw_8(bus_space_tag_t, bus_space_handle_t,
bus_addr_t, const uint8_t *, bus_size_t);
#endif /* _MACHINE_BUS_H_ */

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/* $OpenBSD: cdefs.h,v 1.1 2016/12/17 23:38:33 patrick Exp $ */
#ifndef _MACHINE_CDEFS_H_
#define _MACHINE_CDEFS_H_
#define __strong_alias(alias,sym) \
__asm__(".global " __STRING(alias) " ; " __STRING(alias) \
" = " __STRING(sym))
#define __weak_alias(alias,sym) \
__asm__(".weak " __STRING(alias) " ; " __STRING(alias) \
" = " __STRING(sym))
#define __warn_references(sym,msg) \
__asm__(".section .gnu.warning." __STRING(sym) \
" ; .ascii \"" msg "\" ; .text")
#endif /* !_MACHINE_CDEFS_H_ */

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/* $OpenBSD: conf.h,v 1.5 2024/06/12 02:50:25 jsg Exp $ */
/* $NetBSD: conf.h,v 1.2 1996/05/05 19:28:34 christos Exp $ */
/*
* Copyright (c) 1996 Christos Zoulas. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by Christos Zoulas.
* 4. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _MACHINE_CONF_H_
#define _MACHINE_CONF_H_
#include <sys/conf.h>
#define mmread mmrw
#define mmwrite mmrw
cdev_decl(mm);
/* open, close, ioctl */
#define cdev_openprom_init(c,n) { \
dev_init(c,n,open), dev_init(c,n,close), (dev_type_read((*))) enodev, \
(dev_type_write((*))) enodev, dev_init(c,n,ioctl), \
(dev_type_stop((*))) nullop, 0, \
(dev_type_mmap((*))) enodev }
cdev_decl(openprom);
/* open, close, write, ioctl, kqueue */
#define cdev_acpiapm_init(c,n) { \
dev_init(c,n,open), dev_init(c,n,close), (dev_type_read((*))) enodev, \
(dev_type_write((*))) enodev, dev_init(c,n,ioctl), \
(dev_type_stop((*))) enodev, 0, \
(dev_type_mmap((*))) enodev, 0, 0, dev_init(c,n,kqfilter) }
cdev_decl(apm);
cdev_decl(acpiapm);
#endif /* _MACHINE_CONF_H_ */

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/* $OpenBSD: cpu.h,v 1.51 2025/02/11 22:27:09 kettenis Exp $ */
/*
* Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_CPU_H_
#define _MACHINE_CPU_H_
/*
* User-visible definitions
*/
/*
* CTL_MACHDEP definitions.
*/
#define CPU_COMPATIBLE 1 /* compatible property */
#define CPU_ID_AA64ISAR0 2
#define CPU_ID_AA64ISAR1 3
#define CPU_ID_AA64ISAR2 4
#define CPU_ID_AA64MMFR0 5
#define CPU_ID_AA64MMFR1 6
#define CPU_ID_AA64MMFR2 7
#define CPU_ID_AA64PFR0 8
#define CPU_ID_AA64PFR1 9
#define CPU_ID_AA64SMFR0 10
#define CPU_ID_AA64ZFR0 11
#define CPU_LIDACTION 12
#define CPU_MAXID 13 /* number of valid machdep ids */
#define CTL_MACHDEP_NAMES { \
{ 0, 0 }, \
{ "compatible", CTLTYPE_STRING }, \
{ "id_aa64isar0", CTLTYPE_QUAD }, \
{ "id_aa64isar1", CTLTYPE_QUAD }, \
{ "id_aa64isar2", CTLTYPE_QUAD }, \
{ "id_aa64mmfr0", CTLTYPE_QUAD }, \
{ "id_aa64mmfr1", CTLTYPE_QUAD }, \
{ "id_aa64mmfr2", CTLTYPE_QUAD }, \
{ "id_aa64pfr0", CTLTYPE_QUAD }, \
{ "id_aa64pfr1", CTLTYPE_QUAD }, \
{ "id_aa64smfr0", CTLTYPE_QUAD }, \
{ "id_aa64zfr0", CTLTYPE_QUAD }, \
{ "lidaction", CTLTYPE_INT }, \
}
#ifdef _KERNEL
/*
* Kernel-only definitions
*/
extern uint64_t cpu_id_aa64isar0;
extern uint64_t cpu_id_aa64isar1;
extern uint64_t cpu_id_aa64isar2;
extern uint64_t cpu_id_aa64mmfr0;
extern uint64_t cpu_id_aa64mmfr1;
extern uint64_t cpu_id_aa64mmfr2;
extern uint64_t cpu_id_aa64pfr0;
extern uint64_t cpu_id_aa64pfr1;
extern uint64_t cpu_id_aa64zfr0;
void cpu_identify_cleanup(void);
#include <machine/intr.h>
#include <machine/frame.h>
#include <machine/armreg.h>
/* All the CLKF_* macros take a struct clockframe * as an argument. */
#define clockframe trapframe
/*
* CLKF_USERMODE: Return TRUE/FALSE (1/0) depending on whether the
* frame came from USR mode or not.
*/
#define CLKF_USERMODE(frame) ((frame->tf_elr & (1ul << 63)) == 0)
/*
* CLKF_INTR: True if we took the interrupt from inside another
* interrupt handler.
*/
#define CLKF_INTR(frame) (curcpu()->ci_idepth > 1)
/*
* CLKF_PC: Extract the program counter from a clockframe
*/
#define CLKF_PC(frame) (frame->tf_elr)
/*
* PROC_PC: Find out the program counter for the given process.
*/
#define PROC_PC(p) ((p)->p_addr->u_pcb.pcb_tf->tf_elr)
#define PROC_STACK(p) ((p)->p_addr->u_pcb.pcb_tf->tf_sp)
/*
* Per-CPU information. For now we assume one CPU.
*/
#include <sys/clockintr.h>
#include <sys/device.h>
#include <sys/sched.h>
#include <sys/srp.h>
#include <uvm/uvm_percpu.h>
struct cpu_info {
struct device *ci_dev; /* Device corresponding to this CPU */
struct cpu_info *ci_next;
struct schedstate_percpu ci_schedstate; /* scheduler state */
u_int32_t ci_cpuid;
uint64_t ci_mpidr;
uint64_t ci_midr;
u_int ci_acpi_proc_id;
int ci_node;
struct cpu_info *ci_self;
#define __HAVE_CPU_TOPOLOGY
u_int32_t ci_smt_id;
u_int32_t ci_core_id;
u_int32_t ci_pkg_id;
struct proc *ci_curproc;
struct pcb *ci_curpcb;
struct pmap *ci_curpm;
u_int32_t ci_randseed;
u_int32_t ci_ctrl; /* The CPU control register */
u_int64_t ci_trampoline_vectors;
uint32_t ci_cpl;
uint32_t ci_ipending;
uint32_t ci_idepth;
#ifdef DIAGNOSTIC
int ci_mutex_level;
#endif
int ci_want_resched;
void (*ci_flush_bp)(void);
void (*ci_serror)(void);
uint64_t ci_ttbr1;
vaddr_t ci_el1_stkend;
uint32_t ci_psci_idle_latency;
uint32_t ci_psci_idle_param;
uint32_t ci_psci_suspend_param;
struct opp_table *ci_opp_table;
volatile int ci_opp_idx;
volatile int ci_opp_max;
uint32_t ci_cpu_supply;
u_long ci_prev_sleep;
u_long ci_last_itime;
#ifdef MULTIPROCESSOR
struct srp_hazard ci_srp_hazards[SRP_HAZARD_NUM];
#define __HAVE_UVM_PERCPU
struct uvm_pmr_cache ci_uvm;
volatile int ci_flags;
volatile int ci_ddb_paused;
#define CI_DDB_RUNNING 0
#define CI_DDB_SHOULDSTOP 1
#define CI_DDB_STOPPED 2
#define CI_DDB_ENTERDDB 3
#define CI_DDB_INDDB 4
#endif
#ifdef GPROF
struct gmonparam *ci_gmon;
struct clockintr ci_gmonclock;
#endif
struct clockqueue ci_queue;
char ci_panicbuf[512];
};
#define CPUF_PRIMARY (1<<0)
#define CPUF_AP (1<<1)
#define CPUF_IDENTIFY (1<<2)
#define CPUF_IDENTIFIED (1<<3)
#define CPUF_PRESENT (1<<4)
#define CPUF_GO (1<<5)
#define CPUF_RUNNING (1<<6)
static inline struct cpu_info *
curcpu(void)
{
struct cpu_info *__ci = NULL;
__asm volatile("mrs %0, tpidr_el1" : "=r" (__ci));
return (__ci);
}
extern struct cpu_info cpu_info_primary;
extern struct cpu_info *cpu_info_list;
#ifndef MULTIPROCESSOR
#define cpu_number() 0
#define CPU_IS_PRIMARY(ci) 1
#define CPU_IS_RUNNING(ci) 1
#define CPU_INFO_ITERATOR int
#define CPU_INFO_FOREACH(cii, ci) \
for (cii = 0, ci = curcpu(); ci != NULL; ci = NULL)
#define CPU_INFO_UNIT(ci) 0
#define MAXCPUS 1
#define cpu_unidle(ci)
#else
#define cpu_number() (curcpu()->ci_cpuid)
#define CPU_IS_PRIMARY(ci) ((ci) == &cpu_info_primary)
#define CPU_IS_RUNNING(ci) ((ci)->ci_flags & CPUF_RUNNING)
#define CPU_INFO_ITERATOR int
#define CPU_INFO_FOREACH(cii, ci) for (cii = 0, ci = cpu_info_list; \
ci != NULL; ci = ci->ci_next)
#define CPU_INFO_UNIT(ci) ((ci)->ci_dev ? (ci)->ci_dev->dv_unit : 0)
#define MAXCPUS 256
extern struct cpu_info *cpu_info[MAXCPUS];
void cpu_boot_secondary_processors(void);
#endif /* !MULTIPROCESSOR */
#define CPU_BUSY_CYCLE() __asm volatile("yield" : : : "memory")
#define curpcb curcpu()->ci_curpcb
static inline unsigned int
cpu_rnd_messybits(void)
{
uint64_t val, rval;
__asm volatile("mrs %0, CNTVCT_EL0; rbit %1, %0;"
: "=r" (val), "=r" (rval));
return (val ^ rval);
}
/*
* Scheduling glue
*/
#define aston(p) ((p)->p_md.md_astpending = 1)
#define setsoftast() aston(curcpu()->ci_curproc)
/*
* Notify the current process (p) that it has a signal pending,
* process as soon as possible.
*/
#ifdef MULTIPROCESSOR
void cpu_unidle(struct cpu_info *ci);
#define signotify(p) (aston(p), cpu_unidle((p)->p_cpu))
void cpu_kick(struct cpu_info *);
#else
#define cpu_kick(ci)
#define cpu_unidle(ci)
#define signotify(p) setsoftast()
#endif
/*
* Preempt the current process if in interrupt from user mode,
* or after the current trap/syscall if in system mode.
*/
void need_resched(struct cpu_info *);
#define clear_resched(ci) ((ci)->ci_want_resched = 0)
/*
* Give a profiling tick to the current process when the user profiling
* buffer pages are invalid. On the i386, request an ast to send us
* through trap(), marking the proc as needing a profiling tick.
*/
#define need_proftick(p) aston(p)
// asm code to start new kernel contexts.
void proc_trampoline(void);
/*
* Random cruft
*/
void dumpconf(void);
// syscall.c
void svc_handler (trapframe_t *);
// functions to manipulate interrupt state
static __inline void
restore_daif(uint32_t daif)
{
__asm volatile ("msr daif, %x0":: "r"(daif));
}
static __inline void
enable_irq_daif(void)
{
__asm volatile ("msr daifclr, #3");
}
static __inline void
disable_irq_daif(void)
{
__asm volatile ("msr daifset, #3");
}
static __inline uint32_t
disable_irq_daif_ret(void)
{
uint32_t daif;
__asm volatile ("mrs %x0, daif": "=r"(daif));
__asm volatile ("msr daifset, #3");
return daif;
}
static inline void
intr_enable(void)
{
enable_irq_daif();
}
static inline u_long
intr_disable(void)
{
return disable_irq_daif_ret();
}
static inline void
intr_restore(u_long daif)
{
restore_daif(daif);
}
void cpu_halt(void);
int cpu_suspend_primary(void);
void cpu_resume_secondary(struct cpu_info *);
extern void (*cpu_idle_cycle_fcn)(void);
extern void (*cpu_suspend_cycle_fcn)(void);
void cpu_wfi(void);
void delay (unsigned);
#define DELAY(x) delay(x)
#endif /* _KERNEL */
#ifdef MULTIPROCESSOR
#include <sys/mplock.h>
#endif /* MULTIPROCESSOR */
#endif /* !_MACHINE_CPU_H_ */

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/* $OpenBSD: cpufunc.h,v 1.4 2018/05/02 15:17:30 patrick Exp $ */
/*-
* Copyright (c) 2014 Andrew Turner
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD: head/sys/cpu/include/cpufunc.h 299683 2016-05-13 16:03:50Z andrew $
*/
#ifndef _MACHINE_CPUFUNC_H_
#define _MACHINE_CPUFUNC_H_
#ifdef _KERNEL
#include <machine/armreg.h>
extern int64_t dcache_line_size;
extern int64_t icache_line_size;
extern int64_t idcache_line_size;
extern int64_t dczva_line_size;
void cpu_setttb(int, paddr_t);
void cpu_tlb_flush(void);
void cpu_tlb_flush_asid(vaddr_t);
void cpu_tlb_flush_all_asid(vaddr_t);
void cpu_tlb_flush_asid_all(vaddr_t);
void cpu_icache_sync_range(vaddr_t, vsize_t);
void cpu_idcache_wbinv_range(vaddr_t, vsize_t);
void cpu_dcache_wbinv_range(vaddr_t, vsize_t);
void cpu_dcache_inv_range(vaddr_t, vsize_t);
void cpu_dcache_wb_range(vaddr_t, vsize_t);
register_t smc_call(register_t, register_t, register_t, register_t);
#endif /* _KERNEL */
#endif /* _MACHINE_CPUFUNC_H_ */

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/* $OpenBSD: db_machdep.h,v 1.8 2025/07/22 09:20:41 kettenis Exp $ */
/* $NetBSD: db_machdep.h,v 1.5 2001/11/22 18:00:00 thorpej Exp $ */
/*
* Copyright (c) 1996 Scott K Stevens
*
* Mach Operating System
* Copyright (c) 1991,1990 Carnegie Mellon University
* All Rights Reserved.
*
* Permission to use, copy, modify and distribute this software and its
* documentation is hereby granted, provided that both the copyright
* notice and this permission notice appear in all copies of the
* software, derivative works or modified versions, and any portions
* thereof, and that both notices appear in supporting documentation.
*
* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR
* ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
*
* Carnegie Mellon requests users of this software to return to
*
* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
* School of Computer Science
* Carnegie Mellon University
* Pittsburgh PA 15213-3890
*
* any improvements or extensions that they make and grant Carnegie Mellon
* the rights to redistribute these changes.
*/
#ifndef _MACHINE_DB_MACHDEP_H_
#define _MACHINE_DB_MACHDEP_H_
/*
* Machine-dependent defines for new kernel debugger.
*/
#include <sys/param.h>
#include <uvm/uvm_extern.h>
#include <machine/armreg.h>
#include <machine/frame.h>
/* end of mangling */
typedef long db_expr_t; /* expression - signed */
typedef trapframe_t db_regs_t;
extern db_regs_t ddb_regs; /* register state */
#define DDB_REGS (&ddb_regs)
#define PC_REGS(regs) ((vaddr_t)(regs)->tf_elr)
#define SET_PC_REGS(regs, value) (regs)->tf_elr = (register_t)(value)
#define BKPT_INST 0xd4200000 /* breakpoint instruction */
#define BKPT_SIZE (INSN_SIZE) /* size of breakpoint inst */
#define BKPT_SET(inst) (BKPT_INST)
#define db_clear_single_step(regs) ((regs)->tf_spsr &= ~PSR_SS)
#define db_set_single_step(regs) ((regs)->tf_spsr |= PSR_SS)
#define IS_BREAKPOINT_TRAP(type, code) ((type) == EXCP_BRK)
#define IS_WATCHPOINT_TRAP(type, code) ((type) == EXCP_WATCHPT_EL1)
// ALL BROKEN!!!
#define inst_trap_return(ins) ((ins) == 0 && (ins) == 1)
#define inst_return(ins) ((ins) == 0 && (ins) == 1)
#define inst_call(ins) ((ins) == 0 && (ins) == 1)
#define DB_MACHINE_COMMANDS
int db_ktrap(int, db_regs_t *);
void db_machine_init (void);
#define DDB_STATE_NOT_RUNNING 0
#define DDB_STATE_RUNNING 1
#define DDB_STATE_EXITING 2
#endif /* _MACHINE_DB_MACHDEP_H_ */

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/* $OpenBSD: disklabel.h,v 1.1 2016/12/17 23:38:33 patrick Exp $ */
/*
* Copyright (c) 2014 Patrick Wildt <patrick@blueri.se>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_DISKLABEL_H_
#define _MACHINE_DISKLABEL_H_
#define LABELSECTOR 1 /* sector containing label */
#define LABELOFFSET 0 /* offset of label in sector */
#define MAXPARTITIONS 16 /* number of partitions */
#endif /* _MACHINE_DISKLABEL_H_ */

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/* $OpenBSD: efivar.h,v 1.2 2024/07/10 10:53:55 kettenis Exp $ */
/*
* Copyright (c) 2022 Mark Kettenis <kettenis@openbsd.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_EFIVAR_H_
#define _MACHINE_EFIVAR_H_
#include <dev/clock_subr.h>
struct efi_softc {
struct device sc_dev;
struct pmap *sc_pm;
EFI_RUNTIME_SERVICES *sc_rs;
EFI_SYSTEM_RESOURCE_TABLE *sc_esrt;
u_long sc_psw;
struct todr_chip_handle sc_todr;
};
extern EFI_GET_VARIABLE efi_get_variable;
extern EFI_SET_VARIABLE efi_set_variable;
extern EFI_GET_NEXT_VARIABLE_NAME efi_get_next_variable_name;
void efi_enter(struct efi_softc *);
void efi_leave(struct efi_softc *);
extern label_t efi_jmpbuf;
#define efi_enter_check(sc) (setjmp(&efi_jmpbuf) ? \
(efi_leave(sc), EFAULT) : (efi_enter(sc), 0))
#endif /* _MACHINE_EFIVAR_H_ */

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/*-
* Copyright (c) 1996-1997 John D. Polstra.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE_ELF_H_
#define _MACHINE_ELF_H_
/*
* ELF definitions for the AArch64 architecture.
*/
#ifdef _KERNEL
# define __HAVE_CPU_HWCAP
# define __HAVE_CPU_HWCAP2
extern unsigned long hwcap, hwcap2;
#endif /* _KERNEL */
/* HWCAP */
#define HWCAP_FP 0x00000001
#define HWCAP_ASIMD 0x00000002
#define HWCAP_EVTSTRM 0x00000004
#define HWCAP_AES 0x00000008
#define HWCAP_PMULL 0x00000010
#define HWCAP_SHA1 0x00000020
#define HWCAP_SHA2 0x00000040
#define HWCAP_CRC32 0x00000080
#define HWCAP_ATOMICS 0x00000100
#define HWCAP_FPHP 0x00000200
#define HWCAP_ASIMDHP 0x00000400
#define HWCAP_CPUID 0x00000800
#define HWCAP_ASIMDRDM 0x00001000
#define HWCAP_JSCVT 0x00002000
#define HWCAP_FCMA 0x00004000
#define HWCAP_LRCPC 0x00008000
#define HWCAP_DCPOP 0x00010000
#define HWCAP_SHA3 0x00020000
#define HWCAP_SM3 0x00040000
#define HWCAP_SM4 0x00080000
#define HWCAP_ASIMDDP 0x00100000
#define HWCAP_SHA512 0x00200000
#define HWCAP_SVE 0x00400000
#define HWCAP_ASIMDFHM 0x00800000
#define HWCAP_DIT 0x01000000
#define HWCAP_USCAT 0x02000000
#define HWCAP_ILRCPC 0x04000000
#define HWCAP_FLAGM 0x08000000
#define HWCAP_SSBS 0x10000000
#define HWCAP_SB 0x20000000
#define HWCAP_PACA 0x40000000
#define HWCAP_PACG 0x80000000
/* HWCAP2 */
#define HWCAP2_DCPODP 0x0000000000000001ul
#define HWCAP2_SVE2 0x0000000000000002ul
#define HWCAP2_SVEAES 0x0000000000000004ul
#define HWCAP2_SVEPMULL 0x0000000000000008ul
#define HWCAP2_SVEBITPERM 0x0000000000000010ul
#define HWCAP2_SVESHA3 0x0000000000000020ul
#define HWCAP2_SVESM4 0x0000000000000040ul
#define HWCAP2_FLAGM2 0x0000000000000080ul
#define HWCAP2_FRINT 0x0000000000000100ul
#define HWCAP2_SVEI8MM 0x0000000000000200ul
#define HWCAP2_SVEF32MM 0x0000000000000400ul
#define HWCAP2_SVEF64MM 0x0000000000000800ul
#define HWCAP2_SVEBF16 0x0000000000001000ul
#define HWCAP2_I8MM 0x0000000000002000ul
#define HWCAP2_BF16 0x0000000000004000ul
#define HWCAP2_DGH 0x0000000000008000ul
#define HWCAP2_RNG 0x0000000000010000ul
#define HWCAP2_BTI 0x0000000000020000ul
#define HWCAP2_MTE 0x0000000000040000ul
#define HWCAP2_ECV 0x0000000000080000ul
#define HWCAP2_AFP 0x0000000000100000ul
#define HWCAP2_RPRES 0x0000000000200000ul
#define HWCAP2_MTE3 0x0000000000400000ul
#define HWCAP2_SME 0x0000000000800000ul
#define HWCAP2_SME_I16I64 0x0000000001000000ul
#define HWCAP2_SME_F64F64 0x0000000002000000ul
#define HWCAP2_SME_I8I32 0x0000000004000000ul
#define HWCAP2_SME_F16F32 0x0000000008000000ul
#define HWCAP2_SME_B16F32 0x0000000010000000ul
#define HWCAP2_SME_F32F32 0x0000000020000000ul
#define HWCAP2_SME_FA64 0x0000000040000000ul
#define HWCAP2_WFXT 0x0000000080000000ul
#define HWCAP2_EBF16 0x0000000100000000ul
#define HWCAP2_SVE_EBF16 0x0000000200000000ul
#define HWCAP2_CSSC 0x0000000400000000ul
#define HWCAP2_RPRFM 0x0000000800000000ul
#define HWCAP2_SVE2P1 0x0000001000000000ul
#define HWCAP2_SME2 0x0000002000000000ul
#define HWCAP2_SME2P1 0x0000004000000000ul
#define HWCAP2_SME_I16I32 0x0000008000000000ul
#define HWCAP2_SME_BI32I32 0x0000010000000000ul
#define HWCAP2_SME_B16B16 0x0000020000000000ul
#define HWCAP2_SME_F16F16 0x0000040000000000ul
#define HWCAP2_MOPS 0x0000080000000000ul
#define HWCAP2_HBC 0x0000100000000000ul
#endif /* !_MACHINE_ELF_H_ */

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/* $OpenBSD: endian.h,v 1.4 2024/05/07 14:26:48 naddy Exp $ */
/*
* Copyright (c) 2015 David Gwynne <dlg@openbsd.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_ENDIAN_H_
#define _MACHINE_ENDIAN_H_
#define _BYTE_ORDER _LITTLE_ENDIAN
#define __STRICT_ALIGNMENT
#ifndef __FROM_SYS__ENDIAN
#include <sys/endian.h>
#endif
#endif /* _MACHINE_ENDIAN_H_ */

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/* $OpenBSD: exec.h,v 1.3 2025/07/31 16:09:59 kettenis Exp $ */
/*
* Copyright (c) 2014 Patrick Wildt <patrick@blueri.se>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_EXEC_H_
#define _MACHINE_EXEC_H_
#define __LDPGSZ 4096
#define ARCH_ELFSIZE 64
#define ELF_TARG_CLASS ELFCLASS64
#define ELF_TARG_DATA ELFDATA2LSB
#define ELF_TARG_MACH EM_AARCH64
#ifdef _KERNEL
#define __HAVE_COREDUMP_NOTE_ELF_MD
#endif
#endif

59
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/* $OpenBSD: fdt.h,v 1.7 2020/07/14 15:34:14 patrick Exp $ */
/*
* Copyright (c) 2016 Patrick Wildt <patrick@blueri.se>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __ARM_FDT_H__
#define __ARM_FDT_H__
#define _ARM32_BUS_DMA_PRIVATE
#include <machine/bus.h>
struct fdt_attach_args {
const char *fa_name;
int fa_node;
bus_space_tag_t fa_iot;
bus_dma_tag_t fa_dmat;
struct fdt_reg *fa_reg;
int fa_nreg;
uint32_t *fa_intr;
int fa_nintr;
int fa_acells;
int fa_scells;
};
extern int stdout_node;
extern int stdout_speed;
extern bus_space_tag_t fdt_cons_bs_tag;
void *fdt_find_cons(const char *);
#define fdt_intr_enable arm_intr_enable
#define fdt_intr_establish arm_intr_establish_fdt
#define fdt_intr_establish_cpu arm_intr_establish_fdt_cpu
#define fdt_intr_establish_idx arm_intr_establish_fdt_idx
#define fdt_intr_establish_idx_cpu arm_intr_establish_fdt_idx_cpu
#define fdt_intr_establish_imap arm_intr_establish_fdt_imap
#define fdt_intr_establish_imap_cpu arm_intr_establish_fdt_imap_cpu
#define fdt_intr_establish_msi arm_intr_establish_fdt_msi
#define fdt_intr_establish_msi_cpu arm_intr_establish_fdt_msi_cpu
#define fdt_intr_disable arm_intr_disable
#define fdt_intr_disestablish arm_intr_disestablish_fdt
#define fdt_intr_get_parent arm_intr_get_parent
#define fdt_intr_parent_establish arm_intr_parent_establish_fdt
#define fdt_intr_parent_disestablish arm_intr_parent_disestablish_fdt
#define fdt_intr_register arm_intr_register_fdt
#endif /* __ARM_FDT_H__ */

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/* $OpenBSD: fenv.h,v 1.3 2019/03/12 22:14:50 patrick Exp $ */
/*
* Copyright (c) 2011 Martynas Venckus <martynas@openbsd.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_FENV_H_
#define _MACHINE_FENV_H_
/*
* Each symbol representing a floating point exception expands to an integer
* constant expression with values, such that bitwise-inclusive ORs of _all
* combinations_ of the constants result in distinct values.
*
* We use such values that allow direct bitwise operations on FPU registers.
*/
#define FE_INVALID 0x01
#define FE_DIVBYZERO 0x02
#define FE_OVERFLOW 0x04
#define FE_UNDERFLOW 0x08
#define FE_INEXACT 0x10
#define FE_DENORMAL 0x80
/*
* The following symbol is simply the bitwise-inclusive OR of all floating-point
* exception constants defined above.
*/
#define FE_ALL_EXCEPT (FE_INVALID | FE_DIVBYZERO | FE_OVERFLOW | \
FE_UNDERFLOW | FE_INEXACT | FE_DENORMAL)
/*
* Each symbol representing the rounding direction, expands to an integer
* constant expression whose value is distinct non-negative value.
*
* We use such values that allow direct bitwise operations on FPU registers.
*/
#define FE_TONEAREST 0x0
#define FE_UPWARD 0x1
#define FE_DOWNWARD 0x2
#define FE_TOWARDZERO 0x3
/*
* The following symbol is simply the bitwise-inclusive OR of all floating-point
* rounding direction constants defined above.
*/
#define _ROUND_MASK (FE_TONEAREST | FE_UPWARD | FE_DOWNWARD | \
FE_TOWARDZERO)
#define _ROUND_SHIFT 22
/*
* fenv_t represents the entire floating-point environment.
*/
typedef unsigned long long fenv_t;
/*
* The following constant represents the default floating-point environment
* (that is, the one installed at program startup) and has type pointer to
* const-qualified fenv_t.
*
* It can be used as an argument to the functions within the <fenv.h> header
* that manage the floating-point environment, namely fesetenv() and
* feupdateenv().
*/
__BEGIN_DECLS
extern fenv_t __fe_dfl_env;
__END_DECLS
#define FE_DFL_ENV ((const fenv_t *)&__fe_dfl_env)
/*
* fexcept_t represents the floating-point status flags collectively, including
* any status the implementation associates with the flags.
*
* A floating-point status flag is a system variable whose value is set (but
* never cleared) when a floating-point exception is raised, which occurs as a
* side effect of exceptional floating-point arithmetic to provide auxiliary
* information.
*
* A floating-point control mode is a system variable whose value may be set by
* the user to affect the subsequent behavior of floating-point arithmetic.
*/
typedef unsigned long long fexcept_t;
#endif /* !_MACHINE_FENV_H_ */

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/* $OpenBSD: fpu.h,v 1.2 2025/02/11 22:27:09 kettenis Exp $ */
/*
* Copyright (c) 2022 Mark Kettenis <kettenis@openbsd.org>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_FPU_H
#define _MACHINE_FPU_H
void fpu_save(struct proc *);
void fpu_load(struct proc *);
void sve_load(struct proc *);
void fpu_drop(void);
void fpu_kernel_enter(void);
void fpu_kernel_exit(void);
#endif /* !_MACHINE_FPU_H */

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/* $OpenBSD: frame.h,v 1.3 2018/06/30 15:23:37 deraadt Exp $ */
/*
* Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_FRAME_H_
#define _MACHINE_FRAME_H_
#ifndef _LOCORE
#include <sys/signal.h>
/*
* Exception/Trap Stack Frame
*/
#define clockframe trapframe
typedef struct trapframe {
register_t tf_sp;
register_t tf_lr;
register_t tf_elr;
register_t tf_spsr;
register_t tf_x[30];
} trapframe_t;
/*
* pushed on stack for signal delivery
*/
struct sigframe {
int sf_signum;
struct sigcontext sf_sc;
siginfo_t sf_si;
};
/*
* System stack frames.
*/
/*
* Stack frame inside cpu_switch()
*/
struct switchframe {
register_t sf_x19;
register_t sf_x20;
register_t sf_x21;
register_t sf_x22;
register_t sf_x23;
register_t sf_x24;
register_t sf_x25;
register_t sf_x26;
register_t sf_x27;
register_t sf_x28;
register_t sf_x29;
register_t sf_lr;
};
struct callframe {
struct callframe *f_frame;
register_t f_lr;
};
#endif /* !_LOCORE */
#endif /* _MACHINE_FRAME_H_ */

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/* $OpenBSD: hypervisor.h,v 1.5 2025/02/11 22:27:09 kettenis Exp $ */
/*-
* Copyright (c) 2013, 2014 Andrew Turner
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD: head/sys/arm64/include/hypervisor.h 281494 2015-04-13 14:43:10Z andrew $
*/
#ifndef _MACHINE_HYPERVISOR_H_
#define _MACHINE_HYPERVISOR_H_
/*
* These registers are only useful when in hypervisor context,
* e.g. specific to EL2, or controlling the hypervisor.
*/
/*
* Architecture feature trap register
*/
#define CPTR_RES0 0x7fefc800
#define CPTR_RES1 0x000032ff
#define CPTR_TFP 0x00000400
#define CPTR_TTA 0x00100000
#define CPTR_TCPAC 0x80000000
/*
* Hypervisor Config Register
*/
#define HCR_VM 0x0000000000000001
#define HCR_SWIO 0x0000000000000002
#define HCR_PTW 0x0000000000000004
#define HCR_FMO 0x0000000000000008
#define HCR_IMO 0x0000000000000010
#define HCR_AMO 0x0000000000000020
#define HCR_VF 0x0000000000000040
#define HCR_VI 0x0000000000000080
#define HCR_VSE 0x0000000000000100
#define HCR_FB 0x0000000000000200
#define HCR_BSU_MASK 0x0000000000000c00
#define HCR_DC 0x0000000000001000
#define HCR_TWI 0x0000000000002000
#define HCR_TWE 0x0000000000004000
#define HCR_TID0 0x0000000000008000
#define HCR_TID1 0x0000000000010000
#define HCR_TID2 0x0000000000020000
#define HCR_TID3 0x0000000000040000
#define HCR_TSC 0x0000000000080000
#define HCR_TIDCP 0x0000000000100000
#define HCR_TACR 0x0000000000200000
#define HCR_TSW 0x0000000000400000
#define HCR_TPC 0x0000000000800000
#define HCR_TPU 0x0000000001000000
#define HCR_TTLB 0x0000000002000000
#define HCR_TVM 0x0000000004000000
#define HCR_TGE 0x0000000008000000
#define HCR_TDZ 0x0000000010000000
#define HCR_HCD 0x0000000020000000
#define HCR_TRVM 0x0000000040000000
#define HCR_RW 0x0000000080000000
#define HCR_CD 0x0000000100000000
#define HCR_ID 0x0000000200000000
#define HCR_E2H 0x0000000400000000
#define HCR_APK 0x0000010000000000
#define HCR_API 0x0000020000000000
#endif

148
lib/libc/include/aarch64-openbsd-none/machine/ieee.h vendored Normal file
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@ -0,0 +1,148 @@
/* $OpenBSD: ieee.h,v 1.3 2017/04/16 16:14:37 kettenis Exp $ */
/* $NetBSD: ieee.h,v 1.1 1996/09/30 16:34:25 ws Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)ieee.h 8.1 (Berkeley) 6/11/93
*/
/*
* ieee.h defines the machine-dependent layout of the machine's IEEE
* floating point. It does *not* define (yet?) any of the rounding
* mode bits, exceptions, and so forth.
*/
/*
* Define the number of bits in each fraction and exponent.
*
* k k+1
* Note that 1.0 x 2 == 0.1 x 2 and that denorms are represented
*
* (-exp_bias+1)
* as fractions that look like 0.fffff x 2 . This means that
*
* -126
* the number 0.10000 x 2 , for instance, is the same as the normalized
*
* -127 -128
* float 1.0 x 2 . Thus, to represent 2 , we need one leading zero
*
* -129
* in the fraction; to represent 2 , we need two, and so on. This
*
* (-exp_bias-fracbits+1)
* implies that the smallest denormalized number is 2
*
* for whichever format we are talking about: for single precision, for
*
* -126 -149
* instance, we get .00000000000000000000001 x 2 , or 1.0 x 2 , and
*
* -149 == -127 - 23 + 1.
*/
#define SNG_EXPBITS 8
#define SNG_FRACBITS 23
#define DBL_EXPBITS 11
#define DBL_FRACHBITS 20
#define DBL_FRACLBITS 32
#define DBL_FRACBITS 52
#define EXT_EXPBITS 15
#define EXT_FRACHBITS 16
#define EXT_FRACHMBITS 32
#define EXT_FRACLMBITS 32
#define EXT_FRACLBITS 32
#define EXT_FRACBITS 112
#define EXT_IMPLICIT_NBIT
#define EXT_TO_ARRAY32(p, a) do { \
(a)[0] = (uint32_t)(p)->ext_fracl; \
(a)[1] = (uint32_t)(p)->ext_fraclm; \
(a)[2] = (uint32_t)(p)->ext_frachm; \
(a)[3] = (uint32_t)(p)->ext_frach; \
} while(0)
struct ieee_single {
u_int sng_frac:23;
u_int sng_exp:8;
u_int sng_sign:1;
};
struct ieee_double {
u_int dbl_fracl;
u_int dbl_frach:20;
u_int dbl_exp:11;
u_int dbl_sign:1;
};
struct ieee_ext {
u_int ext_fracl;
u_int ext_fraclm;
u_int ext_frachm;
u_int ext_frach:16;
u_int ext_exp:15;
u_int ext_sign:1;
};
/*
* Floats whose exponent is in [1..INFNAN) (of whatever type) are
* `normal'. Floats whose exponent is INFNAN are either Inf or NaN.
* Floats whose exponent is zero are either zero (iff all fraction
* bits are zero) or subnormal values.
*
* A NaN is a `signalling NaN' if its QUIETNAN bit is clear in its
* high fraction; if the bit is set, it is a `quiet NaN'.
*/
#define SNG_EXP_INFNAN 255
#define DBL_EXP_INFNAN 2047
#define EXT_EXP_INFNAN 32767
#if 0
#define SNG_QUIETNAN (1 << 22)
#define DBL_QUIETNAN (1 << 19)
#define EXT_QUIETNAN (1 << 15)
#endif
/*
* Exponent biases.
*/
#define SNG_EXP_BIAS 127
#define DBL_EXP_BIAS 1023
#define EXT_EXP_BIAS 16383

25
lib/libc/include/aarch64-openbsd-none/machine/ieeefp.h vendored Normal file
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/* $OpenBSD: ieeefp.h,v 1.2 2021/05/01 20:07:01 kettenis Exp $ */
/*
* Based on ieeefp.h written by J.T. Conklin, Apr 28, 1995
* Public domain.
*/
#ifndef _MACHINE_IEEEFP_H_
#define _MACHINE_IEEEFP_H_
typedef int fp_except;
#define FP_X_INV 0x01 /* invalid operation exception */
#define FP_X_DZ 0x02 /* divide-by-zero exception */
#define FP_X_OFL 0x04 /* overflow exception */
#define FP_X_UFL 0x08 /* underflow exception */
#define FP_X_IMP 0x10 /* imprecise (loss of precision) */
typedef enum {
FP_RN=0, /* round to nearest representable number */
FP_RP=1, /* round toward positive infinity */
FP_RM=2, /* round toward negative infinity */
FP_RZ=3 /* round to zero (truncate) */
} fp_rnd;
#endif /* _MACHINE_IEEEFP_H_ */

226
lib/libc/include/aarch64-openbsd-none/machine/intr.h vendored Normal file
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/* $OpenBSD: intr.h,v 1.25 2025/06/30 14:19:20 kettenis Exp $ */
/*
* Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#ifndef _MACHINE_INTR_H_
#define _MACHINE_INTR_H_
/*
* The interrupt level ipl is a logical level; per-platform interrupt
* code will turn it into the appropriate hardware interrupt masks
* values.
*
* Interrupt sources on the CPU are kept enabled regardless of the
* current ipl value; individual hardware sources interrupting while
* logically masked are masked on the fly, remembered as pending, and
* unmasked at the first splx() opportunity.
*/
#ifdef _KERNEL
/* Interrupt priority `levels'; not mutually exclusive. */
#define IPL_NONE 0 /* nothing */
#define IPL_SOFTCLOCK 2 /* soft clock interrupts */
#define IPL_SOFTNET 3 /* soft network interrupts */
#define IPL_SOFTTTY 4 /* soft terminal interrupts */
#define IPL_BIO 5 /* block I/O */
#define IPL_NET 6 /* network */
#define IPL_TTY 7 /* terminal */
#define IPL_VM 8 /* memory allocation */
#define IPL_AUDIO 9 /* audio */
#define IPL_CLOCK 10 /* clock */
#define IPL_SCHED IPL_CLOCK
#define IPL_STATCLOCK IPL_CLOCK
#define IPL_HIGH 11 /* everything */
#define IPL_IPI 12 /* interprocessor interrupt */
#define NIPL 13 /* number of levels */
#define IPL_MPFLOOR IPL_TTY
/* Interrupt priority 'flags'. */
#define IPL_IRQMASK 0xf /* priority only */
#define IPL_FLAGMASK 0xf00 /* flags only*/
#define IPL_MPSAFE 0x100 /* 'mpsafe' interrupt, no kernel lock */
#define IPL_WAKEUP 0x200 /* 'wakeup' interrupt */
/* Interrupt sharing types. */
#define IST_NONE 0 /* none */
#define IST_PULSE 1 /* pulsed */
#define IST_EDGE 2 /* edge-triggered */
#define IST_LEVEL 3 /* level-triggered */
#define IST_LEVEL_LOW IST_LEVEL
#define IST_LEVEL_HIGH 4
#define IST_EDGE_FALLING IST_EDGE
#define IST_EDGE_RISING 5
#define IST_EDGE_BOTH 6
#define __USE_MI_SOFTINTR
#include <sys/softintr.h>
#ifndef _LOCORE
#include <sys/queue.h>
void softintr(int);
int splraise(int);
int spllower(int);
void splx(int);
void arm_do_pending_intr(int);
void arm_set_intr_handler(int (*)(int), int (*)(int), void (*)(int),
void (*)(int), void (*)(void *), void (*)(void *),
void (*)(void), void (*)(void));
struct machine_intr_handle {
struct interrupt_controller *ih_ic;
void *ih_ih;
};
struct arm_intr_func {
int (*raise)(int);
int (*lower)(int);
void (*x)(int);
void (*setipl)(int);
void (*enable_wakeup)(void);
void (*disable_wakeup)(void);
};
extern struct arm_intr_func arm_intr_func;
#define splraise(cpl) (arm_intr_func.raise(cpl))
#define _splraise(cpl) (arm_intr_func.raise(cpl))
#define spllower(cpl) (arm_intr_func.lower(cpl))
#define splx(cpl) (arm_intr_func.x(cpl))
#define splsoftclock() splraise(IPL_SOFTCLOCK)
#define splsoftnet() splraise(IPL_SOFTNET)
#define splsofttty() splraise(IPL_SOFTTTY)
#define splbio() splraise(IPL_BIO)
#define splnet() splraise(IPL_NET)
#define spltty() splraise(IPL_TTY)
#define splvm() splraise(IPL_VM)
#define splaudio() splraise(IPL_AUDIO)
#define splclock() splraise(IPL_CLOCK)
#define splsched() splraise(IPL_SCHED)
#define splstatclock() splraise(IPL_STATCLOCK)
#define splhigh() splraise(IPL_HIGH)
#define spl0() spllower(IPL_NONE)
void intr_barrier(void *);
void intr_set_wakeup(void *);
void intr_enable_wakeup(void);
void intr_disable_wakeup(void);
void arm_init_smask(void); /* XXX */
extern uint32_t arm_smask[NIPL];
/* XXX - this is probably the wrong location for this */
void arm_clock_register(void (*)(void), void (*)(u_int), void (*)(int),
void (*)(void));
struct cpu_info;
struct interrupt_controller {
int ic_node;
void *ic_cookie;
void *(*ic_establish)(void *, int *, int, struct cpu_info *,
int (*)(void *), void *, char *);
void *(*ic_establish_msi)(void *, uint64_t *, uint64_t *, int,
struct cpu_info *, int (*)(void *), void *, char *);
void (*ic_disestablish)(void *);
void (*ic_enable)(void *);
void (*ic_disable)(void *);
void (*ic_route)(void *, int, struct cpu_info *);
void (*ic_cpu_enable)(void);
void (*ic_barrier)(void *);
void (*ic_set_wakeup)(void *);
LIST_ENTRY(interrupt_controller) ic_list;
uint32_t ic_phandle;
uint32_t ic_cells;
uint32_t ic_gic_its_id;
};
void arm_intr_init_fdt(void);
void arm_intr_register_fdt(struct interrupt_controller *);
void *arm_intr_establish_fdt(int, int, int (*)(void *),
void *, char *);
void *arm_intr_establish_fdt_cpu(int, int, struct cpu_info *,
int (*)(void *), void *, char *);
void *arm_intr_establish_fdt_idx(int, int, int, int (*)(void *),
void *, char *);
void *arm_intr_establish_fdt_idx_cpu(int, int, int, struct cpu_info *,
int (*)(void *), void *, char *);
void *arm_intr_establish_fdt_imap(int, int *, int, int, int (*)(void *),
void *, char *);
void *arm_intr_establish_fdt_imap_cpu(int, int *, int, int,
struct cpu_info *, int (*)(void *), void *, char *);
void *arm_intr_establish_fdt_msi(int, uint64_t *, uint64_t *, int,
int (*)(void *), void *, char *);
void *arm_intr_establish_fdt_msi_cpu(int, uint64_t *, uint64_t *, int,
struct cpu_info *, int (*)(void *), void *, char *);
void arm_intr_disestablish_fdt(void *);
void arm_intr_enable(void *);
void arm_intr_disable(void *);
void arm_intr_route(void *, int, struct cpu_info *);
void arm_intr_cpu_enable(void);
void *arm_intr_parent_establish_fdt(void *, int *, int,
struct cpu_info *ci, int (*)(void *), void *, char *);
void arm_intr_parent_disestablish_fdt(void *);
void arm_send_ipi(struct cpu_info *, int);
extern void (*intr_send_ipi_func)(struct cpu_info *, int);
#define ARM_IPI_NOP 0
#define ARM_IPI_DDB 1
#define ARM_IPI_HALT 2
#ifdef DIAGNOSTIC
/*
* Although this function is implemented in MI code, it must be in this MD
* header because we don't want this header to include MI includes.
*/
void splassert_fail(int, int, const char *);
extern int splassert_ctl;
void arm_splassert_check(int, const char *);
#define splassert(__wantipl) do { \
if (splassert_ctl > 0) { \
arm_splassert_check(__wantipl, __func__); \
} \
} while (0)
#define splsoftassert(wantipl) splassert(wantipl)
#else
#define splassert(wantipl) do { /* nothing */ } while (0)
#define splsoftassert(wantipl) do { /* nothing */ } while (0)
#endif
#endif /* ! _LOCORE */
#endif /* _KERNEL */
#endif /* _MACHINE_INTR_H_ */

15
lib/libc/include/aarch64-openbsd-none/machine/kcore.h vendored Normal file
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/* $OpenBSD: kcore.h,v 1.1 2016/12/17 23:38:33 patrick Exp $ */
/* public domain */
/* Make sure this is larger than DRAM_BLOCKS on all arm-based platforms */
#define NPHYS_RAM_SEGS 8
typedef struct cpu_kcore_hdr {
u_int64_t kernelbase; /* value of KERNEL_BASE */
u_int64_t kerneloffs; /* offset of kernel in RAM */
u_int64_t staticsize; /* size of contiguous mapping */
u_int64_t pmap_kernel_l1; /* pmap_kernel()->pm_l1 */
u_int64_t pmap_kernel_l2; /* pmap_kernel()->pm_l2 */
u_int64_t reserved[11];
phys_ram_seg_t ram_segs[NPHYS_RAM_SEGS];
} cpu_kcore_hdr_t;

56
lib/libc/include/aarch64-openbsd-none/machine/limits.h vendored Normal file
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/* $OpenBSD: limits.h,v 1.1 2016/12/17 23:38:33 patrick Exp $ */
/* $NetBSD: limits.h,v 1.4 2003/04/28 23:16:18 bjh21 Exp $ */
/*
* Copyright (c) 1988 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: @(#)limits.h 7.2 (Berkeley) 6/28/90
*/
#ifndef _MACHINE_LIMITS_H_
#define _MACHINE_LIMITS_H_
#include <sys/cdefs.h>
#if __POSIX_VISIBLE || __XPG_VISIBLE
#ifndef SIZE_MAX
#define SIZE_MAX ULONG_MAX /* max value for a size_t */
#endif
#define SSIZE_MAX LONG_MAX /* max value for a ssize_t */
#endif
#if __BSD_VISIBLE
#define SIZE_T_MAX ULONG_MAX /* max value for a size_t (historic) */
#define UQUAD_MAX 0xffffffffffffffffULL /* max unsigned quad */
#define QUAD_MAX 0x7fffffffffffffffLL /* max signed quad */
#define QUAD_MIN (-0x7fffffffffffffffLL-1) /* min signed quad */
#endif /* __BSD_VISIBLE */
#endif /* _MACHINE_LIMITS_H_ */

53
lib/libc/include/aarch64-openbsd-none/machine/loadfile_machdep.h vendored Normal file
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/* $OpenBSD: loadfile_machdep.h,v 1.2 2019/04/10 04:17:34 deraadt Exp $ */
/* $NetBSD: loadfile_machdep.h,v 1.1 1999/04/29 03:17:12 tsubai Exp $ */
/*-
* Copyright (c) 1999 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Christos Zoulas.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#define BOOT_ELF
#define ELFSIZE 64
#define LOAD_KERNEL (LOAD_ALL & ~LOAD_TEXTA)
#define COUNT_KERNEL (COUNT_ALL & ~COUNT_TEXTA)
extern u_long efi_loadaddr;
#define LOADADDR(a) (((((u_long)(a)) + offset)&0x7fffffffff) + \
efi_loadaddr)
#define ALIGNENTRY(a) ((u_long)(a))
#define READ(f, b, c) read((f), (void *)LOADADDR(b), (c))
#define BCOPY(s, d, c) memcpy((void *)LOADADDR(d), (void *)(s), (c))
#define BZERO(d, c) memset((void *)LOADADDR(d), 0, (c))
#define WARN(a) (void)(printf a, \
printf((errno ? ": %s\n" : "\n"), \
strerror(errno)))
#define PROGRESS(a) (void) printf a
#define ALLOC(a) alloc(a)
#define FREE(a, b) free(a, b)
void run_loadfile(uint64_t *, int);

10
lib/libc/include/aarch64-openbsd-none/machine/mplock.h vendored Normal file
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@ -0,0 +1,10 @@
/* $OpenBSD: mplock.h,v 1.3 2018/01/05 17:42:35 kettenis Exp $ */
/* public domain */
#ifndef _MACHINE_MPLOCK_H_
#define _MACHINE_MPLOCK_H_
#define __USE_MI_MPLOCK
#endif /* !_MACHINE_MPLOCK_H */

3
lib/libc/include/aarch64-openbsd-none/machine/mutex.h vendored Normal file
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@ -0,0 +1,3 @@
/* $OpenBSD: mutex.h,v 1.5 2018/01/25 15:06:29 mpi Exp $ */
#define __USE_MI_MUTEX

57
lib/libc/include/aarch64-openbsd-none/machine/openpromio.h vendored Normal file
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@ -0,0 +1,57 @@
/* $OpenBSD: openpromio.h,v 1.1 2017/01/23 12:34:06 kettenis Exp $ */
/* $NetBSD: openpromio.h,v 1.1.1.1 1998/06/20 04:58:52 eeh Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This software was developed by the Computer Systems Engineering group
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
* contributed to Berkeley.
*
* All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Lawrence Berkeley Laboratory.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)openpromio.h 8.1 (Berkeley) 6/11/93
*/
struct opiocdesc {
int op_nodeid; /* passed or returned node id */
int op_namelen; /* length of op_name */
char *op_name; /* pointer to field name */
int op_buflen; /* length of op_buf (value-result) */
char *op_buf; /* pointer to field value */
};
#define OPIOCGET _IOWR('O', 1, struct opiocdesc) /* get openprom field */
#define OPIOCSET _IOW('O', 2, struct opiocdesc) /* set openprom field */
#define OPIOCNEXTPROP _IOWR('O', 3, struct opiocdesc) /* get next property */
#define OPIOCGETOPTNODE _IOR('O', 4, int) /* get openprom field */
#define OPIOCGETNEXT _IOWR('O', 5, int) /* get next node of node */
#define OPIOCGETCHILD _IOWR('O', 6, int) /* get first child of node */

81
lib/libc/include/aarch64-openbsd-none/machine/param.h vendored Normal file
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/* $OpenBSD: param.h,v 1.8 2025/07/07 18:33:36 kettenis Exp $ */
/*-
* Copyright (c) 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* William Jolitz.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifndef _MACHINE_PARAM_H_
#define _MACHINE_PARAM_H_
#ifdef _KERNEL
#ifndef _LOCORE
#include <machine/cpu.h>
#endif
#endif
#define _MACHINE arm64
#define MACHINE "arm64"
#define _MACHINE_ARCH aarch64
#define MACHINE_ARCH "aarch64"
#define MID_MACHINE MID_ARM64
#define PAGE_SHIFT 12
#define PAGE_SIZE (1 << PAGE_SHIFT)
#define PAGE_MASK (PAGE_SIZE - 1)
#define KERNBASE 0xffffff8000000000ULL /* start of kernel virtual space */
#ifdef _KERNEL
#define NBPG PAGE_SIZE /* bytes/page */
#define PGSHIFT PAGE_SHIFT /* LOG2(PAGE_SIZE) */
#define PGOFSET PAGE_MASK /* byte offset into page */
#define UPAGES 6 /* pages of u-area */
#define USPACE (UPAGES * PAGE_SIZE) /* total size of u-area */
#define USPACE_ALIGN 0 /* u-area alignment 0-none */
#define __HAVE_USPACE_GUARD
#define NMBCLUSTERS (64 * 1024) /* max cluster allocation */
#ifndef MSGBUFSIZE
#define MSGBUFSIZE (16 * PAGE_SIZE) /* default message buffer size */
#endif
#define STACKALIGNBYTES (16 - 1)
#define STACKALIGN(p) ((u_long)(p) &~ STACKALIGNBYTES)
#define __HAVE_ACPI
#define __HAVE_FDT
#endif /* _KERNEL */
#endif /* _MACHINE_PARAM_H_ */

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/* $OpenBSD: pcb.h,v 1.8 2025/02/24 13:18:01 jsg Exp $ */
/*
* Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_PCB_H_
#define _MACHINE_PCB_H_
#include <machine/frame.h>
#include <machine/reg.h>
struct trapframe;
/*
* Warning certain fields must be within 256 bytes of the beginning
* of this structure.
*/
struct pcb {
u_int pcb_flags;
#define PCB_FPU 0x00000001 /* Process had FPU initialized */
#define PCB_SINGLESTEP 0x00000002 /* Single step process */
#define PCB_SVE 0x00000004 /* Process had SVE initialized */
struct trapframe *pcb_tf;
register_t pcb_sp; /* stack pointer of switchframe */
caddr_t pcb_onfault; /* On fault handler */
struct fpreg pcb_fpstate; /* Floating Point state */
__uint16_t pcb_sve_p[16]; /* SVE predicate registers */
__uint16_t pcb_sve_ffr; /* SVE first fault register */
void *pcb_tcb;
};
#endif /* _MACHINE_PCB_H_ */

145
lib/libc/include/aarch64-openbsd-none/machine/pci_machdep.h vendored Normal file
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/* $OpenBSD: pci_machdep.h,v 1.13 2025/01/23 11:24:34 kettenis Exp $ */
/*
* Copyright (c) 2003-2004 Opsycon AB (www.opsycon.se / www.opsycon.com)
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
typedef struct machine_pci_chipset *pci_chipset_tag_t;
typedef uint64_t pcitag_t;
#define PCITAG_NODE(x) ((x) >> 32)
#define PCITAG_OFFSET(x) ((x) & 0xffffffff)
/* Supported interrupt types. */
#define PCI_NONE 0
#define PCI_INTX 1
#define PCI_MSI 2
#define PCI_MSIX 3
typedef struct {
pci_chipset_tag_t ih_pc;
pcitag_t ih_tag;
int ih_intrpin;
int ih_type;
bus_dma_tag_t ih_dmat;
} pci_intr_handle_t;
struct pci_attach_args;
/*
* Machine-specific PCI structure and type definitions.
* NOT TO BE USED DIRECTLY BY MACHINE INDEPENDENT CODE.
*/
struct machine_pci_chipset {
void *pc_conf_v;
void (*pc_attach_hook)(struct device *,
struct device *, struct pcibus_attach_args *);
int (*pc_bus_maxdevs)(void *, int);
pcitag_t (*pc_make_tag)(void *, int, int, int);
void (*pc_decompose_tag)(void *, pcitag_t, int *,
int *, int *);
int (*pc_conf_size)(void *, pcitag_t);
pcireg_t (*pc_conf_read)(void *, pcitag_t, int);
void (*pc_conf_write)(void *, pcitag_t, int, pcireg_t);
int (*pc_probe_device_hook)(void *, struct pci_attach_args *);
void *pc_intr_v;
int (*pc_intr_map)(struct pci_attach_args *,
pci_intr_handle_t *);
int (*pc_intr_map_msi)(struct pci_attach_args *,
pci_intr_handle_t *);
int (*pc_intr_map_msivec)(struct pci_attach_args *,
int, pci_intr_handle_t *);
int (*pc_intr_map_msix)(struct pci_attach_args *,
int, pci_intr_handle_t *);
const char *(*pc_intr_string)(void *, pci_intr_handle_t);
void *(*pc_intr_establish)(void *, pci_intr_handle_t,
int, struct cpu_info *, int (*)(void *), void *,
char *);
void (*pc_intr_disestablish)(void *, void *);
};
/*
* Functions provided to machine-independent PCI code.
*/
#define pci_attach_hook(p, s, pba) \
(*(pba)->pba_pc->pc_attach_hook)((p), (s), (pba))
#define pci_bus_maxdevs(c, b) \
(*(c)->pc_bus_maxdevs)((c)->pc_conf_v, (b))
#define pci_make_tag(c, b, d, f) \
(*(c)->pc_make_tag)((c)->pc_conf_v, (b), (d), (f))
#define pci_decompose_tag(c, t, bp, dp, fp) \
(*(c)->pc_decompose_tag)((c)->pc_conf_v, (t), (bp), (dp), (fp))
#define pci_conf_size(c, t) \
(*(c)->pc_conf_size)((c)->pc_conf_v, (t))
#define pci_conf_read(c, t, r) \
(*(c)->pc_conf_read)((c)->pc_conf_v, (t), (r))
#define pci_conf_write(c, t, r, v) \
(*(c)->pc_conf_write)((c)->pc_conf_v, (t), (r), (v))
#define pci_probe_device_hook(c, a) \
(*(c)->pc_probe_device_hook)((c)->pc_conf_v, (a))
#define pci_intr_map(c, ihp) \
(*(c)->pa_pc->pc_intr_map)((c), (ihp))
#define pci_intr_map_msi(c, ihp) \
(*(c)->pa_pc->pc_intr_map_msi)((c), (ihp))
#define pci_intr_map_msivec(c, vec, ihp) \
(*(c)->pa_pc->pc_intr_map_msivec)((c), (vec), (ihp))
#define pci_intr_map_msix(c, vec, ihp) \
(*(c)->pa_pc->pc_intr_map_msix)((c), (vec), (ihp))
#define pci_intr_string(c, ih) \
(*(c)->pc_intr_string)((c)->pc_intr_v, (ih))
#define pci_intr_establish(c, ih, l, h, a, nm) \
(*(c)->pc_intr_establish)((c)->pc_intr_v, (ih), (l), NULL, (h), (a),\
(nm))
#define pci_intr_establish_cpu(c, ih, l, ci, h, a, nm) \
(*(c)->pc_intr_establish)((c)->pc_intr_v, (ih), (l), (ci), (h), (a),\
(nm))
#define pci_intr_disestablish(c, iv) \
(*(c)->pc_intr_disestablish)((c)->pc_intr_v, (iv))
#define pci_min_powerstate(c, t) (PCI_PMCSR_STATE_D3)
#define pci_set_powerstate_md(c, t, s, p)
#define pci_dev_postattach(a, b)
void pci_mcfg_init(bus_space_tag_t, bus_addr_t, int, int, int);
pci_chipset_tag_t pci_lookup_segment(int, int);
int pci_intr_enable_msivec(struct pci_attach_args *, int);
void pci_msi_enable(pci_chipset_tag_t, pcitag_t, bus_addr_t, uint32_t);
void pci_msix_enable(pci_chipset_tag_t, pcitag_t, bus_space_tag_t,
int, bus_addr_t, uint32_t);
int _pci_intr_map_msi(struct pci_attach_args *, pci_intr_handle_t *);
int _pci_intr_map_msivec(struct pci_attach_args *, int,
pci_intr_handle_t *);
int _pci_intr_map_msix(struct pci_attach_args *, int, pci_intr_handle_t *);
#define __HAVE_PCI_MSIX
int pci_msix_table_map(pci_chipset_tag_t, pcitag_t,
bus_space_tag_t, bus_space_handle_t *);
void pci_msix_table_unmap(pci_chipset_tag_t, pcitag_t,
bus_space_tag_t, bus_space_handle_t);

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/* $OpenBSD: pmap.h,v 1.29 2025/05/21 09:42:59 kettenis Exp $ */
/*
* Copyright (c) 2008,2009,2014 Dale Rahn <drahn@dalerahn.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ARM64_PMAP_H_
#define _ARM64_PMAP_H_
#ifndef _LOCORE
#include <sys/mutex.h>
#include <sys/queue.h>
#include <machine/pte.h>
#endif
/* V->P mapping data */
#define VP_IDX0_CNT 512
#define VP_IDX0_MASK (VP_IDX0_CNT-1)
#define VP_IDX0_POS 39
#define VP_IDX1_CNT 512
#define VP_IDX1_MASK (VP_IDX1_CNT-1)
#define VP_IDX1_POS 30
#define VP_IDX2_CNT 512
#define VP_IDX2_MASK (VP_IDX2_CNT-1)
#define VP_IDX2_POS 21
#define VP_IDX3_CNT 512
#define VP_IDX3_MASK (VP_IDX3_CNT-1)
#define VP_IDX3_POS 12
/* cache flags */
#define PMAP_CACHE_CI (PMAP_MD0) /* cache inhibit */
#define PMAP_CACHE_WT (PMAP_MD1) /* writethru */
#define PMAP_CACHE_WB (PMAP_MD1|PMAP_MD0) /* writeback */
#define PMAP_CACHE_DEV_NGNRNE (PMAP_MD2) /* device nGnRnE */
#define PMAP_CACHE_DEV_NGNRE (PMAP_MD2|PMAP_MD0) /* device nGnRE */
#define PMAP_CACHE_BITS (PMAP_MD0|PMAP_MD1|PMAP_MD2)
#define PTED_VA_MANAGED_M (PMAP_MD3)
#define PTED_VA_WIRED_M (PMAP_MD3 << 1)
#if defined(_KERNEL) && !defined(_LOCORE)
/*
* Pmap stuff
*/
typedef struct pmap *pmap_t;
struct pmap {
struct mutex pm_mtx;
union {
struct pmapvp0 *l0; /* virtual to physical table 4 lvl */
struct pmapvp1 *l1; /* virtual to physical table 3 lvl */
} pm_vp;
uint64_t pm_pt0pa;
uint64_t pm_asid;
uint64_t pm_guarded;
int have_4_level_pt;
int pm_privileged;
volatile int pm_active;
int pm_refs; /* ref count */
struct pmap_statistics pm_stats; /* pmap statistics */
uint64_t pm_apiakey[2];
uint64_t pm_apdakey[2];
uint64_t pm_apibkey[2];
uint64_t pm_apdbkey[2];
uint64_t pm_apgakey[2];
};
#define PMAP_PA_MASK ~((paddr_t)PAGE_MASK) /* to remove the flags */
#define PMAP_NOCACHE 0x1 /* non-cacheable memory */
#define PMAP_DEVICE 0x2 /* device memory */
#define PMAP_WC PMAP_DEVICE
#define PG_PMAP_MOD PG_PMAP0
#define PG_PMAP_REF PG_PMAP1
#define PG_PMAP_EXE PG_PMAP2
// [NCPUS]
extern paddr_t zero_page;
extern paddr_t copy_src_page;
extern paddr_t copy_dst_page;
void pagezero_cache(vaddr_t);
extern struct pmap kernel_pmap_;
#define pmap_kernel() (&kernel_pmap_)
#define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count)
#define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count)
vaddr_t pmap_bootstrap(long kvo, paddr_t lpt1, long kernelstart,
long kernelend, long ram_start, long ram_end);
void pmap_postinit(void);
void pmap_init_percpu(void);
void pmap_kenter_cache(vaddr_t va, paddr_t pa, vm_prot_t prot, int cacheable);
void pmap_page_ro(pmap_t pm, vaddr_t va, vm_prot_t prot);
void pmap_page_rw(pmap_t pm, vaddr_t va);
void pmap_setpauthkeys(struct pmap *);
paddr_t pmap_steal_avail(size_t size, int align, void **kva);
void pmap_avail_fixup(void);
void pmap_physload_avail(void);
#define PMAP_GROWKERNEL
struct pv_entry;
/* investigate */
#define pmap_unuse_final(p) do { /* nothing */ } while (0)
int pmap_fault_fixup(pmap_t, vaddr_t, vm_prot_t);
#define __HAVE_PMAP_MPSAFE_ENTER_COW
#define __HAVE_PMAP_POPULATE
#define __HAVE_PMAP_PURGE
#endif /* _KERNEL && !_LOCORE */
#ifndef _LOCORE
struct vm_page_md {
struct mutex pv_mtx;
LIST_HEAD(,pte_desc) pv_list;
};
#define VM_MDPAGE_INIT(pg) do { \
mtx_init(&(pg)->mdpage.pv_mtx, IPL_VM); \
LIST_INIT(&((pg)->mdpage.pv_list)); \
} while (0)
#endif /* _LOCORE */
#endif /* _ARM64_PMAP_H_ */

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/* $OpenBSD: proc.h,v 1.2 2017/04/13 03:52:25 guenther Exp $ */
/* $NetBSD: proc.h,v 1.1 2003/04/26 18:39:46 fvdl Exp $ */
/*
* Copyright (c) 1991 Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)proc.h 7.1 (Berkeley) 5/15/91
*/
#ifndef _MACHINE_PROC_H_
#define _MACHINE_PROC_H_
/*
* Machine-dependent part of the proc structure for arm64.
*/
struct mdproc {
volatile int md_astpending;
};
#endif /* _MACHINE_PROC_H_ */

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/* $OpenBSD: profile.h,v 1.2 2021/02/17 12:11:45 kettenis Exp $ */
/*
* Copyright (c) 2015 Dale Rahn <drahn@dalerahn.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#define _MCOUNT_DECL void _mcount
#define MCOUNT_ASM_NAME "__mcount"
#ifdef __PIC__
#define PLTSYM "" /* XXX -aarch64 defaults to PLT? */
#else
#define PLTSYM ""
#endif
#define MCOUNT \
__asm__ (".text;" \
".align 3;" \
".globl " MCOUNT_ASM_NAME ";" \
".type " MCOUNT_ASM_NAME ",@function;" \
MCOUNT_ASM_NAME ":;" \
" stp x0, x1, [sp, #-160]!;" \
" stp x2, x3, [sp, #16];" \
" stp x4, x5, [sp, #32];" \
" stp x6, x7, [sp, #48];" \
" stp x8, x9, [sp, #64];" \
" stp x10,x11,[sp, #80];" \
" stp x12,x13,[sp, #96];" \
" stp x14,x15,[sp, #112];" \
" stp x16,x17,[sp, #128];" \
" stp x29,lr, [sp, #144];" \
/* load from pc at 8 off frame pointer */ \
" ldr x0, [x29, #8];" \
" mov x1, lr;" \
" bl " __STRING(_mcount) PLTSYM ";" \
/* restore argument registers */ \
" ldp x2, x3, [sp, #16];" \
" ldp x4, x5, [sp, #32];" \
" ldp x6, x7, [sp, #48];" \
" ldp x8, x9, [sp, #64];" \
" ldp x10,x11,[sp, #80];" \
" ldp x12,x13,[sp, #96];" \
" ldp x14,x15,[sp, #112];" \
" ldp x16,x17,[sp, #128];" \
" ldp x29,lr, [sp, #144];" \
" ldp x0, x1, [sp], #160;" \
" ret;");
#ifdef _KERNEL
// Change this to dair read/set, then restore.
#define MCOUNT_ENTER \
__asm__ ("mrs %x0, daif; msr daifset, #0x3": "=r"(s));
#define MCOUNT_EXIT \
__asm__ ("msr daif, %x0":: "r"(s));
#endif // _KERNEL

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/* $OpenBSD: pte.h,v 1.10 2024/10/14 12:02:16 jsg Exp $ */
/*
* Copyright (c) 2014 Dale Rahn <drahn@dalerahn.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _ARM_PTE_H_
#define _ARM_PTE_H_
/* level X descriptor */
#define Lx_TYPE_MASK (0x00000003) /* mask of type bits */
#define Lx_TYPE_S (0x00000001)
#define Lx_TYPE_PT (0x00000003)
// XXX need to investigate use of these
#define Lx_PT_NS (1ULL<<63)
#define Lx_PT_AP00 (0ULL<<61)
#define Lx_PT_AP01 (1ULL<<61)
#define Lx_PT_AP10 (2ULL<<61)
#define Lx_PT_AP11 (3ULL<<61)
#define Lx_PT_XN (1ULL<<60)
#define Lx_PT_PXN (1ULL<<59)
#define Lx_TABLE_ALIGN (4096)
/* Block and Page attributes */
/* TODO: Add the upper attributes */
#define ATTR_MASK_H (0xfff0000000000000ULL)
#define ATTR_MASK_L (0x0000000000000fffULL)
#define ATTR_MASK (ATTR_MASK_H | ATTR_MASK_L)
/* Bits 58:55 are reserved for software */
#define ATTR_SW_MANAGED (1UL << 56)
#define ATTR_SW_WIRED (1UL << 55)
#define ATTR_UXN (1UL << 54)
#define ATTR_PXN (1UL << 53)
#define ATTR_GP (1UL << 50)
#define ATTR_nG (1 << 11)
#define ATTR_AF (1 << 10)
#define ATTR_SH(x) ((x) << 8)
#define ATTR_AP_RW_BIT (1 << 7)
#define ATTR_AP(x) ((x) << 6)
#define ATTR_AP_MASK ATTR_AP(3)
#define ATTR_NS (1 << 5)
#define ATTR_IDX(x) ((x) << 2)
#define ATTR_IDX_MASK (7 << 2)
#define PTE_ATTR_DEV_NGNRNE 0
#define PTE_ATTR_DEV_NGNRE 1
#define PTE_ATTR_CI 2
#define PTE_ATTR_WB 3
#define PTE_ATTR_WT 4
#define PTE_MEMATTR_DEV_NGNRNE 0x0
#define PTE_MEMATTR_DEV_NGNRE 0x1
#define PTE_MEMATTR_CI 0x5
#define PTE_MEMATTR_WB 0xf
#define PTE_MEMATTR_WT 0xa
#define SH_INNER 3
#define SH_OUTER 2
#define SH_NONE 0
/* Level 0 table, 512GiB per entry */
#define L0_SHIFT 39
#define L0_INVAL 0x0 /* An invalid address */
#define L0_BLOCK 0x1 /* A block */
/* 0x2 also marks an invalid address */
#define L0_TABLE 0x3 /* A next-level table */
/* Level 1 table, 1GiB per entry */
#define L1_SHIFT 30
#define L1_SIZE (1 << L1_SHIFT)
#define L1_OFFSET (L1_SIZE - 1)
#define L1_INVAL L0_INVAL
#define L1_BLOCK L0_BLOCK
#define L1_TABLE L0_TABLE
/* Level 2 table, 2MiB per entry */
#define L2_SHIFT 21
#define L2_SIZE (1 << L2_SHIFT)
#define L2_OFFSET (L2_SIZE - 1)
#define L2_INVAL L0_INVAL
#define L2_BLOCK L0_BLOCK
#define L2_TABLE L0_TABLE
/* page mapping */
#define L3_P 0x3
#define Ln_ENTRIES (1 << 9)
#define Ln_ADDR_MASK (Ln_ENTRIES - 1)
#define Ln_TABLE_MASK ((1 << 12) - 1)
/* physical page mask */
#define PTE_RPGN (((1ULL << 48) - 1) & ~PAGE_MASK)
#endif /* _ARM_PTE_H_ */

27
lib/libc/include/aarch64-openbsd-none/machine/ptrace.h vendored Normal file
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/* $OpenBSD: ptrace.h,v 1.2 2023/06/10 19:30:48 kettenis Exp $ */
/*
* Copyright (c) 2014 Patrick Wildt <patrick@blueri.se>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#define PT_STEP (PT_FIRSTMACH + 0)
#define PT_GETREGS (PT_FIRSTMACH + 1)
#define PT_SETREGS (PT_FIRSTMACH + 2)
#define PT_GETFPREGS (PT_FIRSTMACH + 3)
#define PT_SETFPREGS (PT_FIRSTMACH + 4)
#define PT_PACMASK (PT_FIRSTMACH + 5)
#ifdef _KERNEL
register_t process_get_pacmask(struct proc *p);
#endif

36
lib/libc/include/aarch64-openbsd-none/machine/reg.h vendored Normal file
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/* $OpenBSD: reg.h,v 1.3 2017/04/11 06:52:13 kettenis Exp $ */
/*
* Copyright (c) 2014 Patrick Wildt <patrick@blueri.se>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef _MACHINE_REG_H_
#define _MACHINE_REG_H_
struct reg {
uint64_t r_reg[30];
uint64_t r_lr;
uint64_t r_sp;
uint64_t r_pc;
uint64_t r_spsr;
uint64_t r_tpidr;
};
struct fpreg {
__uint128_t fp_reg[32];
uint32_t fp_sr;
uint32_t fp_cr;
};
#endif /* !_MACHINE_REG_H_ */

123
lib/libc/include/aarch64-openbsd-none/machine/reloc.h vendored Normal file
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/* $OpenBSD: reloc.h,v 1.2 2017/10/24 20:35:54 guenther Exp $ */
/*
* AArch64 static relocation types.
*/
/* Miscellaneous. */
#define R_ARM_NONE 0
#define R_AARCH64_TPOFF64 1 /// COMPLETELY WRONG - stub
#define R_AARCH64_NONE 0
/* Data. */
#define R_AARCH64_ABS64 257
#define R_AARCH64_ABS32 258
#define R_AARCH64_ABS16 259
#define R_AARCH64_PREL64 260
#define R_AARCH64_PREL32 261
#define R_AARCH64_PREL16 262
/* Instructions. */
#define R_AARCH64_MOVW_UABS_G0 263
#define R_AARCH64_MOVW_UABS_G0_NC 264
#define R_AARCH64_MOVW_UABS_G1 265
#define R_AARCH64_MOVW_UABS_G1_NC 266
#define R_AARCH64_MOVW_UABS_G2 267
#define R_AARCH64_MOVW_UABS_G2_NC 268
#define R_AARCH64_MOVW_UABS_G3 269
#define R_AARCH64_MOVW_SABS_G0 270
#define R_AARCH64_MOVW_SABS_G1 271
#define R_AARCH64_MOVW_SABS_G2 272
#define R_AARCH64_LD_PREL_LO19 273
#define R_AARCH64_ADR_PREL_LO21 274
#define R_AARCH64_ADR_PREL_PG_HI21 275
#define R_AARCH64_ADR_PREL_PG_HI21_NC 276
#define R_AARCH64_ADD_ABS_LO12_NC 277
#define R_AARCH64_LDST8_ABS_LO12_NC 278
#define R_AARCH64_TSTBR14 279
#define R_AARCH64_CONDBR19 280
#define R_AARCH64_JUMP26 282
#define R_AARCH64_CALL26 283
#define R_AARCH64_LDST16_ABS_LO12_NC 284
#define R_AARCH64_LDST32_ABS_LO12_NC 285
#define R_AARCH64_LDST64_ABS_LO12_NC 286
#define R_AARCH64_LDST128_ABS_LO12_NC 299
#define R_AARCH64_MOVW_PREL_G0 287
#define R_AARCH64_MOVW_PREL_G0_NC 288
#define R_AARCH64_MOVW_PREL_G1 289
#define R_AARCH64_MOVW_PREL_G1_NC 290
#define R_AARCH64_MOVW_PREL_G2 291
#define R_AARCH64_MOVW_PREL_G2_NC 292
#define R_AARCH64_MOVW_PREL_G3 293
#define R_AARCH64_COPY 1024
#define R_AARCH64_GLOB_DAT 1025 // S + A
#define R_AARCH64_JUMP_SLOT 1026 // S + A
#define R_AARCH64_RELATIVE 1027 // Delta(S) + A
#define R_AARCH64_TLS_DTPREL64 1028 // DTPREL(S+A)
#define R_AARCH64_TLS_DTPMOD64 1029 // LDM(S)
#define R_AARCH64_TLS_TPREL64 1030 // TPREL(S+A)
#define R_AARCH64_TLSDESC 1031 // TLSDESC(S+A) TLS descriptor to be filled
#define R_AARCH64_IRELATIVE 1032 // Indirect(Delta(S) + A)
// old arm32 defines.
/* Processor specific relocation types */
#define R_ARM_NONE 0
#define R_ARM_PC24 1
#define R_ARM_ABS32 2
#define R_ARM_REL32 3
#define R_ARM_PC13 4
#define R_ARM_ABS16 5
#define R_ARM_ABS12 6
#define R_ARM_THM_ABS5 7
#define R_ARM_ABS8 8
#define R_ARM_SBREL32 9
#define R_ARM_THM_PC22 10
#define R_ARM_THM_PC8 11
#define R_ARM_AMP_VCALL9 12
#define R_ARM_SWI24 13
#define R_ARM_THM_SWI8 14
#define R_ARM_XPC25 15
#define R_ARM_THM_XPC22 16
/* 17-31 are reserved for ARM Linux. */
#define R_ARM_TLS_DTPMOD32 17
#define R_ARM_TLS_DTPOFF32 18
#define R_ARM_TLS_TPOFF32 19
#define R_ARM_COPY 20
#define R_ARM_GLOB_DAT 21
#define R_ARM_JUMP_SLOT 22
#define R_ARM_RELATIVE 23
#define R_ARM_GOTOFF 24
#define R_ARM_GOTPC 25
#define R_ARM_GOT32 26
#define R_ARM_PLT32 27
#define R_ARM_ALU_PCREL_7_0 32
#define R_ARM_ALU_PCREL_15_8 33
#define R_ARM_ALU_PCREL_23_15 34
#define R_ARM_ALU_SBREL_11_0 35
#define R_ARM_ALU_SBREL_19_12 36
#define R_ARM_ALU_SBREL_27_20 37
/* 96-111 are reserved to G++. */
#define R_ARM_GNU_VTENTRY 100
#define R_ARM_GNU_VTINHERIT 101
#define R_ARM_THM_PC11 102
#define R_ARM_THM_PC9 103
/* 112-127 are reserved for private experiments. */
#define R_ARM_RXPC25 249
#define R_ARM_RSBREL32 250
#define R_ARM_THM_RPC22 251
#define R_ARM_RREL32 252
#define R_ARM_RABS32 253
#define R_ARM_RPC24 254
#define R_ARM_RBASE 255

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lib/libc/include/aarch64-openbsd-none/machine/setjmp.h vendored Normal file
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/* $OpenBSD: setjmp.h,v 1.2 2023/04/11 00:45:07 jsg Exp $ */
/* $NetBSD: setjmp.h,v 1.2 2001/08/25 14:45:59 bjh21 Exp $ */
/*
* machine/setjmp.h: machine dependent setjmp-related information.
*/
#define _JBLEN 64 /* size, in longs, of a jmp_buf */
/*
* NOTE: The internal structure of a jmp_buf is *PRIVATE*
* This information is provided as there is software
* that fiddles with this with obtain the stack pointer
* (yes really ! and it's commercial !).
*
* Description of the setjmp buffer
*
* word 0 magic number (dependant on creator)
* 1 - 3 f4 fp register 4
* 4 - 6 f5 fp register 5
* 7 - 9 f6 fp register 6
* 10 - 12 f7 fp register 7
* 13 fpsr fp status register
* 14 r4 register 4
* 15 r5 register 5
* 16 r6 register 6
* 17 r7 register 7
* 18 r8 register 8
* 19 r9 register 9
* 20 r10 register 10 (sl)
* 21 r11 register 11 (fp)
* 22 r12 register 12 (ip)
* 23 r13 register 13 (sp)
* 24 r14 register 14 (lr)
* 25 signal mask (dependant on magic)
* 26 (con't)
* 27 (con't)
* 28 (con't)
*
* The magic number identifies the jmp_buf and
* how the buffer was created as well as providing
* a sanity check.
*
* A side note I should mention - please do not tamper
* with the floating point fields. While they are
* always saved and restored at the moment this cannot
* be guaranteed especially if the compiler happens
* to be generating soft-float code so no fp
* registers will be used.
*
* Whilst this can be seen an encouraging people to
* use the setjmp buffer in this way I think that it
* is for the best then if changes occur compiles will
* break rather than just having new builds falling over
* mysteriously.
*/
#define _JB_MAGIC__SETJMP 0x4278f500
#define _JB_MAGIC_SETJMP 0x4278f501
/* Valid for all jmp_buf's */
#define _JB_MAGIC 0
#define _JB_REG_F4 1
#define _JB_REG_F5 4
#define _JB_REG_F6 7
#define _JB_REG_F7 10
#define _JB_REG_FPSR 13
#define _JB_REG_R4 14
#define _JB_REG_R5 15
#define _JB_REG_R6 16
#define _JB_REG_R7 17
#define _JB_REG_R8 18
#define _JB_REG_R9 19
#define _JB_REG_R10 20
#define _JB_REG_R11 21
#define _JB_REG_R12 22
#define _JB_REG_R13 23
#define _JB_REG_R14 24
/* Only valid with the _JB_MAGIC_SETJMP magic */
#define _JB_SIGMASK 25

64
lib/libc/include/aarch64-openbsd-none/machine/signal.h vendored Normal file
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/* $OpenBSD: signal.h,v 1.2 2017/03/12 17:57:12 kettenis Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Ralph Campbell.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)signal.h 8.1 (Berkeley) 6/10/93
*/
#ifndef _MACHINE_SIGNAL_H_
#define _MACHINE_SIGNAL_H_
#include <sys/cdefs.h>
typedef int sig_atomic_t;
#if __BSD_VISIBLE || __XPG_VISIBLE >= 420
/*
* Information pushed on stack when a signal is delivered.
* This is used by the kernel to restore state following
* execution of the signal handler. It is also made available
* to the handler to allow it to restore state properly if
* a non-standard exit is performed.
*/
struct sigcontext {
int __sc_unused;
int sc_mask; /* signal mask to restore */
unsigned long sc_sp;
unsigned long sc_lr;
unsigned long sc_elr;
unsigned long sc_spsr;
unsigned long sc_x[30];
long sc_cookie;
};
#endif /* __BSD_VISIBLE || __XPG_VISIBLE >= 420 */
#endif /* !_MACHINE_SIGNAL_H_ */

37
lib/libc/include/aarch64-openbsd-none/machine/simplebusvar.h vendored Normal file
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/* $OpenBSD: simplebusvar.h,v 1.1 2023/09/22 01:10:43 jsg Exp $ */
/*
* Copyright (c) 2016 Patrick Wildt <patrick@blueri.se>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
struct simplebus_softc {
struct device sc_dev;
int sc_node;
bus_space_tag_t sc_iot;
bus_dma_tag_t sc_dmat;
int sc_acells;
int sc_scells;
int sc_pacells;
int sc_pscells;
struct bus_space sc_bus;
struct machine_bus_dma_tag sc_dma;
int *sc_ranges;
int sc_rangeslen;
int *sc_dmaranges;
int sc_dmarangeslen;
int sc_early;
int sc_early_nodes[64];
};
extern void simplebus_attach(struct device *, struct device *, void *);

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