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zig/lib/std/Target
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David Rubin 9e17e097e5
make crc32 a featdep of sse4.2 
To my knowledge there isn't an implementation of `sse4.2` that doesn't have `crc32`.
The Clang driver also sets `crc32` to be implicitly enabled when an explicit `-crc32`
wasn't provided. This matches that behaviour.

We need this behaviour to compile libraries like `rocksdb` which currently guard against
`crc32` intrinsics by checking for `sse4.2`.
2024-11-25 01:11:15 -08:00
..
aarch64.zig std.Target: Regenerate CPU models/features based on LLVM 19.1.0. 2024-09-24 11:45:01 +02:00
amdgcn.zig std.Target: Rename amdgpu module to amdgcn. 2024-11-02 10:44:14 +01:00
arc.zig std: update std.builtin.Type fields to follow naming conventions 2024-08-28 08:39:59 +01:00
arm.zig std.Target: Remove armv7k/armv7s. 2024-11-02 10:25:40 +01:00
avr.zig std: update std.builtin.Type fields to follow naming conventions 2024-08-28 08:39:59 +01:00
bpf.zig std: update std.builtin.Type fields to follow naming conventions 2024-08-28 08:39:59 +01:00
csky.zig std: update std.builtin.Type fields to follow naming conventions 2024-08-28 08:39:59 +01:00
hexagon.zig std: update std.builtin.Type fields to follow naming conventions 2024-08-28 08:39:59 +01:00
lanai.zig update_cpu_features: Don't delete the output file if there are no CPU features. 2024-10-03 05:01:14 +02:00
loongarch.zig std.Target: Update CPU models/features for LLVM 19. 2024-09-19 18:20:21 -07:00
m68k.zig std: update std.builtin.Type fields to follow naming conventions 2024-08-28 08:39:59 +01:00
mips.zig std.Target: Update CPU models/features for LLVM 19. 2024-09-19 18:20:21 -07:00
msp430.zig std: update std.builtin.Type fields to follow naming conventions 2024-08-28 08:39:59 +01:00
nvptx.zig std.Target: Update CPU models/features for LLVM 19. 2024-09-19 18:20:21 -07:00
powerpc.zig std.Target: Update CPU models/features for LLVM 19. 2024-09-19 18:20:21 -07:00
propeller.zig Adds new cpu architectures propeller1 and propeller2. (#21563) 2024-10-04 13:53:28 -07:00
Query.zig Provide a detailed message for invalid arch in target triple (#21921) 2024-11-06 03:38:01 +00:00
riscv.zig std.Target: Update CPU models/features for LLVM 19. 2024-09-19 18:20:21 -07:00
s390x.zig std.Target: Update CPU models/features for LLVM 19. 2024-09-19 18:20:21 -07:00
sparc.zig std: update std.builtin.Type fields to follow naming conventions 2024-08-28 08:39:59 +01:00
spirv.zig std: update std.builtin.Type fields to follow naming conventions 2024-08-28 08:39:59 +01:00
ve.zig std: update std.builtin.Type fields to follow naming conventions 2024-08-28 08:39:59 +01:00
wasm.zig std.Target: Update CPU models/features for LLVM 19. 2024-09-19 18:20:21 -07:00
x86.zig make crc32 a featdep of sse4.2 2024-11-25 01:11:15 -08:00
xcore.zig update_cpu_features: Don't delete the output file if there are no CPU features. 2024-10-03 05:01:14 +02:00
xtensa.zig std: update std.builtin.Type fields to follow naming conventions 2024-08-28 08:39:59 +01:00